chip\-to\-chip (full) in projects: freebsd

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/freebsd/lib/libpmc/pmu-events/arch/powerpc/power8/
H A D	cache.json	5 …ed with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as … 6 …ed with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as … 11 …aded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as … 12 …aded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as … 17 …processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) … 18 …processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) … 23 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a demand … 24 …"PublicDescription": "The processor's data cache was reloaded from local core's L2 due to either o… 29 "BriefDescription": "Demand LD - L2 Miss (not L2 hit)", 35 …or's data cache was reloaded from a localtion other than the local core's L2 due to a demand load", [all …]
H A D	other.json	5 …on": "Number of cycles in single lpar mode. All threads in the core are assigned to the same lpar", 11 …"BriefDescription": "Cycles in 2-lpar mode. Threads 0-3 belong to Lpar0 and threads 4-7 belong to … 17 …in 4 LPAR mode. Threads 0-1 belong to lpar0, threads 2-3 belong to lpar1, threads 4-5 belong to lp… 23 …"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for all data … 24 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pum… 36 …to get data sourced, ended up larger than Initial Pump Scope OR Final Pump Scope(Group) got data f… 41 …"BriefDescription": "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for a… 42 …ump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope (Chip) Final pump wa… 65 …ump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the origi… 66 …to get data sourced, ended up larger than Initial Pump Scope(Chip/Group) OR Final Pump Scope(syste… [all …]
H A D	frontend.json	47 "BriefDescription": "Number of I-ERAT reloads", 71 …"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for an instru… 72 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pum… 89 …ed with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as … 90 …ed with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as … 95 …aded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as … 96 …aded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as … 101 …or's Instruction cache was reloaded from another chip's L4 on a different Node or Group (Distant) … 102 …or's Instruction cache was reloaded from another chip's L4 on a different Node or Group (Distant) … 107 …r's Instruction cache was reloaded from another chip's memory on the same Node or Group (Distant) … [all …]
/freebsd/lib/libpmc/pmu-events/arch/powerpc/power9/
H A D	translation.json	15 …che was reloaded with Shared (S) data from another core's L2 on the same chip due to a demand load" 20 "BriefDescription": "Double-Precion or Quad-Precision instruction completed" 25 …able Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) … 35 …he TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as th… 45 …cription": "Finish stall due to a vector fixed point instruction in the execution pipeline. These … 50 "BriefDescription": "LSU Finished a PPC instruction (up to 4 per cycle)" 55 …"BriefDescription": "Cycles during which the marked instruction is next to complete (completion is… 60 … TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as … 65 …"BriefDescription": "Completion stall due to a long latency vector fixed point instruction (divisi… 70 …ssor's data cache was reloaded from a location other than the local core's L2 due to a demand load" [all …]
H A D	marked.json	5 …Number of cycles the marked instruction is experiencing a stall while it is next to complete (NTC)" 10 …"BriefDescription": "A Page Directory Entry was reloaded to a level 1 page walk cache from beyond … 20 …d into the TLB with Shared (S) data from another core's L3 on the same chip due to a data side req… 25 …rocessor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) … 30 …"BriefDescription": "Completion stall by Dcache miss which resolved from remote chip (cache or mem… 35 …ruction cache was reloaded from local core's L2 with dispatch conflict due to an instruction fetch… 45 …"BriefDescription": "A Page Table Entry was reloaded to a level 3 page walk cache from the core's … 50 …"BriefDescription": "A Page Table Entry was reloaded to a level 3 page walk cache from the core's … 55 "BriefDescription": "Completion stall due to ntc flush" 60 …ion": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a marked d… [all …]
H A D	pipeline.json	10 "BriefDescription": "Number of I-ERAT reloads" 25 …se the NTF instruction was a multi-cycle instruction issued to the Decimal Floating Point executio… 30 …ded either shared or modified data from another core's L2/L3 on the same chip due to a marked load" 35 …Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) … 40 …le Entry was loaded into the TLB from local core's L2 without conflict due to a data side request.… 75 …"BriefDescription": "Cycles in which the ICT is completely empty. No itags are assigned to any thr… 80 …into the TLB with Modified (M) data from another core's L2 on the same chip due to a marked data s… 90 …processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) … 95 …into the TLB with Modified (M) data from another core's L2 on the same chip due to a data side req… 100 … is being held at dispatch because it lost arbitration onto the issue pipe to another instruction … [all …]
/freebsd/share/man/man4/
H A D	ahc.4	13 .\" 3. The name of the author may not be used to endorse or promote products 17 .\" IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 .\" NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 37 .Bd -ragged -offset indent 45 Alternatively, to load the driver as a 48 .Bd -literal -offset indent 54 This driver provides access to the 56 bus(es) connected to the Adaptec AIC77xx and AIC78xx 64 .Tn SCSI-Select 72 For systems that store non-volatile settings in a system specific manner [all …]
H A D	acpi_hp.4	14 .\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 .\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 35 .Bd -ragged -offset indent 39 Alternatively, to load the driver as a 42 .Bd -literal -offset indent 48 driver provides support for ACPI-controlled features found on HP laptops 51 The main purpose of this driver is to provide an interface, 63 .Bl -tag -width "subsystem" -offset indent -compact 77 .Bl -tag -width "0xc0" -offset indent -compact 79 WLAN on air status changed to 0 (not on air) [all …]
/freebsd/sys/contrib/device-tree/Bindings/spi/
H A D	spi-sprd-adi.txt	3 ADI is the abbreviation of Anolog-Digital interface, which is used to access 4 analog chip (such as PMIC) from digital chip. ADI controller follows the SPI 5 framework for its hardware implementation is alike to SPI bus and its timing 6 is compatile to SPI timing. 9 48 hardware channels to access analog chip. For 2 software read/write channels, 10 users should set ADI registers to access analog chip. For hardware channels, 11 we can configure them to allow other hardware components to use it independently, 12 which means we can just link one analog chip address to one hardware channel, 13 then users can access the mapped analog chip address by this hardware channel 16 Thus we introduce one property named "sprd,hw-channels" to configure hardware [all …]
H A D	sprd,spi-adi.yaml	1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/spi/sprd,spi-adi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Orson Zhai <orsonzhai@gmail.com> 11 - Baolin Wang <baolin.wang7@gmail.com> 12 - Chunyan Zhang <zhang.lyra@gmail.com> 15 ADI is the abbreviation of Anolog-Digital interface, which is used to access 16 analog chip (such as PMIC) from digital chip. ADI controller follows the SPI 17 framework for its hardware implementation is alike to SPI bus and its timing [all …]
/freebsd/sys/contrib/device-tree/Bindings/display/mediatek/
H A D	mediatek,disp.txt	7 of frame signal are distributed to the other function blocks by a DISP_MUTEX 10 All DISP device tree nodes must be siblings to the central MMSYS_CONFIG node. 19 interface, or writes pixels back to memory. All DISP function blocks have 21 access memory additionally have to list the IOMMU and local arbiter they are 22 connected to. 29 - compatible: "mediatek,<chip>-disp-<function>", one of 30 "mediatek,<chip>-disp-ovl" - overlay (4 layers, blending, csc) 31 "mediatek,<chip>-disp-ovl-2l" - overlay (2 layers, blending, csc) 32 "mediatek,<chip>-disp-rdma" - read DMA / line buffer 33 "mediatek,<chip>-disp-wdma" - write DMA [all …]
/freebsd/sys/contrib/device-tree/Bindings/mtd/
H A D	fsl-upm-nand.txt	1 Freescale Localbus UPM programmed to work with NAND flash 4 - compatible : "fsl,upm-nand". 5 - reg : should specify localbus chip select and size used for the chip. 6 - fsl,upm-addr-offset : UPM pattern offset for the address latch. 7 - fsl,upm-cmd-offset : UPM pattern offset for the command latch. 10 - fsl,upm-addr-line-cs-offsets : address offsets for multi-chip support. 11 The corresponding address lines are used to select the chip. 12 - gpios : may specify optional GPIOs connected to the Ready-Not-Busy pins 13 (R/B#). For multi-chip devices, "n" GPIO definitions are required 14 according to the number of chips. [all …]
H A D	jedec,spi-nor.txt	`4 - #address-cells, #size-cells : Must be present if the device has sub-nodes 6 - compatible : May include a device-specific string consisting of the 7 manufacturer and name of the chip. A list of supported chip 9 Must also include "jedec,spi-nor" for any SPI NOR flash that can 12 Supported chip names: 50 The following chip names have been used historically to 53 m25p05-nonjedec 54 m25p10-nonjedec 55 m25p20-nonjedec 56 m25p40-nonjedec [all …]`
/freebsd/lib/libpmc/pmu-events/arch/s390/cf_zec12/
H A D	extended.json	6 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB… 12 …"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle… 18 …cription": "A directory write to the Level-1 Data cache directory where the returned cache line wa… 24 …tion": "A directory write to the Level-1 Instruction cache directory where the returned cache line… 30 …cription": "A directory write to the Level-1 Data cache directory where the returned cache line wa… 36 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi… 42 …tion": "A directory write to the Level-1 Data cache where the installed cache line was sourced fro… 48 …n": "A directory write to the Level-1 Instruction cache where the installed cache line was sourced… 53 "BriefDescription": "L1D Read-only Exclusive Writes", 54 …to the Level-1 D-Cache where the line was originally in a Read-Only state in the cache but has bee… [all …]
/freebsd/contrib/ofed/libcxgb4/
H A D	t4_chip_type.h	4 * Copyright (c) 2003-2015 Chelsio Communications, Inc. All rights reserved. 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 16 * - Redistributions of source code must retain the above 20 * - Redistributions in binary form must reproduce the above 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 41 /* We code the Chelsio T4 Family "Chip Code" as a tuple: 43 * (Chip Version, Chip Revision) 47 * Chip Version: is T4, T5, etc. 48 * Chip Revision: is the FAB "spin" of the Chip Version. [all …]
/freebsd/sys/dev/wbwd/
H A D	wbwd.c	1 /- 2 SPDX-License-Identifier: BSD-2-Clause 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * With minor abstractions it might be possible to add support for other 33 * different Winbond Super I/O chips as well. Winbond seems to have four 34 * different types of chips, four different ways to get into extended config 75 /* CRF5: Watchdog scale, P20. Mapped to reg_1. / 81 / CRF6: Watchdog Timeout (0 == off). Mapped to reg_timeout. / 84 / CRF7: Watchdog mouse, keyb, force, .. Mapped to reg_2. */ [all …]
/freebsd/sys/contrib/dev/rtw88/
H A D	coex.c	1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 16 const struct rtw_chip_info chip = rtwdev->chip; in rtw_coex_next_rssi_state() local 17 u8 tol = chip in rtw_coex_next_rssi_state() 39 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_limited_tx() local 368 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_write_scbd() local 403 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_read_scbd() local 413 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_check_rfk() local 492 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_monitor_bt_enable() local 527 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_update_wl_link_info() local 708 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_update_bt_link_info() local 808 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_update_wl_ch_info() local 935 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_coex_ctrl_owner() local 983 const struct rtw_chip_info chip = rtwdev->chip; rtw_btc_wltoggle_table_a() local 1067 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_table() local 1137 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_set_tdma() local 1195 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_tdma() local 1528 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_action_coex_all_off() local 1551 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_action_freerun() local 1596 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_action_rf4ce() local 1621 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_action_bt_whql_test() local 1646 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_action_bt_relink() local 1686 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_action_bt_idle() local 1755 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_action_bt_inquiry() local 1855 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_action_bt_game_hid() local 1903 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_action_bt_hfp() local 1934 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_action_bt_hid() local 2017 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_action_bt_a2dp() local 2059 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_action_bt_a2dpsink() local 2098 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_action_bt_pan() local 2135 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_action_bt_a2dp_hid() local 2192 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_action_bt_a2dp_pan() local 2249 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_action_bt_pan_hid() local 2284 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_action_bt_a2dp_pan_hid() local 2318 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_action_wl_under5g() local 2350 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_action_wl_only() local 2374 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_action_wl_native_lps() local 2413 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_action_wl_linkscan() local 2453 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_action_wl_not_connected() local 2530 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_run_coex() local 3004 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_bt_info_notify() local 3272 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_bt_hid_info_notify() local 3362 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_query_bt_hid_list() local 3584 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_get_table_index() local 3620 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_get_tdma_index() local 3738 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_set_coexinfo_hw() local 3912 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_display_coex_info() local [all...]
H A D	mac.c	1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 93 rtw_err(rtwdev, "failed to poll REG_SDIO_HSUS_CTRL[1]"); in rtw_mac_pre_system_cfg() 94 return -ETIMEDOUT; in rtw_mac_pre_system_cfg() 107 return -EINVAL; in rtw_mac_pre_system_cfg() 156 if (cmd->bas in rtw_pwr_cmd_polling() 273 const struct rtw_chip_info chip = rtwdev->chip; rtw_mac_power_switch() local 640 const struct rtw_chip_info chip = rtwdev->chip; download_firmware_to_mem() local 1005 const struct rtw_chip_info chip = rtwdev->chip; __rtw_mac_flush_prio_queue() local 1067 const struct rtw_chip_info chip = rtwdev->chip; txdma_queue_mapping() local 1118 const struct rtw_chip_info chip = rtwdev->chip; set_trx_fifo_info() local 1173 const struct rtw_chip_info chip = rtwdev->chip; __priority_queue_cfg() local 1204 const struct rtw_chip_info chip = rtwdev->chip; __priority_queue_cfg_legacy() local 1230 const struct rtw_chip_info chip = rtwdev->chip; priority_queue_cfg() local 1361 const struct rtw_chip_info *chip = rtwdev->chip; rtw_mac_init() local [all...]
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A D	arm,pl172.txt	5 - compatible: Must be "arm,primecell" and exactly one from 8 - reg: Must contains offset/length value for controller. 10 - #address-cells: Must be 2. The partition number has to be encoded in the 11 first address cell and it may accept values 0..N-1 12 (N - total number of partitions). The second cell is the 15 - #size-cells: Must be set to 1. 17 - ranges: Must contain one or more chip select memory regions. 19 - clocks: Must contain references to controller clocks. 21 - clock-names: Must contain "mpmcclk" and "apb_pclk". 23 - clock-ranges: Empty property indicating that child nodes can inherit [all …]
/freebsd/sys/dev/ath/ath_hal/ar5212/
H A D	ar5212_power.c	1 /- 2 SPDX-License-Identifier: ISC 4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 5 * Copyright (c) 2002-2008 Atheros Communications, Inc. 7 * Permission to use, copy, modify, and/or distribute this software for any 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 29 * Notify Power Mgt is enabled in self-generated frames. 30 * If requested, force chip awake. 32 * Returns A_OK if chip is awake or successfully forced awake. 35 * There is a problem with the chip where sometimes it will not wake up. [all …]
/freebsd/sys/dev/ath/ath_hal/ar5312/
H A D	ar5312_power.c	1 /- 2 SPDX-License-Identifier: ISC 4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 5 * Copyright (c) 2002-2008 Atheros Communications, Inc. 7 * Permission to use, copy, modify, and/or distribute this software for any 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 31 * Notify Power Mgt is enabled in self-generated frames. 32 * If requested, force chip awake. 34 * Returns A_OK if chip is awake or successfully forced awake. 37 * There is a problem with the chip where sometimes it will not wake up. [all …]
/freebsd/sys/contrib/device-tree/Bindings/input/touchscreen/
H A D	pixcir_i2c_ts.txt	4 - compatible: must be "pixcir,pixcir_ts" or "pixcir,pixcir_tangoc" 5 - reg: I2C address of the chip 6 - interrupts: interrupt to which the chip is connected 7 - attb-gpio: GPIO connected to the ATTB line of the chip 8 - touchscreen-size-x: horizontal resolution of touchscreen (in pixels) 9 - touchscreen-size-y: vertical resolution of touchscreen (in pixels) 12 - reset-gpios: GPIO connected to the RESET line of the chip 13 - enable-gpios: GPIO connected to the ENABLE line of the chip 14 - wake-gpios: GPIO connected to the WAKE line of the chip 25 attb-gpio = <&gpf 2 0 2>; [all …]
/freebsd/sys/contrib/device-tree/Bindings/power/reset/
H A D	ltc2952-poweroff.txt	3 This chip is used to externally trigger a system shut down. Once the trigger has 4 been sent, the chip's watchdog has to be reset to gracefully shut down. 9 - compatible: Must contain: "lltc,ltc2952" 10 - watchdog-gpios: phandle + gpio-specifier for the GPIO connected to the 11 chip's watchdog line 12 - kill-gpios: phandle + gpio-specifier for the GPIO connected to the 13 chip's kill line 16 - trigger-gpios: phandle + gpio-specifier for the GPIO connected to the 17 chip's trigger line. If this property is not set, the 18 trigger function is ignored and the chip is kept alive [all …]
/freebsd/sys/contrib/dev/rtw89/
H A D	efuse.c	`1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 24 if (rtwdev->chip->chip_id != RTL8852A) in rtw89_switch_efuse_bank() 40 return -EBUS in rtw89_switch_efuse_bank() [all...]`
/freebsd/sys/dev/ath/ath_hal/ar5416/
H A D	ar5416_power.c	1 /- 2 SPDX-License-Identifier: ISC 4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 5 * Copyright (c) 2002-2008 Atheros Communications, Inc. 7 * Permission to use, copy, modify, and/or distribute this software for any 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 28 * Notify Power Mgt is enabled in self-generated frames. 29 * If requested, force chip awake. 31 * Returns A_OK if chip is awake or successfully forced awake. 34 * There is a problem with the chip where sometimes it will not wake up. [all …]

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