Lines Matching +full:chip +full:- +full:to +full:- +full:chip
1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
16 const struct rtw_chip_info *chip = rtwdev->chip;
17 u8 tol = chip->rssi_tolerance;
39 const struct rtw_chip_info *chip = rtwdev->chip;
40 struct rtw_coex *coex = &rtwdev->coex;
41 struct rtw_coex_stat *coex_stat = &coex->stat;
44 if (!chip->scbd_support)
48 if (coex_stat->wl_tx_limit_en == tx_limit_en &&
49 coex_stat->wl_ampdu_limit_en == ampdu_limit_en)
52 if (!coex_stat->wl_tx_limit_en) {
53 coex_stat->darfrc = rtw_read32(rtwdev, REG_DARFRC);
54 coex_stat->darfrch = rtw_read32(rtwdev, REG_DARFRCH);
55 coex_stat->retry_limit = rtw_read16(rtwdev, REG_RETRY_LIMIT);
58 if (!coex_stat->wl_ampdu_limit_en)
59 coex_stat->ampdu_max_time =
62 coex_stat->wl_tx_limit_en = tx_limit_en;
63 coex_stat->wl_ampdu_limit_en = ampdu_limit_en;
71 /* set queue life time to avoid can't reach tx retry limit
85 rtw_write16(rtwdev, REG_RETRY_LIMIT, coex_stat->retry_limit);
86 rtw_write32(rtwdev, REG_DARFRC, coex_stat->darfrc);
87 rtw_write32(rtwdev, REG_DARFRCH, coex_stat->darfrch);
94 coex_stat->ampdu_max_time);
99 struct rtw_coex *coex = &rtwdev->coex;
100 struct rtw_coex_dm *coex_dm = &coex->dm;
104 if (!coex->under_5g && coex_dm->bt_status != COEX_BTSTATUS_NCON_IDLE) {
114 struct rtw_coex *coex = &rtwdev->coex;
115 struct rtw_coex_dm *coex_dm = &coex->dm;
116 struct rtw_coex_stat *coex_stat = &coex->stat;
117 struct rtw_efuse *efuse = &rtwdev->efuse;
121 if (coex_stat->bt_disabled)
124 if (efuse->share_ant || ant_distance <= 5 || !coex_stat->wl_gl_busy)
127 if (ant_distance >= 40 || coex_stat->bt_hid_pair_num >= 2)
131 if (COEX_RSSI_HIGH(coex_dm->wl_rssi_state[1]) &&
132 COEX_RSSI_HIGH(coex_dm->bt_rssi_state[0]))
135 if (coex_stat->wl_tput_dir == COEX_WL_TPUT_TX)
136 bt_rssi = coex_dm->bt_rssi_state[0];
138 bt_rssi = coex_dm->bt_rssi_state[1];
140 if (COEX_RSSI_HIGH(coex_dm->wl_rssi_state[3]) &&
142 coex_stat->cnt_wl[COEX_CNT_WL_SCANAP] <= 5)
150 struct rtw_coex *coex = &rtwdev->coex;
151 struct rtw_coex_stat *coex_stat = &coex->stat;
160 coex_stat->cnt_wl[COEX_CNT_WL_5MS_NOEXTEND] = 0;
162 coex_stat->wl_slot_extend = enable;
168 struct rtw_coex *coex = &rtwdev->coex;
169 struct rtw_coex_stat *coex_stat = &coex->stat;
171 if (coex->manual_control || coex->stop_dm)
175 if (coex_stat->tdma_timer_base == 3 && coex_stat->wl_slot_extend) {
177 "[BTCoex], set h2c 0x69 opcode 12 to turn off 5ms WL slot extend!!\n");
182 if (coex_stat->wl_slot_extend && coex_stat->wl_force_lps_ctrl &&
183 !coex_stat->wl_cck_lock_ever) {
184 if (coex_stat->wl_fw_dbg_info[7] <= 5)
185 coex_stat->cnt_wl[COEX_CNT_WL_5MS_NOEXTEND]++;
187 coex_stat->cnt_wl[COEX_CNT_WL_5MS_NOEXTEND] = 0;
191 coex_stat->cnt_wl[COEX_CNT_WL_5MS_NOEXTEND]);
193 if (coex_stat->cnt_wl[COEX_CNT_WL_5MS_NOEXTEND] == 7) {
195 "[BTCoex], set h2c 0x69 opcode 12 to turn off 5ms WL slot extend!!\n");
198 } else if (!coex_stat->wl_slot_extend && coex_stat->wl_cck_lock) {
200 "[BTCoex], set h2c 0x69 opcode 12 to turn on 5ms WL slot extend!!\n");
208 struct rtw_coex *coex = &rtwdev->coex;
209 struct rtw_coex_stat *coex_stat = &coex->stat;
210 struct rtw_coex_dm *coex_dm = &coex->dm;
214 if (coex_stat->wl_coex_mode != COEX_WLINK_2G1PORT &&
215 coex_stat->wl_coex_mode != COEX_WLINK_2GFREE)
218 if (coex_dm->bt_status == COEX_BTSTATUS_INQ_PAGE ||
219 coex_stat->bt_setup_link) {
220 coex_stat->wl_cck_lock = false;
221 coex_stat->wl_cck_lock_pre = false;
225 if (coex_stat->wl_rx_rate <= COEX_CCK_2 ||
226 coex_stat->wl_rts_rx_rate <= COEX_CCK_2)
229 if (coex_stat->wl_connected && coex_stat->wl_gl_busy &&
230 COEX_RSSI_HIGH(coex_dm->wl_rssi_state[3]) &&
231 (coex_dm->bt_status == COEX_BTSTATUS_ACL_BUSY ||
232 coex_dm->bt_status == COEX_BTSTATUS_ACL_SCO_BUSY ||
233 coex_dm->bt_status == COEX_BTSTATUS_SCO_BUSY)) {
235 coex_stat->wl_cck_lock = true;
241 coex_stat->wl_cck_lock = false;
247 coex_stat->wl_cck_lock = false;
251 if (coex_stat->wl_cck_lock && !coex_stat->wl_cck_lock_pre)
252 ieee80211_queue_delayed_work(rtwdev->hw, &coex->wl_ccklock_work,
255 coex_stat->wl_cck_lock_pre = coex_stat->wl_cck_lock;
260 struct rtw_coex *coex = &rtwdev->coex;
261 struct rtw_coex_stat *coex_stat = &coex->stat;
262 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
267 cnt_cck = dm_info->cck_ok_cnt + dm_info->cck_err_cnt;
269 if (!coex_stat->wl_gl_busy && !wl_cck_lock) {
271 if (coex_stat->cnt_wl[COEX_CNT_WL_NOISY2] < 5)
272 coex_stat->cnt_wl[COEX_CNT_WL_NOISY2]++;
274 if (coex_stat->cnt_wl[COEX_CNT_WL_NOISY2] == 5) {
275 coex_stat->cnt_wl[COEX_CNT_WL_NOISY0] = 0;
276 coex_stat->cnt_wl[COEX_CNT_WL_NOISY1] = 0;
279 if (coex_stat->cnt_wl[COEX_CNT_WL_NOISY0] < 5)
280 coex_stat->cnt_wl[COEX_CNT_WL_NOISY0]++;
282 if (coex_stat->cnt_wl[COEX_CNT_WL_NOISY0] == 5) {
283 coex_stat->cnt_wl[COEX_CNT_WL_NOISY1] = 0;
284 coex_stat->cnt_wl[COEX_CNT_WL_NOISY2] = 0;
287 if (coex_stat->cnt_wl[COEX_CNT_WL_NOISY1] < 5)
288 coex_stat->cnt_wl[COEX_CNT_WL_NOISY1]++;
290 if (coex_stat->cnt_wl[COEX_CNT_WL_NOISY1] == 5) {
291 coex_stat->cnt_wl[COEX_CNT_WL_NOISY0] = 0;
292 coex_stat->cnt_wl[COEX_CNT_WL_NOISY2] = 0;
296 if (coex_stat->cnt_wl[COEX_CNT_WL_NOISY2] == 5)
297 coex_stat->wl_noisy_level = 2;
298 else if (coex_stat->cnt_wl[COEX_CNT_WL_NOISY1] == 5)
299 coex_stat->wl_noisy_level = 1;
301 coex_stat->wl_noisy_level = 0;
304 coex_stat->wl_noisy_level);
310 struct rtw_coex *coex = &rtwdev->coex;
311 struct rtw_coex_stat *coex_stat = &coex->stat;
314 u16 tbtt_interval = coex_stat->wl_beacon_interval;
316 if (coex_stat->tdma_timer_base == type)
319 coex_stat->tdma_timer_base = type;
327 para[1] = PARA1_H2C69_TDMA_4SLOT; /* 4-slot */
337 times--;
350 /* no 5ms_wl_slot_extend for 4-slot mode */
351 if (coex_stat->tdma_timer_base == 3)
368 const struct rtw_chip_info *chip = rtwdev->chip;
369 struct rtw_coex *coex = &rtwdev->coex;
370 struct rtw_coex_stat *coex_stat = &coex->stat;
373 if (!chip->scbd_support)
376 val |= coex_stat->score_board;
381 if (!chip->new_scbd10_def && (bitpos & COEX_SCBD_FIX2M)) {
393 if (val != coex_stat->score_board) {
394 coex_stat->score_board = val;
403 const struct rtw_chip_info *chip = rtwdev->chip;
405 if (!chip->scbd_support)
413 const struct rtw_chip_info *chip = rtwdev->chip;
414 struct rtw_coex *coex = &rtwdev->coex;
415 struct rtw_coex_stat *coex_stat = &coex->stat;
416 struct rtw_coex_rfe *coex_rfe = &coex->rfe;
421 if (coex_rfe->wlg_at_btg && chip->scbd_support &&
422 coex_stat->bt_iqk_state != 0xff) {
445 coex_stat->bt_iqk_state = 0xff;
451 struct rtw_coex *coex = &rtwdev->coex;
452 struct rtw_coex_stat *coex_stat = &coex->stat;
454 if (coex_stat->bt_disabled)
469 struct rtw_coex *coex = &rtwdev->coex;
470 struct rtw_coex_stat *coex_stat = &coex->stat;
474 coex_stat->hi_pri_tx = FIELD_GET(MASKLWORD, tmp);
475 coex_stat->hi_pri_rx = FIELD_GET(MASKHWORD, tmp);
478 coex_stat->lo_pri_tx = FIELD_GET(MASKLWORD, tmp);
479 coex_stat->lo_pri_rx = FIELD_GET(MASKHWORD, tmp);
485 "[BTCoex], Hi-Pri Rx/Tx: %d/%d, Lo-Pri Rx/Tx: %d/%d\n",
486 coex_stat->hi_pri_rx, coex_stat->hi_pri_tx,
487 coex_stat->lo_pri_rx, coex_stat->lo_pri_tx);
492 const struct rtw_chip_info *chip = rtwdev->chip;
493 struct rtw_coex *coex = &rtwdev->coex;
494 struct rtw_coex_stat *coex_stat = &coex->stat;
495 struct rtw_coex_dm *coex_dm = &coex->dm;
500 if (chip->scbd_support) {
504 if (coex_stat->hi_pri_tx == 0 && coex_stat->hi_pri_rx == 0 &&
505 coex_stat->lo_pri_tx == 0 && coex_stat->lo_pri_rx == 0)
508 if (coex_stat->hi_pri_tx == 0xffff && coex_stat->hi_pri_rx == 0xffff &&
509 coex_stat->lo_pri_tx == 0xffff && coex_stat->lo_pri_rx == 0xffff)
513 coex_stat->bt_disable_cnt = 0;
516 coex_stat->bt_disable_cnt++;
517 if (coex_stat->bt_disable_cnt >= 10)
522 if (coex_stat->bt_disabled != bt_disabled) {
524 "[BTCoex], BT state changed (%d) -> (%d)\n",
525 coex_stat->bt_disabled, bt_disabled);
527 coex_stat->bt_disabled = bt_disabled;
528 coex_stat->bt_ble_scan_type = 0;
529 coex_dm->cur_bt_lna_lvl = 0;
531 if (!coex_stat->bt_disabled) {
532 coex_stat->bt_reenable = true;
533 ieee80211_queue_delayed_work(rtwdev->hw,
534 &coex->bt_reenable_work,
537 coex_stat->bt_mailbox_reply = false;
538 coex_stat->bt_reenable = false;
545 const struct rtw_chip_info *chip = rtwdev->chip;
546 struct rtw_coex *coex = &rtwdev->coex;
547 struct rtw_coex_stat *coex_stat = &coex->stat;
548 struct rtw_coex_dm *coex_dm = &coex->dm;
549 struct rtw_traffic_stats *stats = &rtwdev->stats;
558 scan = test_bit(RTW_FLAG_SCANNING, rtwdev->flags);
559 coex_stat->wl_connected = !!rtwdev->sta_cnt;
561 wl_busy = test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags);
562 if (wl_busy != coex_stat->wl_gl_busy) {
564 coex_stat->wl_gl_busy = true;
566 ieee80211_queue_delayed_work(rtwdev->hw,
567 &coex->wl_remain_work,
571 if (stats->tx_throughput > stats->rx_throughput)
572 coex_stat->wl_tput_dir = COEX_WL_TPUT_TX;
574 coex_stat->wl_tput_dir = COEX_WL_TPUT_RX;
578 coex_stat->wl_linkscan_proc = true;
580 coex_stat->wl_linkscan_proc = false;
585 rssi_state = coex_dm->wl_rssi_state[i];
586 rssi_step = chip->wl_rssi_step[i];
587 rssi = rtwdev->dm_info.min_rssi;
590 coex_dm->wl_rssi_state[i] = rssi_state;
593 if (coex_stat->wl_linkscan_proc || coex_stat->wl_hi_pri_task1 ||
594 coex_stat->wl_hi_pri_task2 || coex_stat->wl_gl_busy)
613 if (rtwdev->hal.current_band_type == RTW_BAND_5G)
620 coex->under_5g = is_5G;
628 pkt_offset = *((u32 *)resp->cb);
629 c2h = (struct rtw_c2h_cmd *)(resp->data + pkt_offset);
631 return c2h->payload;
636 struct rtw_coex *coex = &rtwdev->coex;
644 skb_queue_tail(&coex->queue, skb);
645 wake_up(&coex->wait);
651 struct rtw_coex *coex = &rtwdev->coex;
654 lockdep_assert_held(&rtwdev->mutex);
658 if (!wait_event_timeout(coex->wait, !skb_queue_empty(&coex->queue),
664 skb_resp = skb_dequeue(&coex->queue);
666 rtw_err(rtwdev, "failed to get coex info response\n");
726 const struct rtw_chip_info *chip = rtwdev->chip;
727 struct rtw_coex *coex = &rtwdev->coex;
728 struct rtw_coex_stat *coex_stat = &coex->stat;
729 struct rtw_coex_dm *coex_dm = &coex->dm;
737 rssi_state = coex_dm->bt_rssi_state[i];
738 rssi_step = chip->bt_rssi_step[i];
739 rssi = coex_stat->bt_rssi;
742 coex_dm->bt_rssi_state[i] = rssi_state;
745 if (coex_stat->bt_ble_scan_en &&
746 coex_stat->cnt_bt[COEX_CNT_BT_INFOUPDATE] % 3 == 0) {
750 coex_stat->bt_ble_scan_type = scan_type;
751 if ((coex_stat->bt_ble_scan_type & 0x1) == 0x1)
752 coex_stat->bt_init_scan = true;
754 coex_stat->bt_init_scan = false;
758 coex_stat->bt_profile_num = 0;
761 if (!(coex_stat->bt_info_lb2 & COEX_INFO_CONNECTION)) {
762 coex_stat->bt_link_exist = false;
763 coex_stat->bt_pan_exist = false;
764 coex_stat->bt_a2dp_exist = false;
765 coex_stat->bt_hid_exist = false;
766 coex_stat->bt_hfp_exist = false;
769 coex_stat->bt_link_exist = true;
770 if (coex_stat->bt_info_lb2 & COEX_INFO_FTP) {
771 coex_stat->bt_pan_exist = true;
772 coex_stat->bt_profile_num++;
774 coex_stat->bt_pan_exist = false;
777 if (coex_stat->bt_info_lb2 & COEX_INFO_A2DP) {
778 coex_stat->bt_a2dp_exist = true;
779 coex_stat->bt_profile_num++;
781 coex_stat->bt_a2dp_exist = false;
784 if (coex_stat->bt_info_lb2 & COEX_INFO_HID) {
785 coex_stat->bt_hid_exist = true;
786 coex_stat->bt_profile_num++;
788 coex_stat->bt_hid_exist = false;
791 if (coex_stat->bt_info_lb2 & COEX_INFO_SCO_ESCO) {
792 coex_stat->bt_hfp_exist = true;
793 coex_stat->bt_profile_num++;
795 coex_stat->bt_hfp_exist = false;
799 if (coex_stat->bt_info_lb2 & COEX_INFO_INQ_PAGE) {
800 coex_dm->bt_status = COEX_BTSTATUS_INQ_PAGE;
801 } else if (!(coex_stat->bt_info_lb2 & COEX_INFO_CONNECTION)) {
802 coex_dm->bt_status = COEX_BTSTATUS_NCON_IDLE;
803 coex_stat->bt_multi_link_remain = false;
804 } else if (coex_stat->bt_info_lb2 == COEX_INFO_CONNECTION) {
805 coex_dm->bt_status = COEX_BTSTATUS_CON_IDLE;
806 } else if ((coex_stat->bt_info_lb2 & COEX_INFO_SCO_ESCO) ||
807 (coex_stat->bt_info_lb2 & COEX_INFO_SCO_BUSY)) {
808 if (coex_stat->bt_info_lb2 & COEX_INFO_ACL_BUSY)
809 coex_dm->bt_status = COEX_BTSTATUS_ACL_SCO_BUSY;
811 coex_dm->bt_status = COEX_BTSTATUS_SCO_BUSY;
812 } else if (coex_stat->bt_info_lb2 & COEX_INFO_ACL_BUSY) {
813 coex_dm->bt_status = COEX_BTSTATUS_ACL_BUSY;
815 coex_dm->bt_status = COEX_BTSTATUS_MAX;
818 coex_stat->cnt_bt[COEX_CNT_BT_INFOUPDATE]++;
821 rtw_coex_get_bt_status_string(coex_dm->bt_status));
826 const struct rtw_chip_info *chip = rtwdev->chip;
827 struct rtw_efuse *efuse = &rtwdev->efuse;
828 struct rtw_coex_dm *coex_dm = &rtwdev->coex.dm;
829 struct rtw_coex_stat *coex_stat = &rtwdev->coex.stat;
835 bw = rtwdev->hal.current_band_width;
838 center_chan = rtwdev->hal.current_channel;
841 (efuse->share_ant && center_chan <= 14 &&
842 coex_stat->wl_coex_mode != COEX_WLINK_2GFREE)) {
850 bw = chip->bt_afh_span_bw40;
852 bw = chip->bt_afh_span_bw20;
853 } else if (chip->afh_5g_num > 1) {
854 for (i = 0; i < chip->afh_5g_num; i++) {
855 if (center_chan == chip->afh_5g[i].wl_5g_ch) {
857 center_chan = chip->afh_5g[i].bt_skip_ch;
858 bw = chip->afh_5g[i].bt_skip_span;
864 coex_dm->wl_ch_info[0] = link;
865 coex_dm->wl_ch_info[1] = center_chan;
866 coex_dm->wl_ch_info[2] = bw;
876 struct rtw_coex *coex = &rtwdev->coex;
877 struct rtw_coex_dm *coex_dm = &coex->dm;
879 if (bt_pwr_dec_lvl == coex_dm->cur_bt_pwr_lvl)
882 coex_dm->cur_bt_pwr_lvl = bt_pwr_dec_lvl;
889 struct rtw_coex *coex = &rtwdev->coex;
890 struct rtw_coex_dm *coex_dm = &coex->dm;
892 if (bt_lna_lvl == coex_dm->cur_bt_lna_lvl)
895 coex_dm->cur_bt_lna_lvl = bt_lna_lvl;
911 struct rtw_coex *coex = &rtwdev->coex;
912 struct rtw_coex_stat *coex_stat = &coex->stat;
915 if (coex->freerun && coex_stat->cnt_wl[COEX_CNT_WL_SCANAP] <= 5)
929 rtw_err(rtwdev, "failed to read indirect register\n");
947 rtw_err(rtwdev, "failed to write indirect register\n");
953 const struct rtw_chip_info *chip = rtwdev->chip;
954 const struct rtw_hw_reg *btg_reg = chip->btg_reg;
960 rtw_write8_set(rtwdev, btg_reg->addr, btg_reg->mask);
965 rtw_write8_clr(rtwdev, btg_reg->addr, btg_reg->mask);
971 if (!rtwdev->chip->ltecoex_addr)
980 if (!rtwdev->chip->ltecoex_addr)
989 struct rtw_coex_stat *coex_stat = &rtwdev->coex.stat;
991 if (!force && state == coex_stat->wl_mimo_ps)
994 coex_stat->wl_mimo_ps = state;
998 rtw_coex_update_wl_ch_info(rtwdev, (u8)coex_stat->wl_connected);
1007 const struct rtw_chip_info *chip = rtwdev->chip;
1008 struct rtw_efuse *efuse = &rtwdev->efuse;
1016 if (efuse->share_ant) {
1017 if (table_case < chip->table_sant_num)
1018 table_wl = chip->table_sant[table_case].wl;
1020 if (table_case < chip->table_nsant_num)
1021 table_wl = chip->table_nsant[table_case].wl;
1024 /* tell WL FW WL slot toggle table-A*/
1042 struct rtw_coex *coex = &rtwdev->coex;
1043 struct rtw_coex_stat *coex_stat = &coex->stat;
1054 coex_stat->wl_toggle_interval = interval;
1057 coex_stat->wl_toggle_para[i] = cur_h2c_para[i];
1071 struct rtw_coex *coex = &rtwdev->coex;
1072 struct rtw_coex_dm *coex_dm = &coex->dm;
1075 if (!force && coex_dm->reason != COEX_RSN_LPS) {
1091 const struct rtw_chip_info *chip = rtwdev->chip;
1092 struct rtw_coex *coex = &rtwdev->coex;
1093 struct rtw_coex_dm *coex_dm = &coex->dm;
1094 struct rtw_efuse *efuse = &rtwdev->efuse;
1095 struct rtw_coex_stat *coex_stat = &coex->stat;
1097 coex_dm->cur_table = type;
1099 rtw_dbg(rtwdev, RTW_DBG_COEX, "[BTCoex], Coex_Table - %d\n", type);
1101 if (efuse->share_ant) {
1102 if (type < chip->table_sant_num)
1104 chip->table_sant[type].bt,
1105 chip->table_sant[type].wl);
1107 type = type - 100;
1108 if (type < chip->table_nsant_num)
1110 chip->table_nsant[type].bt,
1111 chip->table_nsant[type].wl);
1113 if (coex_stat->wl_slot_toggle_change)
1119 struct rtw_coex *coex = &rtwdev->coex;
1121 if (coex->manual_control || coex->stop_dm)
1130 struct rtw_coex *coex = &rtwdev->coex;
1131 struct rtw_coex_stat *coex_stat = &coex->stat;
1134 lps_mode = rtwdev->lps_conf.mode;
1138 /* recover to original 32k low power setting */
1139 coex_stat->wl_force_lps_ctrl = false;
1145 coex_stat->wl_force_lps_ctrl = true;
1161 const struct rtw_chip_info *chip = rtwdev->chip;
1162 struct rtw_coex *coex = &rtwdev->coex;
1163 struct rtw_coex_dm *coex_dm = &coex->dm;
1164 struct rtw_coex_stat *coex_stat = &coex->stat;
1181 coex_stat->wl_coex_mode == COEX_WLINK_2GFREE) {
1186 if (chip->pstdma_type == COEX_PSTDMA_FORCE_LPSOFF)
1200 coex_dm->ps_tdma_para[0] = byte1;
1201 coex_dm->ps_tdma_para[1] = byte2;
1202 coex_dm->ps_tdma_para[2] = byte3;
1203 coex_dm->ps_tdma_para[3] = byte4;
1204 coex_dm->ps_tdma_para[4] = byte5;
1209 coex_stat->wl_slot_toggle = true;
1210 coex_stat->wl_slot_toggle_change = false;
1212 coex_stat->wl_slot_toggle_change = coex_stat->wl_slot_toggle;
1213 coex_stat->wl_slot_toggle = false;
1219 const struct rtw_chip_info *chip = rtwdev->chip;
1220 struct rtw_coex *coex = &rtwdev->coex;
1221 struct rtw_coex_dm *coex_dm = &coex->dm;
1222 struct rtw_coex_stat *coex_stat = &coex->stat;
1223 struct rtw_efuse *efuse = &rtwdev->efuse;
1228 if (tcase & TDMA_4SLOT) /* 4-slot (50ms) mode */
1237 if (!force && turn_on == coex_dm->cur_ps_tdma_on &&
1238 type == coex_dm->cur_ps_tdma) {
1241 (coex_dm->cur_ps_tdma_on ? "on" : "off"),
1242 coex_dm->cur_ps_tdma);
1246 wl_busy = test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags);
1248 if ((coex_stat->bt_a2dp_exist &&
1249 (coex_stat->bt_inq_remain || coex_stat->bt_multi_link)) ||
1256 coex_dm->cur_ps_tdma_on = turn_on;
1257 coex_dm->cur_ps_tdma = type;
1259 if (efuse->share_ant) {
1260 if (type < chip->tdma_sant_num)
1262 chip->tdma_sant[type].para[0],
1263 chip->tdma_sant[type].para[1],
1264 chip->tdma_sant[type].para[2],
1265 chip->tdma_sant[type].para[3],
1266 chip->tdma_sant[type].para[4]);
1268 n = type - 100;
1269 if (n < chip->tdma_nsant_num)
1271 chip->tdma_nsant[n].para[0],
1272 chip->tdma_nsant[n].para[1],
1273 chip->tdma_nsant[n].para[2],
1274 chip->tdma_nsant[n].para[3],
1275 chip->tdma_nsant[n].para[4]);
1285 struct rtw_coex *coex = &rtwdev->coex;
1286 struct rtw_coex_stat *coex_stat = &coex->stat;
1287 struct rtw_coex_rfe *coex_rfe = &coex->rfe;
1288 struct rtw_coex_dm *coex_dm = &coex->dm;
1292 if (!force && coex_dm->cur_ant_pos_type == phase)
1295 coex_dm->cur_ant_pos_type = phase;
1301 "[BTCoex], coex_stat->bt_disabled = 0x%x\n",
1302 coex_stat->bt_disabled);
1307 "[BTCoex], %s() - PHASE_COEX_POWERON\n", __func__);
1308 /* set path control owner to BT at power-on */
1309 if (coex_stat->bt_disabled)
1319 "[BTCoex], %s() - PHASE_COEX_INIT\n", __func__);
1320 if (coex_stat->bt_disabled) {
1321 /* set GNT_BT to SW low */
1324 /* set GNT_WL to SW high */
1327 /* set GNT_BT to SW high */
1330 /* set GNT_WL to SW low */
1334 /* set path control owner to wl at initial step */
1342 "[BTCoex], %s() - PHASE_WLANONLY_INIT\n", __func__);
1343 /* set GNT_BT to SW Low */
1346 /* set GNT_WL to SW high */
1349 /* set path control owner to wl at initial step */
1357 "[BTCoex], %s() - PHASE_WLAN_OFF\n", __func__);
1358 /* set path control owner to BT */
1366 "[BTCoex], %s() - PHASE_2G_RUNTIME\n", __func__);
1367 /* set GNT_BT to PTA */
1370 /* set GNT_WL to PTA */
1373 /* set path control owner to wl at runtime step */
1381 "[BTCoex], %s() - PHASE_5G_RUNTIME\n", __func__);
1383 /* set GNT_BT to HW PTA */
1386 /* set GNT_WL to SW high */
1389 /* set path control owner to wl at runtime step */
1397 "[BTCoex], %s() - PHASE_2G_FREERUN\n", __func__);
1399 /* set GNT_BT to HW PTA */
1402 /* Set GNT_WL to SW high */
1405 /* set path control owner to wl at runtime step */
1413 "[BTCoex], %s() - PHASE_2G_WLBT\n", __func__);
1414 /* set GNT_BT to HW PTA */
1417 /* Set GNT_WL to HW PTA */
1420 /* set path control owner to wl at runtime step */
1432 coex_rfe->ant_switch_exist)
1485 struct rtw_coex *coex = &rtwdev->coex;
1486 struct rtw_coex_stat *coex_stat = &coex->stat;
1490 if (coex_stat->bt_hfp_exist)
1492 if (coex_stat->bt_hid_exist)
1494 if (coex_stat->bt_a2dp_exist)
1496 if (coex_stat->bt_pan_exist)
1529 if (coex_stat->bt_multi_link) {
1530 if (coex_stat->bt_hid_pair_num > 0)
1552 const struct rtw_chip_info *chip = rtwdev->chip;
1553 struct rtw_efuse *efuse = &rtwdev->efuse;
1557 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
1559 if (efuse->share_ant) {
1560 /* Shared-Ant */
1564 /* Non-Shared-Ant */
1575 const struct rtw_chip_info *chip = rtwdev->chip;
1576 struct rtw_coex *coex = &rtwdev->coex;
1577 struct rtw_coex_stat *coex_stat = &coex->stat;
1578 struct rtw_coex_dm *coex_dm = &coex->dm;
1579 struct rtw_efuse *efuse = &rtwdev->efuse;
1585 if (efuse->share_ant)
1588 coex->freerun = true;
1597 if (COEX_RSSI_HIGH(coex_dm->wl_rssi_state[0]))
1599 else if (COEX_RSSI_HIGH(coex_dm->wl_rssi_state[1]))
1601 else if (COEX_RSSI_HIGH(coex_dm->wl_rssi_state[2]))
1606 if (level > chip->wl_rf_para_num - 1)
1607 level = chip->wl_rf_para_num - 1;
1609 if (coex_stat->wl_tput_dir == COEX_WL_TPUT_TX)
1610 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_tx[level]);
1612 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[level]);
1620 const struct rtw_chip_info *chip = rtwdev->chip;
1621 struct rtw_efuse *efuse = &rtwdev->efuse;
1627 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
1629 if (efuse->share_ant) {
1630 /* Shared-Ant */
1634 /* Non-Shared-Ant */
1645 const struct rtw_chip_info *chip = rtwdev->chip;
1646 struct rtw_efuse *efuse = &rtwdev->efuse;
1652 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
1654 if (efuse->share_ant) {
1655 /* Shared-Ant */
1659 /* Non-Shared-Ant */
1670 const struct rtw_chip_info *chip = rtwdev->chip;
1671 struct rtw_coex *coex = &rtwdev->coex;
1672 struct rtw_coex_stat *coex_stat = &coex->stat;
1673 struct rtw_efuse *efuse = &rtwdev->efuse;
1680 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
1682 if (efuse->share_ant) { /* Shared-Ant */
1683 if (coex_stat->wl_gl_busy) {
1685 if (coex_stat->bt_hid_exist &&
1686 coex_stat->bt_profile_num == 1) {
1696 } else { /* Non-Shared-Ant */
1697 if (coex_stat->wl_gl_busy)
1710 const struct rtw_chip_info *chip = rtwdev->chip;
1711 struct rtw_coex *coex = &rtwdev->coex;
1712 struct rtw_coex_stat *coex_stat = &coex->stat;
1713 struct rtw_coex_dm *coex_dm = &coex->dm;
1714 struct rtw_efuse *efuse = &rtwdev->efuse;
1715 struct rtw_coex_rfe *coex_rfe = &coex->rfe;
1719 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
1721 if (coex_rfe->ant_switch_with_bt &&
1722 coex_dm->bt_status == COEX_BTSTATUS_NCON_IDLE) {
1723 if (efuse->share_ant &&
1724 COEX_RSSI_HIGH(coex_dm->wl_rssi_state[3]) &&
1725 coex_stat->wl_gl_busy) {
1728 } else if (!efuse->share_ant) {
1741 if (efuse->share_ant) {
1742 /* Shared-Ant */
1743 if (!coex_stat->wl_gl_busy) {
1746 } else if (coex_dm->bt_status == COEX_BTSTATUS_NCON_IDLE) {
1749 if (coex_stat->lo_pri_rx + coex_stat->lo_pri_tx > 250)
1758 /* Non-Shared-Ant */
1759 if (!coex_stat->wl_gl_busy) {
1762 } else if ((coex_stat->bt_ble_scan_type & 0x2) &&
1763 coex_dm->bt_status == COEX_BTSTATUS_NCON_IDLE) {
1779 const struct rtw_chip_info *chip = rtwdev->chip;
1780 struct rtw_coex *coex = &rtwdev->coex;
1781 struct rtw_coex_stat *coex_stat = &coex->stat;
1782 struct rtw_efuse *efuse = &rtwdev->efuse;
1789 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
1791 if (coex_stat->wl_linkscan_proc || coex_stat->wl_hi_pri_task1 ||
1792 coex_stat->wl_hi_pri_task2)
1795 if (efuse->share_ant) {
1796 /* Shared-Ant */
1799 "[BTCoex], bt inq/page + wifi hi-pri task\n");
1802 if (coex_stat->bt_profile_num > 0)
1804 else if (coex_stat->wl_hi_pri_task1)
1806 else if (!coex_stat->bt_page)
1810 } else if (coex_stat->wl_gl_busy) {
1813 if (coex_stat->bt_profile_num == 0) {
1816 } else if (coex_stat->bt_profile_num == 1 &&
1817 !coex_stat->bt_a2dp_exist) {
1826 } else if (coex_stat->wl_connected) {
1833 "[BTCoex], bt inq/page + wifi not-connected\n");
1838 /* Non_Shared-Ant */
1841 "[BTCoex], bt inq/page + wifi hi-pri task\n");
1844 if (coex_stat->bt_profile_num > 0)
1846 else if (coex_stat->wl_hi_pri_task1)
1848 else if (!coex_stat->bt_page)
1852 } else if (coex_stat->wl_gl_busy) {
1857 } else if (coex_stat->wl_connected) {
1864 "[BTCoex], bt inq/page + wifi not-connected\n");
1871 wl_hi_pri, coex_stat->bt_page);
1879 const struct rtw_chip_info *chip = rtwdev->chip;
1880 struct rtw_coex *coex = &rtwdev->coex;
1881 struct rtw_coex_stat *coex_stat = &coex->stat;
1882 struct rtw_efuse *efuse = &rtwdev->efuse;
1883 struct rtw_coex_dm *coex_dm = &coex->dm;
1889 if (efuse->share_ant) {
1890 coex_stat->wl_coex_mode = COEX_WLINK_2GFREE;
1891 if (coex_stat->bt_whck_test)
1893 else if (coex_stat->wl_linkscan_proc || coex_stat->bt_hid_exist)
1895 else if (coex_stat->bt_setup_link || coex_stat->bt_inq_page)
1897 else if (coex_stat->bt_a2dp_exist)
1904 if (COEX_RSSI_HIGH(coex_dm->wl_rssi_state[1]))
1912 if (coex_stat->wl_coex_mode == COEX_WLINK_2GFREE) {
1913 if (coex_stat->wl_tput_dir == COEX_WL_TPUT_TX)
1914 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_tx[6]);
1916 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[5]);
1918 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
1927 const struct rtw_chip_info *chip = rtwdev->chip;
1928 struct rtw_coex *coex = &rtwdev->coex;
1929 struct rtw_coex_stat *coex_stat = &coex->stat;
1930 struct rtw_efuse *efuse = &rtwdev->efuse;
1935 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
1937 if (efuse->share_ant) {
1938 /* Shared-Ant */
1942 /* Non-Shared-Ant */
1943 if (coex_stat->bt_multi_link) {
1958 const struct rtw_chip_info *chip = rtwdev->chip;
1959 struct rtw_coex *coex = &rtwdev->coex;
1960 struct rtw_coex_stat *coex_stat = &coex->stat;
1961 struct rtw_efuse *efuse = &rtwdev->efuse;
1968 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
1970 if (efuse->share_ant) {
1971 /* Shared-Ant */
1972 if (coex_stat->bt_ble_exist) {
1974 if (coex_stat->cnt_wl[COEX_CNT_WL_SCANAP] > 5) {
1983 if (coex_stat->bt_profile_num == 1 &&
1984 (coex_stat->bt_multi_link ||
1985 (coex_stat->lo_pri_rx +
1986 coex_stat->lo_pri_tx > 360) ||
1987 coex_stat->bt_slave ||
1992 } else if (coex_stat->bt_a2dp_active) {
1995 } else if (coex_stat->bt_418_hid_exist &&
1996 coex_stat->wl_gl_busy) {
2001 } else if (coex_stat->bt_ble_hid_exist &&
2002 coex_stat->wl_gl_busy) {
2011 /* Non-Shared-Ant */
2012 if (coex_stat->bt_ble_exist) {
2014 if (coex_stat->cnt_wl[COEX_CNT_WL_SCANAP] > 5) {
2021 } else if (coex_stat->bt_a2dp_active) {
2041 const struct rtw_chip_info *chip = rtwdev->chip;
2042 struct rtw_coex *coex = &rtwdev->coex;
2043 struct rtw_coex_stat *coex_stat = &coex->stat;
2044 struct rtw_coex_dm *coex_dm = &coex->dm;
2045 struct rtw_efuse *efuse = &rtwdev->efuse;
2052 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
2056 if (efuse->share_ant) {
2057 /* Shared-Ant */
2058 if (coex_stat->wl_gl_busy && coex_stat->wl_noisy_level == 0)
2063 if (coex_stat->wl_connecting || !coex_stat->wl_gl_busy)
2068 /* Non-Shared-Ant */
2071 if (COEX_RSSI_HIGH(coex_dm->wl_rssi_state[1]))
2083 const struct rtw_chip_info *chip = rtwdev->chip;
2084 struct rtw_coex *coex = &rtwdev->coex;
2085 struct rtw_coex_stat *coex_stat = &coex->stat;
2086 struct rtw_efuse *efuse = &rtwdev->efuse;
2093 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
2095 if (efuse->share_ant) { /* Shared-Ant */
2099 } else if (coex_stat->wl_gl_busy) {
2106 } else { /* Non-Shared-Ant */
2122 const struct rtw_chip_info *chip = rtwdev->chip;
2123 struct rtw_coex *coex = &rtwdev->coex;
2124 struct rtw_coex_stat *coex_stat = &coex->stat;
2125 struct rtw_efuse *efuse = &rtwdev->efuse;
2130 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
2132 if (efuse->share_ant) {
2133 /* Shared-Ant */
2134 if (coex_stat->wl_gl_busy && coex_stat->wl_noisy_level == 0)
2139 if (coex_stat->wl_gl_busy)
2144 /* Non-Shared-Ant */
2147 if (coex_stat->wl_gl_busy)
2159 const struct rtw_chip_info *chip = rtwdev->chip;
2160 struct rtw_coex *coex = &rtwdev->coex;
2161 struct rtw_coex_stat *coex_stat = &coex->stat;
2162 struct rtw_coex_dm *coex_dm = &coex->dm;
2163 struct rtw_efuse *efuse = &rtwdev->efuse;
2172 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
2174 if (efuse->share_ant) {
2175 /* Shared-Ant */
2176 if (coex_stat->bt_ble_exist) {
2178 } else if (coex_stat->bt_418_hid_exist) {
2185 if (coex_stat->wl_connecting || !coex_stat->wl_gl_busy) {
2187 } else if (coex_stat->bt_418_hid_exist) {
2194 /* Non-Shared-Ant */
2195 if (coex_stat->bt_ble_exist)
2200 if (COEX_RSSI_HIGH(coex_dm->wl_rssi_state[1]))
2216 const struct rtw_chip_info *chip = rtwdev->chip;
2217 struct rtw_coex *coex = &rtwdev->coex;
2218 struct rtw_coex_stat *coex_stat = &coex->stat;
2219 struct rtw_efuse *efuse = &rtwdev->efuse;
2225 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
2226 if (efuse->share_ant) {
2227 /* Shared-Ant */
2228 if (coex_stat->wl_gl_busy &&
2229 coex_stat->wl_noisy_level == 0)
2234 if (coex_stat->wl_gl_busy)
2239 /* Non-Shared-Ant */
2242 if (coex_stat->wl_gl_busy)
2248 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
2255 const struct rtw_chip_info *chip = rtwdev->chip;
2256 struct rtw_coex *coex = &rtwdev->coex;
2257 struct rtw_coex_stat *coex_stat = &coex->stat;
2258 struct rtw_efuse *efuse = &rtwdev->efuse;
2264 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
2266 if (efuse->share_ant) {
2267 /* Shared-Ant */
2270 if (coex_stat->wl_gl_busy)
2275 /* Non-Shared-Ant */
2278 if (coex_stat->wl_gl_busy)
2290 const struct rtw_chip_info *chip = rtwdev->chip;
2291 struct rtw_coex *coex = &rtwdev->coex;
2292 struct rtw_coex_stat *coex_stat = &coex->stat;
2293 struct rtw_efuse *efuse = &rtwdev->efuse;
2298 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
2300 if (efuse->share_ant) {
2301 /* Shared-Ant */
2304 if (coex_stat->wl_gl_busy)
2309 /* Non-Shared-Ant */
2312 if (coex_stat->wl_gl_busy)
2324 const struct rtw_chip_info *chip = rtwdev->chip;
2325 struct rtw_coex *coex = &rtwdev->coex;
2326 struct rtw_efuse *efuse = &rtwdev->efuse;
2327 struct rtw_coex_stat *coex_stat = &coex->stat;
2333 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
2337 if (coex_stat->bt_game_hid_exist && coex_stat->wl_linkscan_proc)
2338 coex_stat->wl_coex_mode = COEX_WLINK_2GFREE;
2340 if (efuse->share_ant) {
2341 /* Shared-Ant */
2345 /* Non-Shared-Ant */
2356 const struct rtw_chip_info *chip = rtwdev->chip;
2357 struct rtw_efuse *efuse = &rtwdev->efuse;
2362 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
2364 if (efuse->share_ant) {
2365 /* Shared-Ant */
2369 /* Non-Shared-Ant */
2380 const struct rtw_chip_info *chip = rtwdev->chip;
2381 struct rtw_coex *coex = &rtwdev->coex;
2382 struct rtw_efuse *efuse = &rtwdev->efuse;
2383 struct rtw_coex_stat *coex_stat = &coex->stat;
2386 if (coex->under_5g)
2393 if (efuse->share_ant) {
2394 /* Shared-Ant */
2398 /* Non-Shared-Ant */
2403 if (coex_stat->bt_game_hid_exist) {
2404 coex_stat->wl_coex_mode = COEX_WLINK_2GFREE;
2405 if (coex_stat->wl_tput_dir == COEX_WL_TPUT_TX)
2406 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_tx[6]);
2408 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[5]);
2410 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
2419 const struct rtw_chip_info *chip = rtwdev->chip;
2420 struct rtw_coex *coex = &rtwdev->coex;
2421 struct rtw_coex_stat *coex_stat = &coex->stat;
2422 struct rtw_efuse *efuse = &rtwdev->efuse;
2428 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
2430 if (efuse->share_ant) { /* Shared-Ant */
2431 if (coex_stat->bt_a2dp_exist) {
2434 if (coex_stat->wl_gl_busy)
2442 } else { /* Non-Shared-Ant */
2443 if (coex_stat->bt_a2dp_exist) {
2459 const struct rtw_chip_info *chip = rtwdev->chip;
2460 struct rtw_efuse *efuse = &rtwdev->efuse;
2465 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
2467 if (efuse->share_ant) {
2468 /* Shared-Ant */
2472 /* Non-Shared-Ant */
2483 struct rtw_coex *coex = &rtwdev->coex;
2484 struct rtw_coex_stat *coex_stat = &coex->stat;
2504 else if (coex_stat->bt_a2dp_sink)
2536 const struct rtw_chip_info *chip = rtwdev->chip;
2537 struct rtw_coex *coex = &rtwdev->coex;
2538 struct rtw_coex_dm *coex_dm = &coex->dm;
2539 struct rtw_coex_stat *coex_stat = &coex->stat;
2542 lockdep_assert_held(&rtwdev->mutex);
2544 if (!test_bit(RTW_FLAG_RUNNING, rtwdev->flags))
2547 coex_dm->reason = reason;
2557 if (coex->manual_control) {
2563 if (coex->stop_dm) {
2569 if (coex_stat->wl_under_ips) {
2575 if (coex->freeze && coex_dm->reason == COEX_RSN_BTINFO &&
2576 !coex_stat->bt_setup_link) {
2582 coex_stat->cnt_wl[COEX_CNT_WL_COEXRUN]++;
2583 coex->freerun = false;
2585 /* Pure-5G Coex Process */
2586 if (coex->under_5g) {
2587 coex_stat->wl_coex_mode = COEX_WLINK_5G;
2592 rtw_dbg(rtwdev, RTW_DBG_COEX, "[BTCoex], WiFi is single-port 2G!!\n");
2593 coex_stat->wl_coex_mode = COEX_WLINK_2G1PORT;
2595 if (coex_stat->bt_disabled) {
2596 if (coex_stat->wl_connected && rf4ce_en)
2598 else if (!coex_stat->wl_connected)
2605 if (coex_stat->wl_under_lps && !coex_stat->wl_force_lps_ctrl) {
2610 if (coex_stat->bt_game_hid_exist && coex_stat->wl_connected) {
2615 if (coex_stat->bt_whck_test) {
2620 if (coex_stat->bt_setup_link) {
2625 if (coex_stat->bt_inq_page) {
2630 if ((coex_dm->bt_status == COEX_BTSTATUS_NCON_IDLE ||
2631 coex_dm->bt_status == COEX_BTSTATUS_CON_IDLE) &&
2632 coex_stat->wl_connected) {
2637 if (coex_stat->wl_linkscan_proc && !coex->freerun) {
2642 if (coex_stat->wl_connected) {
2652 if (chip->wl_mimo_ps_support) {
2653 if (coex_stat->wl_coex_mode == COEX_WLINK_2GFREE) {
2654 if (coex_dm->reason == COEX_RSN_2GMEDIA)
2663 rtw_coex_gnt_workaround(rtwdev, false, coex_stat->wl_coex_mode);
2669 struct rtw_coex *coex = &rtwdev->coex;
2670 struct rtw_coex_stat *coex_stat = &coex->stat;
2671 struct rtw_coex_dm *coex_dm = &coex->dm;
2678 coex_stat->cnt_wl[i] = 0;
2681 coex_stat->cnt_bt[i] = 0;
2683 for (i = 0; i < ARRAY_SIZE(coex_dm->bt_rssi_state); i++)
2684 coex_dm->bt_rssi_state[i] = COEX_RSSI_STATE_LOW;
2686 for (i = 0; i < ARRAY_SIZE(coex_dm->wl_rssi_state); i++)
2687 coex_dm->wl_rssi_state[i] = COEX_RSSI_STATE_LOW;
2689 coex_stat->wl_coex_mode = COEX_WLINK_MAX;
2690 coex_stat->wl_rx_rate = DESC_RATE5_5M;
2691 coex_stat->wl_rts_rx_rate = DESC_RATE5_5M;
2696 struct rtw_coex *coex = &rtwdev->coex;
2697 struct rtw_coex_stat *coex_stat = &coex->stat;
2703 coex_stat->kt_ver = u8_get_bits(rtw_read8(rtwdev, 0xf1), GENMASK(7, 4));
2706 rtw_coex_wl_slot_extend(rtwdev, coex_stat->wl_slot_extend);
2713 /* set Tx response = Hi-Pri (ex: Transmitting ACK,BA,CTS) */
2716 /* set Tx beacon = Hi-Pri */
2719 /* set Tx beacon queue = Hi-Pri */
2723 if (coex->wl_rf_off) {
2726 coex->stop_dm = true;
2734 coex->stop_dm = true;
2739 coex->stop_dm = false;
2740 coex->freeze = true;
2751 struct rtw_coex *coex = &rtwdev->coex;
2756 coex->stop_dm = true;
2757 coex->wl_rf_off = false;
2766 /* set antenna path to BT */
2790 struct rtw_coex *coex = &rtwdev->coex;
2791 struct rtw_coex_stat *coex_stat = &coex->stat;
2793 if (coex->manual_control || coex->stop_dm)
2799 coex_stat->wl_under_ips = true;
2813 coex_stat->wl_under_ips = false;
2819 struct rtw_coex *coex = &rtwdev->coex;
2820 struct rtw_coex_stat *coex_stat = &coex->stat;
2822 if (coex->manual_control || coex->stop_dm)
2828 coex_stat->wl_under_lps = true;
2830 if (coex_stat->wl_force_lps_ctrl) {
2831 /* for ps-tdma */
2843 coex_stat->wl_under_lps = false;
2848 if (!coex_stat->wl_force_lps_ctrl)
2857 struct rtw_coex *coex = &rtwdev->coex;
2858 struct rtw_coex_stat *coex_stat = &coex->stat;
2860 if (coex->manual_control || coex->stop_dm)
2863 coex->freeze = false;
2876 coex_stat->wl_hi_pri_task2 = true;
2882 coex_stat->cnt_wl[COEX_CNT_WL_SCANAP] = 30; /* To do */
2885 "[BTCoex], SCAN FINISH notify (Scan-AP = %d)\n",
2886 coex_stat->cnt_wl[COEX_CNT_WL_SCANAP]);
2888 coex_stat->wl_hi_pri_task2 = false;
2895 struct rtw_coex *coex = &rtwdev->coex;
2897 if (coex->manual_control || coex->stop_dm)
2921 struct rtw_coex *coex = &rtwdev->coex;
2922 struct rtw_coex_stat *coex_stat = &coex->stat;
2924 if (coex->manual_control || coex->stop_dm)
2942 coex_stat->wl_hi_pri_task1 = true;
2943 coex_stat->wl_connecting = true;
2944 coex_stat->cnt_wl[COEX_CNT_WL_CONNPKT] = 2;
2945 coex_stat->wl_connecting = true;
2946 ieee80211_queue_delayed_work(rtwdev->hw,
2947 &coex->wl_connecting_work, 2 * HZ);
2956 /* To keep TDMA case during connect process,
2957 * to avoid changed by Btinfo and runcoexmechanism
2959 coex->freeze = true;
2960 ieee80211_queue_delayed_work(rtwdev->hw, &coex->defreeze_work,
2963 coex_stat->wl_hi_pri_task1 = false;
2964 coex->freeze = false;
2965 coex_stat->wl_connecting = false;
2975 struct rtw_coex *coex = &rtwdev->coex;
2976 struct rtw_coex_stat *coex_stat = &coex->stat;
2978 if (coex->manual_control || coex->stop_dm)
2991 coex_stat->wl_connecting = false;
3013 const struct rtw_chip_info *chip = rtwdev->chip;
3014 struct rtw_coex *coex = &rtwdev->coex;
3015 struct rtw_coex_stat *coex_stat = &coex->stat;
3016 struct rtw_coex_dm *coex_dm = &coex->dm;
3024 coex_stat->cnt_bt_info_c2h[rsp_source]++;
3027 coex_stat->bt_iqk_state = buf[1];
3028 if (coex_stat->bt_iqk_state == 0)
3029 coex_stat->cnt_bt[COEX_CNT_BT_IQK]++;
3030 else if (coex_stat->bt_iqk_state == 2)
3031 coex_stat->cnt_bt[COEX_CNT_BT_IQKFAIL]++;
3046 if (coex_stat->bt_disabled != coex_stat->bt_disabled_pre) {
3047 coex_stat->bt_disabled_pre = coex_stat->bt_disabled;
3059 coex_dm->fw_tdma_para[i - 1] = buf[i];
3073 if (coex_stat->bt_disabled) {
3074 coex_stat->bt_disabled = false;
3075 coex_stat->bt_reenable = true;
3076 ieee80211_queue_delayed_work(rtwdev->hw,
3077 &coex->bt_reenable_work,
3096 coex_stat->bt_info_c2h[rsp_source][i] = buf[i];
3099 if (coex_stat->bt_info_c2h[rsp_source][1] == coex_stat->bt_info_lb2 &&
3100 coex_stat->bt_info_c2h[rsp_source][2] == coex_stat->bt_info_lb3 &&
3101 coex_stat->bt_info_c2h[rsp_source][3] == coex_stat->bt_info_hb0 &&
3102 coex_stat->bt_info_c2h[rsp_source][4] == coex_stat->bt_info_hb1 &&
3103 coex_stat->bt_info_c2h[rsp_source][5] == coex_stat->bt_info_hb2 &&
3104 coex_stat->bt_info_c2h[rsp_source][6] == coex_stat->bt_info_hb3) {
3110 coex_stat->bt_info_lb2 = coex_stat->bt_info_c2h[rsp_source][1];
3111 coex_stat->bt_info_lb3 = coex_stat->bt_info_c2h[rsp_source][2];
3112 coex_stat->bt_info_hb0 = coex_stat->bt_info_c2h[rsp_source][3];
3113 coex_stat->bt_info_hb1 = coex_stat->bt_info_c2h[rsp_source][4];
3114 coex_stat->bt_info_hb2 = coex_stat->bt_info_c2h[rsp_source][5];
3115 coex_stat->bt_info_hb3 = coex_stat->bt_info_c2h[rsp_source][6];
3118 coex_stat->bt_whck_test = (coex_stat->bt_info_lb2 == 0xff);
3120 inq_page = ((coex_stat->bt_info_lb2 & BIT(2)) == BIT(2));
3122 if (inq_page != coex_stat->bt_inq_page) {
3123 cancel_delayed_work_sync(&coex->bt_remain_work);
3124 coex_stat->bt_inq_page = inq_page;
3127 coex_stat->bt_inq_remain = true;
3129 ieee80211_queue_delayed_work(rtwdev->hw,
3130 &coex->bt_remain_work,
3133 coex_stat->bt_acl_busy = ((coex_stat->bt_info_lb2 & BIT(3)) == BIT(3));
3134 if (chip->ble_hid_profile_support) {
3135 if (coex_stat->bt_info_lb2 & BIT(5)) {
3136 if (coex_stat->bt_info_hb1 & BIT(0)) {
3138 coex_stat->bt_ble_hid_exist = true;
3140 coex_stat->bt_ble_hid_exist = false;
3142 coex_stat->bt_ble_exist = false;
3143 } else if (coex_stat->bt_info_hb1 & BIT(0)) {
3145 coex_stat->bt_ble_hid_exist = false;
3146 coex_stat->bt_ble_exist = true;
3148 coex_stat->bt_ble_hid_exist = false;
3149 coex_stat->bt_ble_exist = false;
3152 if (coex_stat->bt_info_hb1 & BIT(0)) {
3153 if (coex_stat->bt_hid_slot == 1 &&
3154 coex_stat->hi_pri_rx + 100 < coex_stat->hi_pri_tx &&
3155 coex_stat->hi_pri_rx < 100) {
3156 coex_stat->bt_ble_hid_exist = true;
3157 coex_stat->bt_ble_exist = false;
3159 coex_stat->bt_ble_hid_exist = false;
3160 coex_stat->bt_ble_exist = true;
3163 coex_stat->bt_ble_hid_exist = false;
3164 coex_stat->bt_ble_exist = false;
3168 coex_stat->cnt_bt[COEX_CNT_BT_RETRY] = coex_stat->bt_info_lb3 & 0xf;
3169 if (coex_stat->cnt_bt[COEX_CNT_BT_RETRY] >= 1)
3170 coex_stat->cnt_bt[COEX_CNT_BT_POPEVENT]++;
3172 coex_stat->bt_fix_2M = ((coex_stat->bt_info_lb3 & BIT(4)) == BIT(4));
3173 coex_stat->bt_inq = ((coex_stat->bt_info_lb3 & BIT(5)) == BIT(5));
3174 if (coex_stat->bt_inq)
3175 coex_stat->cnt_bt[COEX_CNT_BT_INQ]++;
3177 coex_stat->bt_page = ((coex_stat->bt_info_lb3 & BIT(7)) == BIT(7));
3178 if (coex_stat->bt_page)
3179 coex_stat->cnt_bt[COEX_CNT_BT_PAGE]++;
3181 /* unit: % (value-100 to translate to unit: dBm in coex info) */
3182 if (chip->bt_rssi_type == COEX_BTRSSI_RATIO) {
3183 coex_stat->bt_rssi = coex_stat->bt_info_hb0 * 2 + 10;
3185 if (coex_stat->bt_info_hb0 <= 127)
3186 coex_stat->bt_rssi = 100;
3187 else if (256 - coex_stat->bt_info_hb0 <= 100)
3188 coex_stat->bt_rssi = 100 - (256 - coex_stat->bt_info_hb0);
3190 coex_stat->bt_rssi = 0;
3193 if (coex_stat->bt_info_hb1 & BIT(1))
3194 coex_stat->cnt_bt[COEX_CNT_BT_REINIT]++;
3196 if (coex_stat->bt_info_hb1 & BIT(2)) {
3197 coex_stat->cnt_bt[COEX_CNT_BT_SETUPLINK]++;
3198 coex_stat->bt_setup_link = true;
3199 if (coex_stat->bt_reenable)
3204 ieee80211_queue_delayed_work(rtwdev->hw,
3205 &coex->bt_relink_work,
3209 "[BTCoex], Re-Link start in BT info!!\n");
3212 if (coex_stat->bt_info_hb1 & BIT(3))
3213 coex_stat->cnt_bt[COEX_CNT_BT_IGNWLANACT]++;
3215 coex_stat->bt_ble_voice = ((coex_stat->bt_info_hb1 & BIT(4)) == BIT(4));
3216 coex_stat->bt_ble_scan_en = ((coex_stat->bt_info_hb1 & BIT(5)) == BIT(5));
3217 if (coex_stat->bt_info_hb1 & BIT(6))
3218 coex_stat->cnt_bt[COEX_CNT_BT_ROLESWITCH]++;
3220 coex_stat->bt_multi_link = ((coex_stat->bt_info_hb1 & BIT(7)) == BIT(7));
3222 /* Use PS-TDMA to protect WL RX */
3223 if (!coex_stat->bt_multi_link && coex_stat->bt_multi_link_pre) {
3224 coex_stat->bt_multi_link_remain = true;
3225 ieee80211_queue_delayed_work(rtwdev->hw,
3226 &coex->bt_multi_link_remain_work,
3229 coex_stat->bt_multi_link_pre = coex_stat->bt_multi_link;
3231 /* resend wifi info to bt, it is reset and lost the info */
3232 if (coex_stat->bt_info_hb1 & BIT(1)) {
3234 "[BTCoex], BT Re-init, send wifi BW & Chnl to BT!!\n");
3236 if (coex_stat->wl_connected)
3244 if ((coex_stat->bt_info_hb1 & BIT(3)) &&
3245 (!(coex_stat->bt_info_hb1 & BIT(2)))) {
3247 "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n");
3251 coex_stat->bt_opp_exist = ((coex_stat->bt_info_hb2 & BIT(0)) == BIT(0));
3252 if (coex_stat->bt_info_hb2 & BIT(1))
3253 coex_stat->cnt_bt[COEX_CNT_BT_AFHUPDATE]++;
3255 coex_stat->bt_a2dp_active = (coex_stat->bt_info_hb2 & BIT(2)) == BIT(2);
3256 coex_stat->bt_slave = ((coex_stat->bt_info_hb2 & BIT(3)) == BIT(3));
3257 coex_stat->bt_hid_slot = (coex_stat->bt_info_hb2 & 0x30) >> 4;
3258 coex_stat->bt_hid_pair_num = (coex_stat->bt_info_hb2 & 0xc0) >> 6;
3259 if (coex_stat->bt_hid_pair_num > 0 && coex_stat->bt_hid_slot >= 2)
3260 coex_stat->bt_418_hid_exist = true;
3261 else if (coex_stat->bt_hid_pair_num == 0 || coex_stat->bt_hid_slot == 1)
3262 coex_stat->bt_418_hid_exist = false;
3264 if ((coex_stat->bt_info_lb2 & 0x49) == 0x49)
3265 coex_stat->bt_a2dp_bitpool = (coex_stat->bt_info_hb3 & 0x7f);
3267 coex_stat->bt_a2dp_bitpool = 0;
3269 coex_stat->bt_a2dp_sink = ((coex_stat->bt_info_hb3 & BIT(7)) == BIT(7));
3281 const struct rtw_chip_info *chip = rtwdev->chip;
3282 struct rtw_coex *coex = &rtwdev->coex;
3283 struct rtw_coex_stat *coex_stat = &coex->stat;
3290 if (!chip->wl_mimo_ps_support &&
3299 hl = &coex_stat->hid_handle_list;
3303 coex_stat->hid_handle_list = *bhl;
3304 memset(&coex_stat->hid_info, 0, sizeof(coex_stat->hid_info));
3306 hidinfo = &coex_stat->hid_info[i];
3307 if (hl->handle[i] != COEX_BT_HIDINFO_NOTCON &&
3308 hl->handle[i] != 0)
3309 hidinfo->hid_handle = hl->handle[i];
3314 handle = hida->handle;
3316 hidinfo = &coex_stat->hid_info[i];
3317 if (hidinfo->hid_handle == handle) {
3318 hidinfo->hid_vendor = hida->vendor;
3319 memcpy(hidinfo->hid_name, hida->name,
3320 sizeof(hidinfo->hid_name));
3321 hidinfo->hid_info_completed = true;
3328 hidinfo = &coex_stat->hid_info[i];
3329 complete = hidinfo->hid_info_completed;
3330 handle = hidinfo->hid_handle;
3333 hidinfo->is_game_hid = false;
3337 if (hidinfo->hid_vendor == COEX_BT_HIDINFO_MTK) {
3338 if ((memcmp(hidinfo->hid_name,
3341 hidinfo->is_game_hid = true;
3342 else if ((memcmp(hidinfo->hid_name,
3345 hidinfo->is_game_hid = true;
3347 hidinfo->is_game_hid = false;
3349 hidinfo->is_game_hid = false;
3351 if (hidinfo->is_game_hid)
3360 if (cur_game_hid_exist != coex_stat->bt_game_hid_exist) {
3361 coex_stat->bt_game_hid_exist = cur_game_hid_exist;
3364 coex_stat->bt_game_hid_exist);
3371 const struct rtw_chip_info *chip = rtwdev->chip;
3372 struct rtw_coex *coex = &rtwdev->coex;
3373 struct rtw_coex_stat *coex_stat = &coex->stat;
3378 if (!chip->wl_mimo_ps_support || coex_stat->wl_under_ips ||
3379 (coex_stat->wl_under_lps && !coex_stat->wl_force_lps_ctrl))
3382 if (!coex_stat->bt_hid_exist &&
3383 !((coex_stat->bt_info_lb2 & COEX_INFO_CONNECTION) &&
3384 (coex_stat->hi_pri_tx + coex_stat->hi_pri_rx >
3391 hidinfo = &coex_stat->hid_info[i];
3392 complete = hidinfo->hid_info_completed;
3393 handle = hidinfo->hid_handle;
3406 struct rtw_coex *coex = &rtwdev->coex;
3407 struct rtw_coex_stat *coex_stat = &coex->stat;
3421 val = coex_stat->wl_fw_dbg_info_pre[i];
3423 coex_stat->wl_fw_dbg_info[i] = buf[i] - val;
3425 coex_stat->wl_fw_dbg_info[i] = 255 - val + buf[i];
3427 coex_stat->wl_fw_dbg_info_pre[i] = buf[i];
3430 coex_stat->cnt_wl[COEX_CNT_WL_FW_NOTIFY]++;
3442 struct rtw_coex_stat *coex_stat = &rtwdev->coex.stat;
3444 if ((coex_stat->wl_under_lps && !coex_stat->wl_force_lps_ctrl) ||
3445 coex_stat->wl_under_ips)
3455 struct rtw_coex_stat *coex_stat = &rtwdev->coex.stat;
3457 mutex_lock(&rtwdev->mutex);
3458 coex_stat->bt_setup_link = false;
3460 mutex_unlock(&rtwdev->mutex);
3467 struct rtw_coex_stat *coex_stat = &rtwdev->coex.stat;
3469 mutex_lock(&rtwdev->mutex);
3470 coex_stat->bt_reenable = false;
3471 mutex_unlock(&rtwdev->mutex);
3478 struct rtw_coex *coex = &rtwdev->coex;
3479 struct rtw_coex_stat *coex_stat = &rtwdev->coex.stat;
3481 mutex_lock(&rtwdev->mutex);
3482 coex->freeze = false;
3483 coex_stat->wl_hi_pri_task1 = false;
3485 mutex_unlock(&rtwdev->mutex);
3492 struct rtw_coex_stat *coex_stat = &rtwdev->coex.stat;
3494 mutex_lock(&rtwdev->mutex);
3495 coex_stat->wl_gl_busy = test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags);
3497 mutex_unlock(&rtwdev->mutex);
3504 struct rtw_coex_stat *coex_stat = &rtwdev->coex.stat;
3506 mutex_lock(&rtwdev->mutex);
3507 coex_stat->bt_inq_remain = coex_stat->bt_inq_page;
3509 mutex_unlock(&rtwdev->mutex);
3516 struct rtw_coex_stat *coex_stat = &rtwdev->coex.stat;
3518 mutex_lock(&rtwdev->mutex);
3519 coex_stat->wl_connecting = false;
3522 mutex_unlock(&rtwdev->mutex);
3529 struct rtw_coex_stat *coex_stat = &rtwdev->coex.stat;
3531 mutex_lock(&rtwdev->mutex);
3532 coex_stat->bt_multi_link_remain = false;
3533 mutex_unlock(&rtwdev->mutex);
3540 struct rtw_coex_stat *coex_stat = &rtwdev->coex.stat;
3542 mutex_lock(&rtwdev->mutex);
3543 coex_stat->wl_cck_lock = false;
3544 mutex_unlock(&rtwdev->mutex);
3593 const struct rtw_chip_info *chip = rtwdev->chip;
3594 struct rtw_efuse *efuse = &rtwdev->efuse;
3599 bool share_ant = efuse->share_ant;
3602 n = chip->table_sant_num;
3604 n = chip->table_nsant_num;
3608 load_bt_val = chip->table_sant[i].bt;
3609 load_wl_val = chip->table_sant[i].wl;
3611 load_bt_val = chip->table_nsant[i].bt;
3612 load_wl_val = chip->table_nsant[i].wl;
3629 const struct rtw_chip_info *chip = rtwdev->chip;
3630 struct rtw_efuse *efuse = &rtwdev->efuse;
3635 bool share_ant = efuse->share_ant;
3638 n = chip->tdma_sant_num;
3640 n = chip->tdma_nsant_num;
3646 load_cur_tab_val = chip->tdma_sant[i].para[j];
3648 load_cur_tab_val = chip->tdma_nsant[i].para[j];
3674 if (INFO_SIZE - n <= 0)
3677 switch (reg->domain) {
3696 ffs = __ffs(reg->mask);
3697 fls = __fls(reg->mask);
3700 return scnprintf(addr_info + n, INFO_SIZE - n, "%s%s%x",
3701 sep, rf_prefix, reg->addr);
3703 return scnprintf(addr_info + n, INFO_SIZE - n, "%s%s%x[%d]",
3704 sep, rf_prefix, reg->addr, ffs);
3706 return scnprintf(addr_info + n, INFO_SIZE - n, "%s%s%x[%d:%d]",
3707 sep, rf_prefix, reg->addr, fls, ffs);
3717 if (INFO_SIZE - n <= 0)
3720 switch (reg->domain) {
3722 return scnprintf(val_info + n, INFO_SIZE - n, "%s0x%x", sep,
3723 rtw_read32_mask(rtwdev, reg->addr, reg->mask));
3725 return scnprintf(val_info + n, INFO_SIZE - n, "%s0x%x", sep,
3726 rtw_read16_mask(rtwdev, reg->addr, reg->mask));
3728 return scnprintf(val_info + n, INFO_SIZE - n, "%s0x%x", sep,
3729 rtw_read8_mask(rtwdev, reg->addr, reg->mask));
3741 return scnprintf(val_info + n, INFO_SIZE - n, "%s0x%x", sep,
3742 rtw_read_rf(rtwdev, rf_path, reg->addr, reg->mask));
3747 const struct rtw_chip_info *chip = rtwdev->chip;
3755 for (i = 0; i < chip->coex_info_hw_regs_num; i++) {
3756 reg = &chip->coex_info_hw_regs[i];
3761 if (reg->domain == RTW_REG_DOMAIN_NL) {
3762 seq_printf(m, "%-40s = %s\n", addr_info, val_info);
3769 seq_printf(m, "%-40s = %s\n", addr_info, val_info);
3863 struct rtw_vif *rtwvif = sta_iter_data->rtwvif;
3864 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
3865 struct seq_file *m = sta_iter_data->file;
3869 if (si->vif != vif)
3872 rssi = ewma_rssi_read(&si->avg_rssi);
3873 seq_printf(m, "\tPeer %3d\n", si->mac_id);
3874 seq_printf(m, "\t\t%-24s = %d\n", "RSSI", rssi);
3875 seq_printf(m, "\t\t%-24s = %d\n", "BW mode", si->bw_mode);
3888 struct rtw_dev *rtwdev = vif_iter_data->rtwdev;
3889 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
3890 struct seq_file *m = vif_iter_data->file;
3891 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
3893 seq_printf(m, "Iface on Port (%d)\n", rtwvif->port);
3894 seq_printf(m, "\t%-32s = %d\n",
3895 "Beacon interval", bss_conf->beacon_int);
3896 seq_printf(m, "\t%-32s = %d\n",
3897 "Network Type", rtwvif->net_type);
3921 const struct rtw_chip_info *chip = rtwdev->chip;
3922 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
3923 struct rtw_coex *coex = &rtwdev->coex;
3924 struct rtw_coex_stat *coex_stat = &coex->stat;
3925 struct rtw_coex_dm *coex_dm = &coex->dm;
3926 struct rtw_hal *hal = &rtwdev->hal;
3927 struct rtw_efuse *efuse = &rtwdev->efuse;
3928 struct rtw_fw_state *fw = &rtwdev->fw;
3930 u8 reason = coex_dm->reason;
3938 score_board_WB = coex_stat->score_board;
3946 if (rtwdev->chip->ltecoex_addr) {
3951 if (!coex_stat->wl_under_ips &&
3952 (!coex_stat->wl_under_lps || coex_stat->wl_force_lps_ctrl) &&
3953 !coex_stat->bt_disabled && !coex_stat->bt_mailbox_reply) {
3955 &coex_stat->bt_supported_version);
3956 rtw_coex_get_bt_patch_version(rtwdev, &coex_stat->patch_ver);
3958 &coex_stat->bt_supported_feature);
3959 rtw_coex_get_bt_reg(rtwdev, 3, 0xae, &coex_stat->bt_reg_vendor_ae);
3960 rtw_coex_get_bt_reg(rtwdev, 3, 0xac, &coex_stat->bt_reg_vendor_ac);
3962 if (coex_stat->patch_ver != 0)
3963 coex_stat->bt_mailbox_reply = true;
3968 seq_printf(m, "\t\tBT Coexist info %x\n", chip->id);
3971 if (coex->manual_control) {
3975 } else if (coex->stop_dm) {
3979 } else if (coex->freeze) {
3984 seq_printf(m, "%-40s = %s/ %d\n",
3986 efuse->share_ant ? "Shared" : "Non-Shared",
3987 efuse->rfe_option);
3988 seq_printf(m, "%-40s = %08x/ 0x%02x/ 0x%08x %s\n",
3990 chip->coex_para_ver, chip->bt_desired_ver,
3991 coex_stat->bt_supported_version,
3992 coex_stat->bt_disabled ? "(BT disabled)" :
3993 coex_stat->bt_supported_version >= chip->bt_desired_ver ?
3995 seq_printf(m, "%-40s = %s/ %u/ %d\n",
3997 coex_stat->bt_slave ? "Slave" : "Master",
3998 coex_stat->cnt_bt[COEX_CNT_BT_ROLESWITCH],
3999 coex_dm->ignore_wl_act);
4000 seq_printf(m, "%-40s = %u.%u/ 0x%x/ 0x%x/ %c\n",
4002 fw->version, fw->sub_version,
4003 coex_stat->patch_ver,
4004 chip->wl_fw_desired_ver, coex_stat->kt_ver + 65);
4005 seq_printf(m, "%-40s = %u/ %u/ %u/ ch-(%u)\n",
4007 coex_dm->wl_ch_info[0], coex_dm->wl_ch_info[1],
4008 coex_dm->wl_ch_info[2], hal->current_channel);
4014 seq_printf(m, "%-40s = %s/ %ddBm/ %u/ %u\n",
4016 coex_dm->bt_status == COEX_BTSTATUS_NCON_IDLE ? "non-conn" :
4017 coex_dm->bt_status == COEX_BTSTATUS_CON_IDLE ? "conn-idle" : "busy",
4018 coex_stat->bt_rssi - 100,
4019 coex_stat->cnt_bt[COEX_CNT_BT_RETRY],
4020 coex_stat->cnt_bt[COEX_CNT_BT_POPEVENT]);
4021 seq_printf(m, "%-40s = %s%s%s%s%s (multi-link %d)\n",
4023 coex_stat->bt_a2dp_exist ? (coex_stat->bt_a2dp_sink ?
4025 coex_stat->bt_hfp_exist ? "HFP," : "",
4026 coex_stat->bt_hid_exist ?
4027 (coex_stat->bt_ble_exist ? "HID(RCU)," :
4028 coex_stat->bt_hid_slot >= 2 ? "HID(4/18)" :
4029 coex_stat->bt_ble_hid_exist ? "HID(BLE)" :
4031 coex_stat->bt_pan_exist ? coex_stat->bt_opp_exist ?
4033 coex_stat->bt_ble_voice ? "Voice," : "",
4034 coex_stat->bt_multi_link);
4035 seq_printf(m, "%-40s = %u/ %u/ %u/ 0x%08x\n",
4037 coex_stat->cnt_bt[COEX_CNT_BT_REINIT],
4038 coex_stat->cnt_bt[COEX_CNT_BT_SETUPLINK],
4039 coex_stat->cnt_bt[COEX_CNT_BT_IGNWLANACT],
4040 coex_stat->bt_supported_feature);
4041 seq_printf(m, "%-40s = %u/ %u/ %u/ %u\n",
4043 coex_stat->cnt_bt[COEX_CNT_BT_PAGE],
4044 coex_stat->cnt_bt[COEX_CNT_BT_INQ],
4045 coex_stat->cnt_bt[COEX_CNT_BT_IQK],
4046 coex_stat->cnt_bt[COEX_CNT_BT_IQKFAIL]);
4047 seq_printf(m, "%-40s = 0x%04x/ 0x%04x/ 0x%04x/ 0x%04x\n",
4048 "0xae/ 0xac/ score board (W->B)/ (B->W)",
4049 coex_stat->bt_reg_vendor_ae,
4050 coex_stat->bt_reg_vendor_ac,
4052 seq_printf(m, "%-40s = %u/%u, %u/%u\n",
4053 "Hi-Pri TX/RX, Lo-Pri TX/RX",
4054 coex_stat->hi_pri_tx, coex_stat->hi_pri_rx,
4055 coex_stat->lo_pri_tx, coex_stat->lo_pri_rx);
4057 seq_printf(m, "%-40s = %7ph\n",
4059 coex_stat->bt_info_c2h[i]);
4064 seq_printf(m, "%-40s = %d\n",
4065 "Scanning", test_bit(RTW_FLAG_SCANNING, rtwdev->flags));
4066 seq_printf(m, "%-40s = %u/ TX %d Mbps/ RX %d Mbps\n",
4068 coex_stat->wl_gl_busy,
4069 rtwdev->stats.tx_throughput, rtwdev->stats.rx_throughput);
4070 seq_printf(m, "%-40s = %u/ %u/ %u\n",
4072 !test_bit(RTW_FLAG_POWERON, rtwdev->flags),
4073 test_bit(RTW_FLAG_LEISURE_PS_DEEP, rtwdev->flags),
4074 rtwdev->lps_conf.mode);
4080 if (coex->manual_control) {
4084 seq_printf(m, "%-40s = %5ph (%d)\n",
4086 coex_dm->fw_tdma_para,
4088 &coex_dm->fw_tdma_para[0]));
4093 seq_printf(m, "%-40s = %5ph (case-%d)\n",
4095 coex_dm->ps_tdma_para, coex_dm->cur_ps_tdma);
4097 seq_printf(m, "%-40s = %s/ %s/ %d\n",
4099 rtw_coex_get_wl_coex_mode(coex_stat->wl_coex_mode),
4100 coex->freerun ? "Yes" : "No",
4101 coex_stat->tdma_timer_base);
4102 seq_printf(m, "%-40s = %d(%d)/ 0x%08x/ 0x%08x/ 0x%08x\n",
4104 coex_dm->cur_table,
4107 seq_printf(m, "%-40s = 0x%08x/ 0x%08x/ %d/ reason (%s)\n",
4110 coex_stat->cnt_wl[COEX_CNT_WL_COEXRUN],
4112 seq_printf(m, "%-40s = %3ph\n",
4113 "AFH Map to BT",
4114 coex_dm->wl_ch_info);
4115 seq_printf(m, "%-40s = %s/ %d\n",
4117 coex_stat->wl_force_lps_ctrl ? "On" : "Off",
4118 coex_stat->wl_gl_busy);
4119 seq_printf(m, "%-40s = %u/ %u/ %u/ %u/ %u\n",
4121 coex_stat->wl_fw_dbg_info[1], coex_stat->wl_fw_dbg_info[2],
4122 coex_stat->wl_fw_dbg_info[3], coex_stat->wl_fw_dbg_info[4],
4123 coex_stat->wl_fw_dbg_info[5]);
4124 seq_printf(m, "%-40s = %u/ %u/ %s/ %u\n",
4126 coex_stat->wl_fw_dbg_info[6],
4127 coex_stat->wl_fw_dbg_info[7],
4128 coex_stat->wl_slot_extend ? "Yes" : "No",
4129 coex_stat->cnt_wl[COEX_CNT_WL_FW_NOTIFY]);
4130 seq_printf(m, "%-40s = %d/ %d/ %s/ %d\n",
4132 coex_dm->cur_wl_pwr_lvl,
4133 coex_dm->cur_bt_pwr_lvl,
4134 coex_dm->cur_wl_rx_low_gain_en ? "On" : "Off",
4135 coex_dm->cur_bt_lna_lvl);
4140 seq_printf(m, "%-40s = %s/ %s\n",
4144 seq_printf(m, "%-40s = RF:%s_BB:%s/ RF:%s_BB:%s/ %s\n",
4151 seq_printf(m, "%-40s = %lu/ %lu\n",
4154 seq_printf(m, "%-40s = %u/ %u/ %u/ %u\n",
4156 dm_info->cck_ok_cnt, dm_info->ofdm_ok_cnt,
4157 dm_info->ht_ok_cnt, dm_info->vht_ok_cnt);
4158 seq_printf(m, "%-40s = %u/ %u/ %u/ %u\n",
4160 dm_info->cck_err_cnt, dm_info->ofdm_err_cnt,
4161 dm_info->ht_err_cnt, dm_info->vht_err_cnt);
4162 seq_printf(m, "%-40s = %s/ %s/ %s/ %u\n",
4164 coex_stat->wl_hi_pri_task1 ? "Y" : "N",
4165 coex_stat->wl_cck_lock ? "Y" : "N",
4166 coex_stat->wl_cck_lock_ever ? "Y" : "N",
4167 coex_stat->wl_noisy_level);
4170 seq_printf(m, "%-40s = %d/ %d/ %d/ %d\n",
4172 -dm_info->rx_evm_dbm[RF_PATH_A],
4173 -dm_info->rx_evm_dbm[RF_PATH_B],
4174 -dm_info->rx_snr[RF_PATH_A],
4175 -dm_info->rx_snr[RF_PATH_B]);
4176 seq_printf(m, "%-40s = %d/ %d/ %d/ %d\n",
4177 "CCK-CCA/CCK-FA/OFDM-CCA/OFDM-FA",
4178 dm_info->cck_cca_cnt, dm_info->cck_fa_cnt,
4179 dm_info->ofdm_cca_cnt, dm_info->ofdm_fa_cnt);
4180 seq_printf(m, "%-40s = %d/ %d/ %d/ %d\n", "CRC OK CCK/11g/11n/11ac",
4181 dm_info->cck_ok_cnt, dm_info->ofdm_ok_cnt,
4182 dm_info->ht_ok_cnt, dm_info->vht_ok_cnt);
4183 seq_printf(m, "%-40s = %d/ %d/ %d/ %d\n", "CRC Err CCK/11g/11n/11ac",
4184 dm_info->cck_err_cnt, dm_info->ofdm_err_cnt,
4185 dm_info->ht_err_cnt, dm_info->vht_err_cnt);