Lines Matching +full:chip +full:- +full:to +full:- +full:chip
1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
93 rtw_err(rtwdev, "failed to poll REG_SDIO_HSUS_CTRL[1]");
94 return -ETIMEDOUT;
107 return -EINVAL;
156 if (cmd->base == RTW_PWR_ADDR_SDIO)
157 offset = cmd->offset | SDIO_LOCAL_OFFSET;
159 offset = cmd->offset;
161 if (do_pwr_poll_cmd(rtwdev, offset, cmd->mask, cmd->value))
169 if (rtwdev->chip->id == RTW_CHIP_TYPE_8723D)
173 if (rtwdev->chip->id == RTW_CHIP_TYPE_8723D)
176 if (do_pwr_poll_cmd(rtwdev, offset, cmd->mask, cmd->value))
180 rtw_err(rtwdev, "failed to poll offset=0x%x mask=0x%x value=0x%x\n",
181 offset, cmd->mask, cmd->value);
182 return -EBUSY;
193 for (cur_cmd = cmd; cur_cmd->cmd != RTW_PWR_CMD_END; cur_cmd++) {
194 if (!(cur_cmd->intf_mask & intf_mask) ||
195 !(cur_cmd->cut_mask & cut_mask))
198 switch (cur_cmd->cmd) {
200 offset = cur_cmd->offset;
202 if (cur_cmd->base == RTW_PWR_ADDR_SDIO)
206 value &= ~cur_cmd->mask;
207 value |= (cur_cmd->value & cur_cmd->mask);
212 return -EBUSY;
215 if (cur_cmd->value == RTW_PWR_DELAY_US)
216 udelay(cur_cmd->offset);
218 mdelay(cur_cmd->offset);
223 return -EINVAL;
240 cut = rtwdev->hal.cut_version;
253 return -EINVAL;
273 const struct rtw_chip_info *chip = rtwdev->chip;
281 rpwm = rtw_read8(rtwdev, rtwdev->hci.rpwm_addr);
286 rtw_write8(rtwdev, rtwdev->hci.rpwm_addr, rpwm);
299 return -EALREADY;
307 clear_bit(RTW_FLAG_POWERON, rtwdev->flags);
309 pwr_seq = pwr_on ? chip->pwr_on_seq : chip->pwr_off_seq;
313 if (chip->id == RTW_CHIP_TYPE_8822C ||
314 chip->id == RTW_CHIP_TYPE_8822B ||
315 chip->id == RTW_CHIP_TYPE_8821C)
323 set_bit(RTW_FLAG_POWERON, rtwdev->flags);
330 u8 sys_func_en = rtwdev->chip->sys_func_en;
342 /* disable boot-from-flash for driver's DL FW */
385 if (ret == -EALREADY) {
423 dmem_size = le32_to_cpu(fw_hdr->dmem_size);
424 imem_size = le32_to_cpu(fw_hdr->imem_size);
425 emem_size = (fw_hdr->mem_usage & BIT(4)) ?
426 le32_to_cpu(fw_hdr->emem_size) : 0;
463 /* set HIQ to hi priority */
471 /* DLFW only use HIQ, map HIQ to hi priority */
494 rtw_write32(rtwdev, REG_RQPN_CTRL_2, bckp[bckp_idx - 1].val);
536 return -ENOMEM;
549 !((size + TX_DESC_SIZE) & (512 - 1)))
554 rtw_err(rtwdev, "failed to download rsvd page\n");
567 return -EBUSY;
578 return -EBUSY;
585 return -EBUSY;
595 rtw_dbg(rtwdev, RTW_DBG_FW, "busy to start ddma\n");
596 return -EBUSY;
602 rtw_dbg(rtwdev, RTW_DBG_FW, "busy to complete ddma\n");
603 return -EBUSY;
647 const struct rtw_chip_info *chip = rtwdev->chip;
648 u32 desc_size = chip->tx_pkt_desc_sz;
685 residue_size -= pkt_size;
689 return -EINVAL;
706 dmem_size = le32_to_cpu(fw_hdr->dmem_size);
707 imem_size = le32_to_cpu(fw_hdr->imem_size);
708 emem_size = (fw_hdr->mem_usage & BIT(4)) ?
709 le32_to_cpu(fw_hdr->emem_size) : 0;
719 addr = le32_to_cpu(fw_hdr->dmem_addr);
726 addr = le32_to_cpu(fw_hdr->imem_addr);
734 addr = le32_to_cpu(fw_hdr->emem_addr);
753 return -EINVAL;
778 const u8 *data = fw->firmware->data;
779 u32 size = fw->firmware->size;
784 return -EINVAL;
787 return -EBUSY;
805 ret = -EBUSY;
816 rtwdev->h2c.last_box_num = 0;
817 rtwdev->h2c.seq = 0;
819 set_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags);
847 rtw_err(rtwdev, "failed to check fw download ready\n");
867 remain_size = size & (DLFW_BLK_SIZE_LEGACY - 1);
895 size -= sizeof(struct rtw_fw_hdr_legacy);
898 last_page_size = size & (DLFW_PAGE_SIZE_LEGACY - 1);
910 rtw_err(rtwdev, "failed to check download firmware report\n");
911 return -EINVAL;
937 rtw_err(rtwdev, "failed to validate firmware\n");
938 return -EINVAL;
947 if (rtwdev->chip->id == RTW_CHIP_TYPE_8703B &&
953 ret = download_firmware_legacy(rtwdev, fw->firmware->data, fw->firmware->size);
965 rtwdev->h2c.last_box_num = 0;
966 rtwdev->h2c.seq = 0;
968 set_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags);
992 rtwdev->chip->id == RTW_CHIP_TYPE_8821C)
1000 const struct rtw_rqpn *rqpn = rtwdev->fifo.rqpn;
1004 prio_queues |= BIT(rqpn->dma_map_vo);
1006 prio_queues |= BIT(rqpn->dma_map_vi);
1008 prio_queues |= BIT(rqpn->dma_map_be);
1010 prio_queues |= BIT(rqpn->dma_map_bk);
1018 const struct rtw_chip_info *chip = rtwdev->chip;
1027 addr = &chip->prioq_addrs->prio[prio_queue];
1028 wsize = chip->prioq_addrs->wsize;
1032 rsvd_page = wsize ? rtw_read16(rtwdev, addr->rsvd) :
1033 rtw_read8(rtwdev, addr->rsvd);
1034 avail_page = wsize ? rtw_read16(rtwdev, addr->avail) :
1035 rtw_read8(rtwdev, addr->avail);
1044 * Note that if we want to flush the tx queue when having a lot of
1046 * And it requires like ~2secs to flush the full priority queue.
1050 "timed out to flush queue %d\n", prio_queue);
1067 /* If all of the hardware queues are requested to flush,
1071 if (queues == BIT(rtwdev->hw->queues) - 1 || !rtwdev->fifo.rqpn)
1072 prio_queues = BIT(RTW_DMA_MAPPING_MAX) - 1;
1081 const struct rtw_chip_info *chip = rtwdev->chip;
1087 rqpn = &chip->rqpn_table[1];
1090 if (rtwdev->hci.bulkout_num == 2)
1091 rqpn = &chip->rqpn_table[2];
1092 else if (rtwdev->hci.bulkout_num == 3)
1093 rqpn = &chip->rqpn_table[3];
1094 else if (rtwdev->hci.bulkout_num == 4)
1095 rqpn = &chip->rqpn_table[4];
1097 return -EINVAL;
1100 rqpn = &chip->rqpn_table[0];
1103 return -EINVAL;
1106 rtwdev->fifo.rqpn = rqpn;
1107 txdma_pq_map |= BIT_TXDMA_HIQ_MAP(rqpn->dma_map_hi);
1108 txdma_pq_map |= BIT_TXDMA_MGQ_MAP(rqpn->dma_map_mg);
1109 txdma_pq_map |= BIT_TXDMA_BKQ_MAP(rqpn->dma_map_bk);
1110 txdma_pq_map |= BIT_TXDMA_BEQ_MAP(rqpn->dma_map_be);
1111 txdma_pq_map |= BIT_TXDMA_VIQ_MAP(rqpn->dma_map_vi);
1112 txdma_pq_map |= BIT_TXDMA_VOQ_MAP(rqpn->dma_map_vo);
1132 const struct rtw_chip_info *chip = rtwdev->chip;
1133 struct rtw_fifo_conf *fifo = &rtwdev->fifo;
1135 u8 csi_buf_pg_num = chip->csi_buf_pg_num;
1138 fifo->rsvd_drv_pg_num = chip->rsvd_drv_pg_num;
1139 fifo->txff_pg_num = chip->txff_size >> 7;
1141 fifo->rsvd_pg_num = fifo->rsvd_drv_pg_num;
1143 fifo->rsvd_pg_num = fifo->rsvd_drv_pg_num +
1151 if (fifo->rsvd_pg_num > fifo->txff_pg_num)
1152 return -ENOMEM;
1154 fifo->acq_pg_num = fifo->txff_pg_num - fifo->rsvd_pg_num;
1155 fifo->rsvd_boundary = fifo->txff_pg_num - fifo->rsvd_pg_num;
1157 cur_pg_addr = fifo->txff_pg_num;
1159 cur_pg_addr -= csi_buf_pg_num;
1160 fifo->rsvd_csibuf_addr = cur_pg_addr;
1161 cur_pg_addr -= RSVD_PG_FW_TXBUF_NUM;
1162 fifo->rsvd_fw_txbuf_addr = cur_pg_addr;
1163 cur_pg_addr -= RSVD_PG_CPU_INSTRUCTION_NUM;
1164 fifo->rsvd_cpu_instr_addr = cur_pg_addr;
1165 cur_pg_addr -= RSVD_PG_H2CQ_NUM;
1166 fifo->rsvd_h2cq_addr = cur_pg_addr;
1167 cur_pg_addr -= RSVD_PG_H2C_STATICINFO_NUM;
1168 fifo->rsvd_h2c_sta_info_addr = cur_pg_addr;
1169 cur_pg_addr -= RSVD_PG_H2C_EXTRAINFO_NUM;
1170 fifo->rsvd_h2c_info_addr = cur_pg_addr;
1172 cur_pg_addr -= fifo->rsvd_drv_pg_num;
1173 fifo->rsvd_drv_addr = cur_pg_addr;
1175 if (fifo->rsvd_boundary != fifo->rsvd_drv_addr) {
1177 return -EINVAL;
1187 const struct rtw_chip_info *chip = rtwdev->chip;
1188 struct rtw_fifo_conf *fifo = &rtwdev->fifo;
1190 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_1, pg_tbl->hq_num);
1191 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_2, pg_tbl->lq_num);
1192 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_3, pg_tbl->nq_num);
1193 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_4, pg_tbl->exq_num);
1197 rtw_write16(rtwdev, REG_FIFOPAGE_CTRL_2, fifo->rsvd_boundary);
1200 rtw_write16(rtwdev, REG_BCNQ_BDNY_V1, fifo->rsvd_boundary);
1201 rtw_write16(rtwdev, REG_FIFOPAGE_CTRL_2 + 2, fifo->rsvd_boundary);
1202 rtw_write16(rtwdev, REG_BCNQ1_BDNY_V1, fifo->rsvd_boundary);
1203 rtw_write32(rtwdev, REG_RXFF_BNDY, chip->rxff_size - C2H_PKT_BUF - 1);
1205 if (rtwdev->hci.type == RTW_HCI_TYPE_USB) {
1207 chip->usb_tx_agg_desc_num);
1209 rtw_write8(rtwdev, REG_AUTO_LLT_V1 + 3, chip->usb_tx_agg_desc_num);
1216 return -EBUSY;
1227 const struct rtw_chip_info *chip = rtwdev->chip;
1228 struct rtw_fifo_conf *fifo = &rtwdev->fifo;
1231 val32 = BIT_RQPN_NE(pg_tbl->nq_num, pg_tbl->exq_num);
1233 val32 = BIT_RQPN_HLP(pg_tbl->hq_num, pg_tbl->lq_num, pubq_num);
1236 rtw_write8(rtwdev, REG_TRXFF_BNDY, fifo->rsvd_boundary);
1237 rtw_write16(rtwdev, REG_TRXFF_BNDY + 2, chip->rxff_size - REPORT_BUF - 1);
1238 rtw_write8(rtwdev, REG_DWBCN0_CTRL + 1, fifo->rsvd_boundary);
1239 rtw_write8(rtwdev, REG_BCNQ_BDNY, fifo->rsvd_boundary);
1240 rtw_write8(rtwdev, REG_MGQ_BDNY, fifo->rsvd_boundary);
1241 rtw_write8(rtwdev, REG_WMAC_LBK_BF_HD, fifo->rsvd_boundary);
1246 return -EBUSY;
1253 const struct rtw_chip_info *chip = rtwdev->chip;
1254 struct rtw_fifo_conf *fifo = &rtwdev->fifo;
1265 pg_tbl = &chip->page_table[1];
1268 if (rtwdev->hci.bulkout_num == 2)
1269 pg_tbl = &chip->page_table[2];
1270 else if (rtwdev->hci.bulkout_num == 3)
1271 pg_tbl = &chip->page_table[3];
1272 else if (rtwdev->hci.bulkout_num == 4)
1273 pg_tbl = &chip->page_table[4];
1275 return -EINVAL;
1278 pg_tbl = &chip->page_table[0];
1281 return -EINVAL;
1284 pubq_num = fifo->acq_pg_num - pg_tbl->hq_num - pg_tbl->lq_num -
1285 pg_tbl->nq_num - pg_tbl->exq_num - pg_tbl->gapq_num;
1294 struct rtw_fifo_conf *fifo = &rtwdev->fifo;
1305 h2cq_addr = fifo->rsvd_h2cq_addr << TX_PAGE_SIZE_SHIFT;
1335 h2cq_free = wp >= rp ? h2cq_size - (wp - rp) : rp - wp;
1339 return -EINVAL;
1384 const struct rtw_chip_info *chip = rtwdev->chip;
1391 ret = chip->ops->mac_init(rtwdev);