Lines Matching +full:chip +full:- +full:to +full:- +full:chip
1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
93 rtw_err(rtwdev, "failed to poll REG_SDIO_HSUS_CTRL[1]");
94 return -ETIMEDOUT;
107 return -EINVAL;
156 if (cmd->base == RTW_PWR_ADDR_SDIO)
157 offset = cmd->offset | SDIO_LOCAL_OFFSET;
159 offset = cmd->offset;
161 if (do_pwr_poll_cmd(rtwdev, offset, cmd->mask, cmd->value))
169 if (rtwdev->chip->id == RTW_CHIP_TYPE_8723D)
173 if (rtwdev->chip->id == RTW_CHIP_TYPE_8723D)
176 if (do_pwr_poll_cmd(rtwdev, offset, cmd->mask, cmd->value))
180 rtw_err(rtwdev, "failed to poll offset=0x%x mask=0x%x value=0x%x\n",
181 offset, cmd->mask, cmd->value);
182 return -EBUSY;
193 for (cur_cmd = cmd; cur_cmd->cmd != RTW_PWR_CMD_END; cur_cmd++) {
194 if (!(cur_cmd->intf_mask & intf_mask) ||
195 !(cur_cmd->cut_mask & cut_mask))
198 switch (cur_cmd->cmd) {
200 offset = cur_cmd->offset;
202 if (cur_cmd->base == RTW_PWR_ADDR_SDIO)
206 value &= ~cur_cmd->mask;
207 value |= (cur_cmd->value & cur_cmd->mask);
212 return -EBUSY;
215 if (cur_cmd->value == RTW_PWR_DELAY_US)
216 udelay(cur_cmd->offset);
218 mdelay(cur_cmd->offset);
223 return -EINVAL;
240 cut = rtwdev->hal.cut_version;
253 return -EINVAL;
274 const struct rtw_chip_info *chip = rtwdev->chip;
282 rpwm = rtw_read8(rtwdev, rtwdev->hci.rpwm_addr);
287 rtw_write8(rtwdev, rtwdev->hci.rpwm_addr, rpwm);
300 return -EALREADY;
308 clear_bit(RTW_FLAG_POWERON, rtwdev->flags);
310 pwr_seq = pwr_on ? chip->pwr_on_seq : chip->pwr_off_seq;
314 if (chip->id == RTW_CHIP_TYPE_8822C ||
315 chip->id == RTW_CHIP_TYPE_8822B ||
316 chip->id == RTW_CHIP_TYPE_8821C)
324 set_bit(RTW_FLAG_POWERON, rtwdev->flags);
331 u8 sys_func_en = rtwdev->chip->sys_func_en;
343 /* disable boot-from-flash for driver's DL FW */
386 if (ret == -EALREADY) {
424 dmem_size = le32_to_cpu(fw_hdr->dmem_size);
425 imem_size = le32_to_cpu(fw_hdr->imem_size);
426 emem_size = (fw_hdr->mem_usage & BIT(4)) ?
427 le32_to_cpu(fw_hdr->emem_size) : 0;
464 /* set HIQ to hi priority */
472 /* DLFW only use HIQ, map HIQ to hi priority */
495 rtw_write32(rtwdev, REG_RQPN_CTRL_2, bckp[bckp_idx - 1].val);
537 return -ENOMEM;
550 !((size + TX_DESC_SIZE) & (512 - 1)))
555 rtw_err(rtwdev, "failed to download rsvd page\n");
568 return -EBUSY;
579 return -EBUSY;
586 return -EBUSY;
596 rtw_dbg(rtwdev, RTW_DBG_FW, "busy to start ddma\n");
597 return -EBUSY;
603 rtw_dbg(rtwdev, RTW_DBG_FW, "busy to complete ddma\n");
604 return -EBUSY;
648 const struct rtw_chip_info *chip = rtwdev->chip;
649 u32 desc_size = chip->tx_pkt_desc_sz;
686 residue_size -= pkt_size;
690 return -EINVAL;
707 dmem_size = le32_to_cpu(fw_hdr->dmem_size);
708 imem_size = le32_to_cpu(fw_hdr->imem_size);
709 emem_size = (fw_hdr->mem_usage & BIT(4)) ?
710 le32_to_cpu(fw_hdr->emem_size) : 0;
720 addr = le32_to_cpu(fw_hdr->dmem_addr);
727 addr = le32_to_cpu(fw_hdr->imem_addr);
735 addr = le32_to_cpu(fw_hdr->emem_addr);
754 return -EINVAL;
779 const u8 *data = fw->firmware->data;
780 u32 size = fw->firmware->size;
785 return -EINVAL;
788 return -EBUSY;
806 ret = -EBUSY;
817 rtwdev->h2c.last_box_num = 0;
818 rtwdev->h2c.seq = 0;
820 set_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags);
848 rtw_err(rtwdev, "failed to check fw download ready\n");
868 remain_size = size & (DLFW_BLK_SIZE_LEGACY - 1);
896 size -= sizeof(struct rtw_fw_hdr_legacy);
899 last_page_size = size & (DLFW_PAGE_SIZE_LEGACY - 1);
911 rtw_err(rtwdev, "failed to check download firmware report\n");
912 return -EINVAL;
938 rtw_err(rtwdev, "failed to validate firmware\n");
939 return -EINVAL;
948 if (rtwdev->chip->id == RTW_CHIP_TYPE_8703B &&
954 ret = download_firmware_legacy(rtwdev, fw->firmware->data, fw->firmware->size);
966 rtwdev->h2c.last_box_num = 0;
967 rtwdev->h2c.seq = 0;
969 set_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags);
993 rtwdev->chip->id == RTW_CHIP_TYPE_8821C)
1002 const struct rtw_rqpn *rqpn = rtwdev->fifo.rqpn;
1006 prio_queues |= BIT(rqpn->dma_map_vo);
1008 prio_queues |= BIT(rqpn->dma_map_vi);
1010 prio_queues |= BIT(rqpn->dma_map_be);
1012 prio_queues |= BIT(rqpn->dma_map_bk);
1020 const struct rtw_chip_info *chip = rtwdev->chip;
1029 addr = &chip->prioq_addrs->prio[prio_queue];
1030 wsize = chip->prioq_addrs->wsize;
1034 rsvd_page = wsize ? rtw_read16(rtwdev, addr->rsvd) :
1035 rtw_read8(rtwdev, addr->rsvd);
1036 avail_page = wsize ? rtw_read16(rtwdev, addr->avail) :
1037 rtw_read8(rtwdev, addr->avail);
1046 * Note that if we want to flush the tx queue when having a lot of
1048 * And it requires like ~2secs to flush the full priority queue.
1052 "timed out to flush queue %d\n", prio_queue);
1069 /* If all of the hardware queues are requested to flush,
1073 if (queues == BIT(rtwdev->hw->queues) - 1 || !rtwdev->fifo.rqpn)
1074 prio_queues = BIT(RTW_DMA_MAPPING_MAX) - 1;
1083 const struct rtw_chip_info *chip = rtwdev->chip;
1089 rqpn = &chip->rqpn_table[1];
1092 if (rtwdev->hci.bulkout_num == 2)
1093 rqpn = &chip->rqpn_table[2];
1094 else if (rtwdev->hci.bulkout_num == 3)
1095 rqpn = &chip->rqpn_table[3];
1096 else if (rtwdev->hci.bulkout_num == 4)
1097 rqpn = &chip->rqpn_table[4];
1099 return -EINVAL;
1102 rqpn = &chip->rqpn_table[0];
1105 return -EINVAL;
1108 rtwdev->fifo.rqpn = rqpn;
1109 txdma_pq_map |= BIT_TXDMA_HIQ_MAP(rqpn->dma_map_hi);
1110 txdma_pq_map |= BIT_TXDMA_MGQ_MAP(rqpn->dma_map_mg);
1111 txdma_pq_map |= BIT_TXDMA_BKQ_MAP(rqpn->dma_map_bk);
1112 txdma_pq_map |= BIT_TXDMA_BEQ_MAP(rqpn->dma_map_be);
1113 txdma_pq_map |= BIT_TXDMA_VIQ_MAP(rqpn->dma_map_vi);
1114 txdma_pq_map |= BIT_TXDMA_VOQ_MAP(rqpn->dma_map_vo);
1134 const struct rtw_chip_info *chip = rtwdev->chip;
1135 struct rtw_fifo_conf *fifo = &rtwdev->fifo;
1137 u8 csi_buf_pg_num = chip->csi_buf_pg_num;
1140 fifo->rsvd_drv_pg_num = chip->rsvd_drv_pg_num;
1141 fifo->txff_pg_num = chip->txff_size / chip->page_size;
1143 fifo->rsvd_pg_num = fifo->rsvd_drv_pg_num;
1145 fifo->rsvd_pg_num = fifo->rsvd_drv_pg_num +
1153 if (fifo->rsvd_pg_num > fifo->txff_pg_num)
1154 return -ENOMEM;
1156 fifo->acq_pg_num = fifo->txff_pg_num - fifo->rsvd_pg_num;
1157 fifo->rsvd_boundary = fifo->txff_pg_num - fifo->rsvd_pg_num;
1159 cur_pg_addr = fifo->txff_pg_num;
1161 cur_pg_addr -= csi_buf_pg_num;
1162 fifo->rsvd_csibuf_addr = cur_pg_addr;
1163 cur_pg_addr -= RSVD_PG_FW_TXBUF_NUM;
1164 fifo->rsvd_fw_txbuf_addr = cur_pg_addr;
1165 cur_pg_addr -= RSVD_PG_CPU_INSTRUCTION_NUM;
1166 fifo->rsvd_cpu_instr_addr = cur_pg_addr;
1167 cur_pg_addr -= RSVD_PG_H2CQ_NUM;
1168 fifo->rsvd_h2cq_addr = cur_pg_addr;
1169 cur_pg_addr -= RSVD_PG_H2C_STATICINFO_NUM;
1170 fifo->rsvd_h2c_sta_info_addr = cur_pg_addr;
1171 cur_pg_addr -= RSVD_PG_H2C_EXTRAINFO_NUM;
1172 fifo->rsvd_h2c_info_addr = cur_pg_addr;
1174 cur_pg_addr -= fifo->rsvd_drv_pg_num;
1175 fifo->rsvd_drv_addr = cur_pg_addr;
1177 if (fifo->rsvd_boundary != fifo->rsvd_drv_addr) {
1179 return -EINVAL;
1190 const struct rtw_chip_info *chip = rtwdev->chip;
1191 struct rtw_fifo_conf *fifo = &rtwdev->fifo;
1193 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_1, pg_tbl->hq_num);
1194 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_2, pg_tbl->lq_num);
1195 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_3, pg_tbl->nq_num);
1196 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_4, pg_tbl->exq_num);
1200 rtw_write16(rtwdev, REG_FIFOPAGE_CTRL_2, fifo->rsvd_boundary);
1203 rtw_write16(rtwdev, REG_BCNQ_BDNY_V1, fifo->rsvd_boundary);
1204 rtw_write16(rtwdev, REG_FIFOPAGE_CTRL_2 + 2, fifo->rsvd_boundary);
1205 rtw_write16(rtwdev, REG_BCNQ1_BDNY_V1, fifo->rsvd_boundary);
1206 rtw_write32(rtwdev, REG_RXFF_BNDY, chip->rxff_size - C2H_PKT_BUF - 1);
1208 if (rtwdev->hci.type == RTW_HCI_TYPE_USB) {
1210 chip->usb_tx_agg_desc_num);
1212 rtw_write8(rtwdev, REG_AUTO_LLT_V1 + 3, chip->usb_tx_agg_desc_num);
1219 return -EBUSY;
1230 const struct rtw_chip_info *chip = rtwdev->chip;
1231 struct rtw_fifo_conf *fifo = &rtwdev->fifo;
1234 val32 = BIT_RQPN_NE(pg_tbl->nq_num, pg_tbl->exq_num);
1236 val32 = BIT_RQPN_HLP(pg_tbl->hq_num, pg_tbl->lq_num, pubq_num);
1239 rtw_write8(rtwdev, REG_TRXFF_BNDY, fifo->rsvd_boundary);
1240 rtw_write16(rtwdev, REG_TRXFF_BNDY + 2, chip->rxff_size - REPORT_BUF - 1);
1241 rtw_write8(rtwdev, REG_DWBCN0_CTRL + 1, fifo->rsvd_boundary);
1242 rtw_write8(rtwdev, REG_BCNQ_BDNY, fifo->rsvd_boundary);
1243 rtw_write8(rtwdev, REG_MGQ_BDNY, fifo->rsvd_boundary);
1244 rtw_write8(rtwdev, REG_WMAC_LBK_BF_HD, fifo->rsvd_boundary);
1249 return -EBUSY;
1256 const struct rtw_chip_info *chip = rtwdev->chip;
1257 struct rtw_fifo_conf *fifo = &rtwdev->fifo;
1268 pg_tbl = &chip->page_table[1];
1271 if (rtwdev->hci.bulkout_num == 2)
1272 pg_tbl = &chip->page_table[2];
1273 else if (rtwdev->hci.bulkout_num == 3)
1274 pg_tbl = &chip->page_table[3];
1275 else if (rtwdev->hci.bulkout_num == 4)
1276 pg_tbl = &chip->page_table[4];
1278 return -EINVAL;
1281 pg_tbl = &chip->page_table[0];
1284 return -EINVAL;
1287 pubq_num = fifo->acq_pg_num - pg_tbl->hq_num - pg_tbl->lq_num -
1288 pg_tbl->nq_num - pg_tbl->exq_num - pg_tbl->gapq_num;
1297 struct rtw_fifo_conf *fifo = &rtwdev->fifo;
1308 h2cq_addr = fifo->rsvd_h2cq_addr << TX_PAGE_SIZE_SHIFT;
1338 h2cq_free = wp >= rp ? h2cq_size - (wp - rp) : rp - wp;
1342 return -EINVAL;
1387 const struct rtw_chip_info *chip = rtwdev->chip;
1394 ret = chip->ops->mac_init(rtwdev);