Home
last modified time | relevance | path

Searched full:ccu1 (Results 1 – 24 of 24) sorted by relevance

/linux/arch/arm/boot/dts/nxp/lpc/
H A Dlpc18xx.dtsi34 clocks = <&ccu1 CLK_CPU_CORE>;
77 clocks = <&ccu1 CLK_CPU_SCT>;
89 clocks = <&ccu1 CLK_CPU_DMA>;
108 clocks = <&ccu1 CLK_SPIFI>, <&ccu1 CLK_CPU_SPIFI>;
118 clocks = <&ccu2 CLK_SDIO>, <&ccu1 CLK_CPU_SDIO>;
128 clocks = <&ccu1 CLK_CPU_USB0>;
140 clocks = <&ccu1 CLK_CPU_USB1>;
148 clocks = <&ccu1 CLK_CPU_EMCDIV>, <&ccu1 CLK_CPU_EMC>;
165 clocks = <&cgu BASE_LCD_CLK>, <&ccu1 CLK_CPU_LCD>;
175 clocks = <&ccu1 CLK_CPU_EEPROM>;
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dlpc1850-ccu.txt4 or off independently by the Clock Control Units CCU1 or CCU2. The
5 branch clocks are distributed between CCU1 and CCU2.
43 ccu1: clock-controller@40051000 {
74 clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>;
H A Dlpc1850-creg-clk.txt48 clocks = <&creg_clk 0>, <&ccu1 CLK_CPU_BUS>;
H A Dlpc1850-cgu.txt126 clocks = <&cgu BASE_LCD_CLK>, <&ccu1 CLK_CPU_LCD>;
/linux/Documentation/devicetree/bindings/dma/
H A Dlpc1850-dmamux.txt24 clocks = <&ccu1 CLK_CPU_DMA>;
49 clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>;
/linux/Documentation/devicetree/bindings/mtd/
H A Dnxp-spifi.txt40 clocks = <&ccu1 CLK_SPIFI>, <&ccu1 CLK_CPU_SPIFI>;
/linux/Documentation/devicetree/bindings/reset/
H A Dnxp,lpc1850-rgu.txt68 clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_BUS>;
79 clocks = <&ccu1 CLK_CPU_ETHERNET>;
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Darm,pl172.txt93 clocks = <&ccu1 CLK_CPU_EMCDIV>, <&ccu1 CLK_CPU_EMC>;
/linux/Documentation/devicetree/bindings/net/
H A Dnxp,lpc1850-dwmac.txt16 clocks = <&ccu1 CLK_CPU_ETHERNET>;
/linux/Documentation/devicetree/bindings/pwm/
H A Dlpc1850-sct-pwm.txt17 clocks =<&ccu1 CLK_CPU_SCT>;
/linux/Documentation/devicetree/bindings/nvmem/
H A Dlpc1857-eeprom.txt24 clocks = <&ccu1 CLK_CPU_EEPROM>;
/linux/Documentation/devicetree/bindings/phy/
H A Dphy-lpc18xx-usb-otg.txt23 clocks = <&ccu1 CLK_USB0>;
/linux/Documentation/devicetree/bindings/i2c/
H A Dnxp,lpc1788-i2c.yaml51 clocks = <&ccu1 CLK_APB1_I2C0>;
/linux/Documentation/devicetree/bindings/watchdog/
H A Dnxp,lpc1850-wwdt.yaml49 clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_WWDT>;
/linux/Documentation/devicetree/bindings/iio/dac/
H A Dnxp,lpc1850-dac.yaml53 clocks = <&ccu1 CLK_APB3_DAC>;
/linux/Documentation/devicetree/bindings/iio/adc/
H A Dnxp,lpc1850-adc.yaml56 clocks = <&ccu1 CLK_APB3_ADC0>;
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dnxp,lpc1850-scu.txt37 clocks = <&ccu1 CLK_CPU_SCU>;
/linux/include/dt-bindings/clock/
H A Dlpc18xx-ccu.h12 /* Clock Control Unit 1 (CCU1) clock offsets */
/linux/Documentation/devicetree/bindings/gpio/
H A Dnxp,lpc1850-gpio.txt38 clocks = <&ccu1 CLK_CPU_GPIO>;
/linux/include/dt-bindings/memory/
H A Dmt8192-larb-port.h23 * CCU1 0x4400_0000 ~ 0x47ff_ffff larb14: port 4/5
H A Dmt8186-memory-port.h28 * CCU1 0x24400_0000 ~ 0x247ff_ffff larb14: port 4/5
H A Dmt8195-memory-port.h26 * CCU1 0x24400_0000 ~ 0x247ff_ffff larb18: port 2/3
H A Dmediatek,mt8188-memory-port.h59 * CCU1 0x24400_0000 ~ 0x247ff_ffff larb27(24): port 2/3
/linux/drivers/iommu/
H A Dmtk_iommu.c360 { .iova_base = 0x244000000ULL, .size = 0x4000000}, /* CCU1 */