1*89f271c4SJoachim Eastwood* NXP SPI Flash Interface (SPIFI) 2*89f271c4SJoachim Eastwood 3*89f271c4SJoachim EastwoodNXP SPIFI is a specialized SPI interface for serial Flash devices. 4*89f271c4SJoachim EastwoodIt supports one Flash device with 1-, 2- and 4-bits width in SPI 5*89f271c4SJoachim Eastwoodmode 0 or 3. The controller operates in either command or memory 6*89f271c4SJoachim Eastwoodmode. In memory mode the Flash is accessible from the CPU as 7*89f271c4SJoachim Eastwoodnormal memory. 8*89f271c4SJoachim Eastwood 9*89f271c4SJoachim EastwoodRequired properties: 10*89f271c4SJoachim Eastwood - compatible : Should be "nxp,lpc1773-spifi" 11*89f271c4SJoachim Eastwood - reg : the first contains the register location and length, 12*89f271c4SJoachim Eastwood the second contains the memory mapping address and length 13*89f271c4SJoachim Eastwood - reg-names: Should contain the reg names "spifi" and "flash" 14*89f271c4SJoachim Eastwood - interrupts : Should contain the interrupt for the device 15*89f271c4SJoachim Eastwood - clocks : The clocks needed by the SPIFI controller 16*89f271c4SJoachim Eastwood - clock-names : Should contain the clock names "spifi" and "reg" 17*89f271c4SJoachim Eastwood 18*89f271c4SJoachim EastwoodOptional properties: 19*89f271c4SJoachim Eastwood - resets : phandle + reset specifier 20*89f271c4SJoachim Eastwood 21*89f271c4SJoachim EastwoodThe SPI Flash must be a child of the SPIFI node and must have a 22*89f271c4SJoachim Eastwoodcompatible property as specified in bindings/mtd/jedec,spi-nor.txt 23*89f271c4SJoachim Eastwood 24*89f271c4SJoachim EastwoodOptionally it can also contain the following properties. 25*89f271c4SJoachim Eastwood - spi-cpol : Controller only supports mode 0 and 3 so either 26*89f271c4SJoachim Eastwood both spi-cpol and spi-cpha should be present or 27*89f271c4SJoachim Eastwood none of them 28*89f271c4SJoachim Eastwood - spi-cpha : See above 29*89f271c4SJoachim Eastwood - spi-rx-bus-width : Used to select how many pins that are used 30*89f271c4SJoachim Eastwood for input on the controller 31*89f271c4SJoachim Eastwood 32*89f271c4SJoachim EastwoodSee bindings/spi/spi-bus.txt for more information. 33*89f271c4SJoachim Eastwood 34*89f271c4SJoachim EastwoodExample: 35*89f271c4SJoachim Eastwoodspifi: spifi@40003000 { 36*89f271c4SJoachim Eastwood compatible = "nxp,lpc1773-spifi"; 37*89f271c4SJoachim Eastwood reg = <0x40003000 0x1000>, <0x14000000 0x4000000>; 38*89f271c4SJoachim Eastwood reg-names = "spifi", "flash"; 39*89f271c4SJoachim Eastwood interrupts = <30>; 40*89f271c4SJoachim Eastwood clocks = <&ccu1 CLK_SPIFI>, <&ccu1 CLK_CPU_SPIFI>; 41*89f271c4SJoachim Eastwood clock-names = "spifi", "reg"; 42*89f271c4SJoachim Eastwood resets = <&rgu 53>; 43*89f271c4SJoachim Eastwood 44*89f271c4SJoachim Eastwood flash@0 { 45*89f271c4SJoachim Eastwood compatible = "jedec,spi-nor"; 46*89f271c4SJoachim Eastwood spi-cpol; 47*89f271c4SJoachim Eastwood spi-cpha; 48*89f271c4SJoachim Eastwood spi-rx-bus-width = <4>; 49*89f271c4SJoachim Eastwood #address-cells = <1>; 50*89f271c4SJoachim Eastwood #size-cells = <1>; 51*89f271c4SJoachim Eastwood 52*89f271c4SJoachim Eastwood partition@0 { 53*89f271c4SJoachim Eastwood label = "data"; 54*89f271c4SJoachim Eastwood reg = <0 0x200000>; 55*89f271c4SJoachim Eastwood }; 56*89f271c4SJoachim Eastwood }; 57*89f271c4SJoachim Eastwood}; 58*89f271c4SJoachim Eastwood 59