1ddfb1574SJoachim Eastwood* NXP LPC1850 Clock Control Unit (CCU) 2ddfb1574SJoachim Eastwood 3ddfb1574SJoachim EastwoodEach CGU base clock has several clock branches which can be turned on 4ddfb1574SJoachim Eastwoodor off independently by the Clock Control Units CCU1 or CCU2. The 5ddfb1574SJoachim Eastwoodbranch clocks are distributed between CCU1 and CCU2. 6ddfb1574SJoachim Eastwood 7ddfb1574SJoachim Eastwood - Above text taken from NXP LPC1850 User Manual. 8ddfb1574SJoachim Eastwood 9ddfb1574SJoachim EastwoodThis binding uses the common clock binding: 10ddfb1574SJoachim Eastwood Documentation/devicetree/bindings/clock/clock-bindings.txt 11ddfb1574SJoachim Eastwood 12ddfb1574SJoachim EastwoodRequired properties: 13ddfb1574SJoachim Eastwood- compatible: 14ddfb1574SJoachim Eastwood Should be "nxp,lpc1850-ccu" 15ddfb1574SJoachim Eastwood- reg: 16ddfb1574SJoachim Eastwood Shall define the base and range of the address space 17ddfb1574SJoachim Eastwood containing clock control registers 18ddfb1574SJoachim Eastwood- #clock-cells: 19ddfb1574SJoachim Eastwood Shall have value <1>. The permitted clock-specifier values 20ddfb1574SJoachim Eastwood are the branch clock names defined in table below. 21ddfb1574SJoachim Eastwood- clocks: 22ddfb1574SJoachim Eastwood Shall contain a list of phandles for the base clocks routed 23ddfb1574SJoachim Eastwood from the CGU to the specific CCU. See mapping of base clocks 24ddfb1574SJoachim Eastwood and CCU in table below. 25ddfb1574SJoachim Eastwood- clock-names: 26ddfb1574SJoachim Eastwood Shall contain a list of names for the base clock routed 27ddfb1574SJoachim Eastwood from the CGU to the specific CCU. Valid CCU clock names: 28ddfb1574SJoachim Eastwood "base_usb0_clk", "base_periph_clk", "base_usb1_clk", 29ddfb1574SJoachim Eastwood "base_cpu_clk", "base_spifi_clk", "base_spi_clk", 30ddfb1574SJoachim Eastwood "base_apb1_clk", "base_apb3_clk", "base_adchs_clk", 31ddfb1574SJoachim Eastwood "base_sdio_clk", "base_ssp0_clk", "base_ssp1_clk", 32ddfb1574SJoachim Eastwood "base_uart0_clk", "base_uart1_clk", "base_uart2_clk", 33ddfb1574SJoachim Eastwood "base_uart3_clk", "base_audio_clk" 34ddfb1574SJoachim Eastwood 35ddfb1574SJoachim EastwoodWhich branch clocks that are available on the CCU depends on the 36ddfb1574SJoachim Eastwoodspecific LPC part. Check the user manual for your specific part. 37ddfb1574SJoachim Eastwood 38ddfb1574SJoachim EastwoodA list of CCU clocks can be found in dt-bindings/clock/lpc18xx-ccu.h. 39ddfb1574SJoachim Eastwood 40ddfb1574SJoachim EastwoodExample board file: 41ddfb1574SJoachim Eastwood 42ddfb1574SJoachim Eastwoodsoc { 43ddfb1574SJoachim Eastwood ccu1: clock-controller@40051000 { 44ddfb1574SJoachim Eastwood compatible = "nxp,lpc1850-ccu"; 45ddfb1574SJoachim Eastwood reg = <0x40051000 0x1000>; 46ddfb1574SJoachim Eastwood #clock-cells = <1>; 47ddfb1574SJoachim Eastwood clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>, 48ddfb1574SJoachim Eastwood <&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>, 49ddfb1574SJoachim Eastwood <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>, 50ddfb1574SJoachim Eastwood <&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>; 51ddfb1574SJoachim Eastwood clock-names = "base_apb3_clk", "base_apb1_clk", 52ddfb1574SJoachim Eastwood "base_spifi_clk", "base_cpu_clk", 53ddfb1574SJoachim Eastwood "base_periph_clk", "base_usb0_clk", 54ddfb1574SJoachim Eastwood "base_usb1_clk", "base_spi_clk"; 55ddfb1574SJoachim Eastwood }; 56ddfb1574SJoachim Eastwood 57ddfb1574SJoachim Eastwood ccu2: clock-controller@40052000 { 58ddfb1574SJoachim Eastwood compatible = "nxp,lpc1850-ccu"; 59ddfb1574SJoachim Eastwood reg = <0x40052000 0x1000>; 60ddfb1574SJoachim Eastwood #clock-cells = <1>; 61ddfb1574SJoachim Eastwood clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>, 62ddfb1574SJoachim Eastwood <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>, 63ddfb1574SJoachim Eastwood <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>, 64ddfb1574SJoachim Eastwood <&cgu BASE_SSP0_CLK>, <&cgu BASE_SDIO_CLK>; 65ddfb1574SJoachim Eastwood clock-names = "base_audio_clk", "base_uart3_clk", 66ddfb1574SJoachim Eastwood "base_uart2_clk", "base_uart1_clk", 67ddfb1574SJoachim Eastwood "base_uart0_clk", "base_ssp1_clk", 68ddfb1574SJoachim Eastwood "base_ssp0_clk", "base_sdio_clk"; 69ddfb1574SJoachim Eastwood }; 70ddfb1574SJoachim Eastwood 71*47aab533SBjorn Helgaas /* A user of CCU branch clocks */ 72ddfb1574SJoachim Eastwood uart1: serial@40082000 { 73ddfb1574SJoachim Eastwood ... 74ddfb1574SJoachim Eastwood clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>; 75ddfb1574SJoachim Eastwood ... 76ddfb1574SJoachim Eastwood }; 77ddfb1574SJoachim Eastwood}; 78