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/linux/Documentation/devicetree/bindings/net/can/
H A Drockchip,rk3568v2-canfd.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/can/rockchip,rk3568v2-canfd.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 Rockchip CAN-FD controller
11 - Marc Kleine-Budde <mkl@pengutronix.de>
14 - $ref: can-controller.yaml#
19 - const: rockchip,rk3568v2-canfd
20 - items:
21 - const: rockchip,rk3568v3-canfd
[all …]
H A Dxilinx,can.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 Xilinx CAN and CANFD controller
11 - Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
16 - xlnx,zynq-can-1.0
17 - xlnx,axi-can-1.00.a
18 - xlnx,canfd-1.0
19 - xlnx,canfd-2.0
29 maxItems: 2
[all …]
H A Drenesas,rcar-can.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/can/renesas,rcar-can.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car CAN Controller
10 - Sergei Shtylyov <sergei.shtylyov@gmail.com>
15 - items:
16 - enum:
17 - renesas,can-r8a7778 # R-Car M1-A
18 - renesas,can-r8a7779 # R-Car H1
[all …]
H A Dctu,ctucanfd.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: CTU CAN FD Open-source IP Core
10 Open-source CAN FD IP core developed at the Czech Technical University in Prague
14 [2] datasheet : https://canbus.pages.fel.cvut.cz/ctucanfd_ip_core/doc/Datasheet.pdf
18 [3] project : https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top
21 …tps://dspace.cvut.cz/bitstream/handle/10467/80366/F3-DP-2019-Jerabek-Martin-Jerabek-thesis-2019-ca…
24 - Pavel Pisa <pisa@cmp.felk.cvut.cz>
25 - Ondrej Ille <ondrej.ille@gmail.com>
[all …]
/linux/drivers/net/can/
H A Dxilinx_can.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2012 - 2022 Xilinx, Inc.
6 * Copyright (C) 2017 - 2018 Sandvik Mining and Construction Oy
9 * This driver is developed for AXI CAN IP, AXI CANFD IP, CANPS and CANFD PS Controller.
95 /* CAN register bit masks - XCAN_<REG>_<BIT>_MASK */
102 #define XCAN_2_BRPR_TDCO_MASK GENMASK(13, 8) /* TDCO for CANFD 2.0 */
104 #define XCAN_BTR_TS2_MASK 0x00000070 /* Time segment 2 */
107 #define XCAN_BTR_TS2_MASK_CANFD 0x00000F00 /* Time segment 2 */
160 #define XCAN_ECC_CFG_REECRX_MASK BIT(2) /* Reset RX FIFO ECC error counters */
164 #define XCAN_ECC_2BIT_CNT_MASK GENMASK(31, 16) /* FIFO ECC 2bit count mask */
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3568.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include "rk356x-base.dtsi"
11 cpu0_opp_table: opp-table-0 {
12 compatible = "operating-points-v2";
13 opp-shared;
15 opp-408000000 {
16 opp-hz = /bits/ 64 <408000000>;
17 opp-microvolt = <850000 850000 1150000>;
18 clock-latency-ns = <40000>;
21 opp-600000000 {
[all …]
/linux/drivers/net/can/usb/etas_es58x/
H A Des58x_fd.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* Driver for ETAS GmbH ES58X USB CAN(-FD) Bus Interfaces.
19 #define ES582_1_NUM_CAN_CH 2
21 #define ES58X_FD_NUM_CAN_CH 2
34 /* Command IDs for ES58X_FD_CMD_TYPE_{CAN,CANFD}. */
54 * enum es58x_fd_ctrlmode - Controller mode.
58 * @ES58X_FD_CTRLMODE_FD: CAN FD according to ISO11898-1.
63 * dominant. (c.f. ISO 11898-1:2015, section 10.4.2.4 "Control
83 __le16 tseg1; /* range: [tseg1_min-1..tseg1_max-1] */
84 __le16 tseg2; /* range: [tseg2_min-1..tseg2_max-1] */
[all …]
/linux/arch/arm64/boot/dts/renesas/
H A Dwhite-hawk-common.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
9 #include "white-hawk-csi-dsi.dtsi"
10 #include "white-hawk-ethernet.dtsi"
13 can_transceiver0: can-phy0 {
15 #phy-cells = <0>;
16 enable-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
17 max-bitrate = <5000000>;
22 clock-frequency = <40000000>;
25 &canfd {
26 pinctrl-0 = <&canfd0_pins>, <&canfd1_pins>, <&can_clk_pins>;
[all …]
H A Drenesas-smarc2.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Device Tree Source for the RZ SMARC Carrier-II Board.
13 * 0 - SMARC SDIO signal is connected to uSD1
14 * 1 - SMARC SDIO signal is connected to M.2 Key E connector
20 * 0 - Connect to GPIO8 PMOD (default)
21 * 1 - Connect to CAN0 transceiver STB pin
24 * 0 - Connect to GPIO9 PMOD (default)
25 * 1 - Connect to CAN1 transceiver STB pin
32 model = "Renesas RZ SMARC Carrier-II Board";
33 compatible = "renesas,smarc2-evk";
[all …]
H A Drzg2ul-smarc.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Device Tree Source for the RZ/G2UL Type-1 SMARC EVK parts
8 #include <dt-bindings/gpio/gpio.h>
9 #include "rzg2ul-smarc-pinfunction.dtsi"
10 #include "rz-smarc-common.dtsi"
13 &canfd {
14 /delete-property/ pinctrl-0;
15 /delete-property/ pinctrl-names;
21 sound-dai = <&ssi1>;
25 clock-frequency = <400000>;
[all …]
H A Debisu.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the Ebisu/Ebisu-4D board
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
33 stdout-path = "serial0:115200n8";
36 audio_clkout: audio-clkout {
39 * but needed to avoid cs2000/rcar_sound probe dead-lock
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <11289600>;
[all …]
H A Drz-smarc-common.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
12 * SSI-WM8978
32 stdout-path = "serial0:115200n8";
36 compatible = "simple-audio-card";
37 simple-audio-card,format = "i2s";
38 simple-audio-card,bitclock-master = <&cpu_dai>;
39 simple-audio-card,frame-master = <&cpu_dai>;
40 simple-audio-card,mclk-fs = <256>;
[all …]
H A Dr9a07g043.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/clock/r9a07g043-cpg.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
15 audio_clk1: audio1-clk {
16 compatible = "fixed-clock";
17 #clock-cells = <0>;
19 clock-frequency = <0>;
22 audio_clk2: audio2-clk {
23 compatible = "fixed-clock";
[all …]
H A Dr9a07g054.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/r9a07g054-cpg.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
16 audio_clk1: audio1-clk {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
20 clock-frequency = <0>;
23 audio_clk2: audio2-clk {
[all …]
H A Dr9a07g044.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/r9a07g044-cpg.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
16 audio_clk1: audio1-clk {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
20 clock-frequency = <0>;
23 audio_clk2: audio2-clk {
[all …]
H A Dr8a77995.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car D3 (R8A77995) SoC
9 #include <dt-bindings/clock/r8a77995-cpg-mssr.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/r8a77995-sysc.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
24 compatible = "fixed-clock";
25 #clock-cells = <0>;
26 clock-frequency = <0>;
[all …]
H A Dr8a77970-eagle.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the Eagle board with R-Car V3M
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
29 stdout-path = "serial0:115200n8";
32 d1p8: regulator-fixed {
33 compatible = "regulator-fixed";
34 regulator-name = "fixed-1.8V";
35 regulator-min-microvolt = <1800000>;
[all …]
H A Dcondor-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the Condor board with R-Car V3H
8 #include <dt-bindings/gpio/gpio.h>
23 stdout-path = "serial0:115200n8";
27 d1_8v: regulator-2 {
28 compatible = "regulator-fixed";
29 regulator-name = "D1.8V";
30 regulator-min-microvolt = <1800000>;
31 regulator-max-microvolt = <1800000>;
32 regulator-boot-on;
[all …]
/linux/drivers/net/can/usb/
H A Dgs_usb.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013-2016 Geschwister Schneider Technologie-,
6 * Entwicklungs- und Vertriebs UG (Haftungsbeschränkt).
8 * Copyright (c) 2023 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de>
28 #include <linux/can/rx-offload.h>
55 CYCLECOUNTER_MASK(32) / GS_USB_TIMESTAMP_TIMER_HZ / 2);
109 * Technologie Entwicklungs- und Vertriebs UG exchanges all data
133 #define GS_CAN_MODE_TRIPLE_SAMPLE BIT(2)
175 #define GS_CAN_FEATURE_TRIPLE_SAMPLE BIT(2)
189 /* internal quirks - keep in GS_CAN_FEATURE space for now */
[all …]
/linux/drivers/net/can/rockchip/
H A Drockchip_canfd-core.c1 // SPDX-License-Identifier: GPL-2.0
4 // Marc Kleine-Budde <kernel@pengutronix.de>
8 // Rockchip CANFD driver
38 /* The rk3568 CAN-FD errata sheet as of Tue 07 Nov 2023 11:25:31 +08:00
68 return __rkcanfd_get_model_str(priv->devtype_data.model); in rkcanfd_get_model_str()
75 * Tsclk = 2 x Tclk x (brp + 1)
78 * for the arbitration and data bit timing) to take the "2 x" into
88 .brp_min = 2, /* value from data sheet x2 */
90 .brp_inc = 2, /* value from data sheet x2 */
100 .brp_min = 2, /* value from data sheet x2 */
[all …]
/linux/Documentation/networking/device_drivers/can/ctu/
H A Dctucanfd-driver.rst1 .. SPDX-License-Identifier: GPL-2.0-or-later
10 ------------------------
19 `Vivado integration <https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top>`_
20 and Intel Cyclone V 5CSEMA4U23C6 based DE0-Nano-SoC Terasic board
21 `QSys integration <https://gitlab.fel.cvut.cz/canbus/intel-soc-ctucanfd>`_
23 `PCIe integration <https://gitlab.fel.cvut.cz/canbus/pcie-ctucanfd>`_ of the core.
33 version of emulation support can be cloned from ctu-canfd branch of QEMU local
34 development `repository <https://gitlab.fel.cvut.cz/canbus/qemu-canbus>`_.
38 ---------------
59 it allows for device hot-plug.
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mm-mx8menlo.dts1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * Copyright 2021-2022 Marek Vasut <marex@denx.de>
6 /dts-v1/;
8 #include "imx8mm-verdin.dtsi"
13 "toradex,verdin-imx8mm-nonwifi",
14 "toradex,verdin-imx8mm",
17 /delete-node/ gpio-keys;
20 compatible = "gpio-leds";
21 pinctrl-names = "default";
22 pinctrl-0 = <&pinctrl_led>;
[all …]
/linux/drivers/clk/renesas/
H A Dr8a77995-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
7 * Based on r8a7795-cpg-mssr.c
16 #include <linux/soc/renesas/rcar-rst.h>
18 #include <dt-bindings/clock/r8a77995-cpg-mssr.h>
20 #include "renesas-cpg-mssr.h"
21 #include "rcar-gen3-cpg.h"
63 DEF_FIXED(".pll0d2", CLK_PLL0D2, CLK_PLL0, 2, 1),
66 DEF_FIXED(".pll1d2", CLK_PLL1D2, CLK_PLL1, 2, 1),
68 DEF_FIXED(".s0", CLK_S0, CLK_PLL1, 2, 1),
72 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
[all …]
H A Dr8a77980-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
8 * Based on r8a7795-cpg-mssr.c
16 #include <linux/soc/renesas/rcar-rst.h>
19 #include <dt-bindings/clock/r8a77980-cpg-mssr.h>
21 #include "renesas-cpg-mssr.h"
22 #include "rcar-gen3-cpg.h"
62 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
63 DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
64 DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
68 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
[all …]
/linux/include/uapi/linux/
H A Dif_ether.h1 /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
19 * 2 of the License, or (at your option) any later version.
33 #define ETH_TLEN 2 /* Octets in ethernet type field */
51 #define ETH_P_ERSPAN2 0x22EB /* ERSPAN version 2 (type III) */
58 #define ETH_P_BATMAN 0x4305 /* B.A.T.M.A.N.-Advanced packet [ NOT AN OFFICIALLY REGISTERED ID ] */
77 #define ETH_P_WCCP 0x883E /* Web-cache coordination protocol
78 * defined in draft-wilson-wrec-wccp-v2-00.txt */
85 #define ETH_P_ATMFATE 0x8884 /* Frame-based ATM Transport
104 #define ETH_P_PRP 0x88FB /* IEC 62439-3 PRP/HSRv0 */
111 #define ETH_P_HSR 0x892F /* IEC 62439-3 HSRv1 */
[all …]

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