Lines Matching +full:canfd +full:- +full:2
1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2012 - 2022 Xilinx, Inc.
6 * Copyright (C) 2017 - 2018 Sandvik Mining and Construction Oy
9 * This driver is developed for AXI CAN IP, AXI CANFD IP, CANPS and CANFD PS Controller.
95 /* CAN register bit masks - XCAN_<REG>_<BIT>_MASK */
102 #define XCAN_2_BRPR_TDCO_MASK GENMASK(13, 8) /* TDCO for CANFD 2.0 */
104 #define XCAN_BTR_TS2_MASK 0x00000070 /* Time segment 2 */
107 #define XCAN_BTR_TS2_MASK_CANFD 0x00000F00 /* Time segment 2 */
160 #define XCAN_ECC_CFG_REECRX_MASK BIT(2) /* Reset RX FIFO ECC error counters */
164 #define XCAN_ECC_2BIT_CNT_MASK GENMASK(31, 16) /* FIFO ECC 2bit count mask */
166 /* CAN register bit shift - XCAN_<REG>_<BIT>_SHIFT */
169 #define XCAN_BTR_TS2_SHIFT 4 /* Time segment 2 */
171 #define XCAN_BTR_TS2_SHIFT_CANFD 8 /* Time segment 2 */
182 /* TX-FIFO-empty interrupt available */
213 * struct xcan_priv - This definition define CAN driver instance
232 * @ecc_rx_2_bit_errors: RXFIFO 2bit ECC count
234 * @ecc_txol_2_bit_errors: TXOLFIFO 2bit ECC count
236 * @ecc_txtl_2_bit_errors: TXTLFIFO 2bit ECC count
280 /* AXI CANFD Arbitration Bittiming constants as per AXI CANFD 1.0 spec */
293 /* AXI CANFD Data Bittiming constants as per AXI CANFD 1.0 specs */
306 /* AXI CANFD 2.0 Arbitration Bittiming constants as per AXI CANFD 2.0 spec */
319 /* AXI CANFD 2.0 Data Bittiming constants as per AXI CANFD 2.0 spec */
332 /* Transmission Delay Compensation constants for CANFD 1.0 */
342 /* Transmission Delay Compensation constants for CANFD 2.0 */
371 * xcan_write_reg_le - Write a value to the device register little endian
381 iowrite32(val, priv->reg_base + reg); in xcan_write_reg_le()
385 * xcan_read_reg_le - Read a value from the device register little endian
394 return ioread32(priv->reg_base + reg); in xcan_read_reg_le()
398 * xcan_write_reg_be - Write a value to the device register big endian
408 iowrite32be(val, priv->reg_base + reg); in xcan_write_reg_be()
412 * xcan_read_reg_be - Read a value from the device register big endian
421 return ioread32be(priv->reg_base + reg); in xcan_read_reg_be()
425 * xcan_rx_int_mask - Get the mask for the receive interrupt
433 * while the FIFO is non-empty, but CAN FD HW does not have it in xcan_rx_int_mask()
435 if (priv->devtype.flags & XCAN_FLAG_RX_FIFO_MULTI) in xcan_rx_int_mask()
442 * set_reset_mode - Resets the CAN device mode
455 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK); in set_reset_mode()
458 while (!(priv->read_reg(priv, XCAN_SR_OFFSET) & XCAN_SR_CONFIG_MASK)) { in set_reset_mode()
461 return -ETIMEDOUT; in set_reset_mode()
467 priv->tx_head = 0; in set_reset_mode()
468 priv->tx_tail = 0; in set_reset_mode()
474 * xcan_set_bittiming - CAN set bit timing routine
483 struct can_bittiming *bt = &priv->can.bittiming; in xcan_set_bittiming()
484 struct can_bittiming *dbt = &priv->can.data_bittiming; in xcan_set_bittiming()
491 is_config_mode = priv->read_reg(priv, XCAN_SR_OFFSET) & in xcan_set_bittiming()
495 "BUG! Cannot set bittiming - CAN is not in config mode\n"); in xcan_set_bittiming()
496 return -EPERM; in xcan_set_bittiming()
500 btr0 = (bt->brp - 1); in xcan_set_bittiming()
503 btr1 = (bt->prop_seg + bt->phase_seg1 - 1); in xcan_set_bittiming()
505 /* Setting Time Segment 2 in BTR Register */ in xcan_set_bittiming()
506 btr1 |= (bt->phase_seg2 - 1) << priv->devtype.btr_ts2_shift; in xcan_set_bittiming()
509 btr1 |= (bt->sjw - 1) << priv->devtype.btr_sjw_shift; in xcan_set_bittiming()
511 priv->write_reg(priv, XCAN_BRPR_OFFSET, btr0); in xcan_set_bittiming()
512 priv->write_reg(priv, XCAN_BTR_OFFSET, btr1); in xcan_set_bittiming()
514 if (priv->devtype.cantype == XAXI_CANFD || in xcan_set_bittiming()
515 priv->devtype.cantype == XAXI_CANFD_2_0) { in xcan_set_bittiming()
517 btr0 = dbt->brp - 1; in xcan_set_bittiming()
518 if (can_tdc_is_enabled(&priv->can)) { in xcan_set_bittiming()
519 if (priv->devtype.cantype == XAXI_CANFD) in xcan_set_bittiming()
520 btr0 |= FIELD_PREP(XCAN_BRPR_TDCO_MASK, priv->can.tdc.tdco) | in xcan_set_bittiming()
523 btr0 |= FIELD_PREP(XCAN_2_BRPR_TDCO_MASK, priv->can.tdc.tdco) | in xcan_set_bittiming()
528 btr1 = dbt->prop_seg + dbt->phase_seg1 - 1; in xcan_set_bittiming()
530 /* Setting Time Segment 2 in BTR Register */ in xcan_set_bittiming()
531 btr1 |= (dbt->phase_seg2 - 1) << priv->devtype.btr_ts2_shift; in xcan_set_bittiming()
534 btr1 |= (dbt->sjw - 1) << priv->devtype.btr_sjw_shift; in xcan_set_bittiming()
536 priv->write_reg(priv, XCAN_F_BRPR_OFFSET, btr0); in xcan_set_bittiming()
537 priv->write_reg(priv, XCAN_F_BTR_OFFSET, btr1); in xcan_set_bittiming()
541 priv->read_reg(priv, XCAN_BRPR_OFFSET), in xcan_set_bittiming()
542 priv->read_reg(priv, XCAN_BTR_OFFSET)); in xcan_set_bittiming()
548 * xcan_chip_start - This the drivers start routine
585 if (priv->ecc_enable) in xcan_chip_start()
588 if (priv->devtype.flags & XCAN_FLAG_RXMNF) in xcan_chip_start()
591 priv->write_reg(priv, XCAN_IER_OFFSET, ier); in xcan_chip_start()
594 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) in xcan_chip_start()
600 * filtering default to non-receipt if all filters are disabled in xcan_chip_start()
602 if (priv->devtype.flags & XCAN_FLAG_EXT_FILTERS) in xcan_chip_start()
603 priv->write_reg(priv, XCAN_AFR_EXT_OFFSET, 0x00000001); in xcan_chip_start()
605 priv->write_reg(priv, XCAN_MSR_OFFSET, reg_msr); in xcan_chip_start()
606 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_CEN_MASK); in xcan_chip_start()
609 priv->read_reg(priv, XCAN_SR_OFFSET)); in xcan_chip_start()
611 priv->can.state = CAN_STATE_ERROR_ACTIVE; in xcan_chip_start()
616 * xcan_do_set_mode - This sets the mode of the driver
638 ret = -EOPNOTSUPP; in xcan_do_set_mode()
646 * xcan_write_frame - Write a frame to HW
654 u32 id, dlc, data[2] = {0, 0}; in xcan_write_frame()
655 struct canfd_frame *cf = (struct canfd_frame *)skb->data; in xcan_write_frame()
660 if (cf->can_id & CAN_EFF_FLAG) { in xcan_write_frame()
662 id = ((cf->can_id & CAN_EFF_MASK) << XCAN_IDR_ID2_SHIFT) & in xcan_write_frame()
664 id |= (((cf->can_id & CAN_EFF_MASK) >> in xcan_write_frame()
665 (CAN_EFF_ID_BITS - CAN_SFF_ID_BITS)) << in xcan_write_frame()
673 if (cf->can_id & CAN_RTR_FLAG) in xcan_write_frame()
678 id = ((cf->can_id & CAN_SFF_MASK) << XCAN_IDR_ID1_SHIFT) & in xcan_write_frame()
681 if (cf->can_id & CAN_RTR_FLAG) in xcan_write_frame()
686 dlc = can_fd_len2dlc(cf->len) << XCAN_DLCR_DLC_SHIFT; in xcan_write_frame()
688 if (cf->flags & CANFD_BRS) in xcan_write_frame()
693 if (!(priv->devtype.flags & XCAN_FLAG_TX_MAILBOXES) && in xcan_write_frame()
694 (priv->devtype.flags & XCAN_FLAG_TXFEMP)) in xcan_write_frame()
695 can_put_echo_skb(skb, ndev, priv->tx_head % priv->tx_max, 0); in xcan_write_frame()
699 priv->tx_head++; in xcan_write_frame()
701 priv->write_reg(priv, XCAN_FRAME_ID_OFFSET(frame_offset), id); in xcan_write_frame()
705 priv->write_reg(priv, XCAN_FRAME_DLC_OFFSET(frame_offset), dlc); in xcan_write_frame()
706 if (priv->devtype.cantype == XAXI_CANFD || in xcan_write_frame()
707 priv->devtype.cantype == XAXI_CANFD_2_0) { in xcan_write_frame()
708 for (i = 0; i < cf->len; i += 4) { in xcan_write_frame()
711 priv->write_reg(priv, ramoff, in xcan_write_frame()
712 be32_to_cpup((__be32 *)(cf->data + i))); in xcan_write_frame()
716 if (cf->len > 0) in xcan_write_frame()
717 data[0] = be32_to_cpup((__be32 *)(cf->data + 0)); in xcan_write_frame()
718 if (cf->len > 4) in xcan_write_frame()
719 data[1] = be32_to_cpup((__be32 *)(cf->data + 4)); in xcan_write_frame()
721 if (!(cf->can_id & CAN_RTR_FLAG)) { in xcan_write_frame()
722 priv->write_reg(priv, in xcan_write_frame()
728 priv->write_reg(priv, in xcan_write_frame()
736 * xcan_start_xmit_fifo - Starts the transmission (FIFO mode)
740 * Return: 0 on success, -ENOSPC if FIFO is full.
748 if (unlikely(priv->read_reg(priv, XCAN_SR_OFFSET) & in xcan_start_xmit_fifo()
750 return -ENOSPC; in xcan_start_xmit_fifo()
752 spin_lock_irqsave(&priv->tx_lock, flags); in xcan_start_xmit_fifo()
756 /* Clear TX-FIFO-empty interrupt for xcan_tx_interrupt() */ in xcan_start_xmit_fifo()
757 if (priv->tx_max > 1) in xcan_start_xmit_fifo()
758 priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_TXFEMP_MASK); in xcan_start_xmit_fifo()
761 if ((priv->tx_head - priv->tx_tail) == priv->tx_max) in xcan_start_xmit_fifo()
764 spin_unlock_irqrestore(&priv->tx_lock, flags); in xcan_start_xmit_fifo()
770 * xcan_start_xmit_mailbox - Starts the transmission (mailbox mode)
774 * Return: 0 on success, -ENOSPC if there is no space
781 if (unlikely(priv->read_reg(priv, XCAN_TRR_OFFSET) & in xcan_start_xmit_mailbox()
783 return -ENOSPC; in xcan_start_xmit_mailbox()
785 spin_lock_irqsave(&priv->tx_lock, flags); in xcan_start_xmit_mailbox()
791 priv->write_reg(priv, XCAN_TRR_OFFSET, BIT(XCAN_TX_MAILBOX_IDX)); in xcan_start_xmit_mailbox()
795 spin_unlock_irqrestore(&priv->tx_lock, flags); in xcan_start_xmit_mailbox()
801 * xcan_start_xmit - Starts the transmission
817 if (priv->devtype.flags & XCAN_FLAG_TX_MAILBOXES) in xcan_start_xmit()
832 * xcan_rx - Is called from CAN isr to complete the received
845 struct net_device_stats *stats = &ndev->stats; in xcan_rx()
848 u32 id_xcan, dlc, data[2] = {0, 0}; in xcan_rx()
852 stats->rx_dropped++; in xcan_rx()
857 id_xcan = priv->read_reg(priv, XCAN_FRAME_ID_OFFSET(frame_base)); in xcan_rx()
858 dlc = priv->read_reg(priv, XCAN_FRAME_DLC_OFFSET(frame_base)) >> in xcan_rx()
862 cf->len = can_cc_dlc2len(dlc); in xcan_rx()
867 cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >> 3; in xcan_rx()
868 cf->can_id |= (id_xcan & XCAN_IDR_ID2_MASK) >> in xcan_rx()
870 cf->can_id |= CAN_EFF_FLAG; in xcan_rx()
872 cf->can_id |= CAN_RTR_FLAG; in xcan_rx()
875 cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >> in xcan_rx()
878 cf->can_id |= CAN_RTR_FLAG; in xcan_rx()
882 data[0] = priv->read_reg(priv, XCAN_FRAME_DW1_OFFSET(frame_base)); in xcan_rx()
883 data[1] = priv->read_reg(priv, XCAN_FRAME_DW2_OFFSET(frame_base)); in xcan_rx()
885 if (!(cf->can_id & CAN_RTR_FLAG)) { in xcan_rx()
887 if (cf->len > 0) in xcan_rx()
888 *(__be32 *)(cf->data) = cpu_to_be32(data[0]); in xcan_rx()
889 if (cf->len > 4) in xcan_rx()
890 *(__be32 *)(cf->data + 4) = cpu_to_be32(data[1]); in xcan_rx()
892 stats->rx_bytes += cf->len; in xcan_rx()
894 stats->rx_packets++; in xcan_rx()
902 * xcanfd_rx - Is called from CAN isr to complete the received
915 struct net_device_stats *stats = &ndev->stats; in xcanfd_rx()
918 u32 id_xcan, dlc, data[2] = {0, 0}, dwindex = 0, i, dw_offset; in xcanfd_rx()
920 id_xcan = priv->read_reg(priv, XCAN_FRAME_ID_OFFSET(frame_base)); in xcanfd_rx()
921 dlc = priv->read_reg(priv, XCAN_FRAME_DLC_OFFSET(frame_base)); in xcanfd_rx()
928 stats->rx_dropped++; in xcanfd_rx()
932 /* Change Xilinx CANFD data length format to socketCAN data in xcanfd_rx()
936 cf->len = can_fd_dlc2len((dlc & XCAN_DLCR_DLC_MASK) >> in xcanfd_rx()
939 cf->len = can_cc_dlc2len((dlc & XCAN_DLCR_DLC_MASK) >> in xcanfd_rx()
945 cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >> 3; in xcanfd_rx()
946 cf->can_id |= (id_xcan & XCAN_IDR_ID2_MASK) >> in xcanfd_rx()
948 cf->can_id |= CAN_EFF_FLAG; in xcanfd_rx()
950 cf->can_id |= CAN_RTR_FLAG; in xcanfd_rx()
953 cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >> in xcanfd_rx()
957 cf->can_id |= CAN_RTR_FLAG; in xcanfd_rx()
962 for (i = 0; i < cf->len; i += 4) { in xcanfd_rx()
965 data[0] = priv->read_reg(priv, dw_offset); in xcanfd_rx()
966 *(__be32 *)(cf->data + i) = cpu_to_be32(data[0]); in xcanfd_rx()
970 for (i = 0; i < cf->len; i += 4) { in xcanfd_rx()
972 data[0] = priv->read_reg(priv, dw_offset + i); in xcanfd_rx()
973 *(__be32 *)(cf->data + i) = cpu_to_be32(data[0]); in xcanfd_rx()
977 if (!(cf->can_id & CAN_RTR_FLAG)) in xcanfd_rx()
978 stats->rx_bytes += cf->len; in xcanfd_rx()
979 stats->rx_packets++; in xcanfd_rx()
987 * xcan_current_error_state - Get current error state from HW
1000 u32 status = priv->read_reg(priv, XCAN_SR_OFFSET); in xcan_current_error_state()
1011 * xcan_set_error_state - Set new CAN error state
1024 u32 ecr = priv->read_reg(priv, XCAN_ECR_OFFSET); in xcan_set_error_state()
1030 /* non-ERROR states are handled elsewhere */ in xcan_set_error_state()
1037 cf->can_id |= CAN_ERR_CNT; in xcan_set_error_state()
1038 cf->data[6] = txerr; in xcan_set_error_state()
1039 cf->data[7] = rxerr; in xcan_set_error_state()
1044 * xcan_update_error_state_after_rxtx - Update CAN error state after RX/TX
1047 * If the device is in a ERROR-WARNING or ERROR-PASSIVE state, check if
1054 enum can_state old_state = priv->can.state; in xcan_update_error_state_after_rxtx()
1080 * xcan_err_interrupt - error frame Isr
1091 struct net_device_stats *stats = &ndev->stats; in xcan_err_interrupt()
1095 err_status = priv->read_reg(priv, XCAN_ESR_OFFSET); in xcan_err_interrupt()
1096 priv->write_reg(priv, XCAN_ESR_OFFSET, err_status); in xcan_err_interrupt()
1099 priv->can.state = CAN_STATE_BUS_OFF; in xcan_err_interrupt()
1100 priv->can.can_stats.bus_off++; in xcan_err_interrupt()
1101 /* Leave device in Config Mode in bus-off state */ in xcan_err_interrupt()
1102 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK); in xcan_err_interrupt()
1108 if (new_state != priv->can.state) in xcan_err_interrupt()
1114 priv->can.can_stats.arbitration_lost++; in xcan_err_interrupt()
1121 stats->rx_over_errors++; in xcan_err_interrupt()
1122 stats->rx_errors++; in xcan_err_interrupt()
1129 stats->rx_dropped++; in xcan_err_interrupt()
1130 stats->rx_errors++; in xcan_err_interrupt()
1140 if (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) { in xcan_err_interrupt()
1147 stats->tx_errors++; in xcan_err_interrupt()
1156 stats->tx_errors++; in xcan_err_interrupt()
1159 cf.data[2] = CAN_ERR_PROT_BIT; in xcan_err_interrupt()
1165 stats->rx_errors++; in xcan_err_interrupt()
1168 cf.data[2] = CAN_ERR_PROT_STUFF; in xcan_err_interrupt()
1174 stats->rx_errors++; in xcan_err_interrupt()
1177 cf.data[2] = CAN_ERR_PROT_FORM; in xcan_err_interrupt()
1183 stats->rx_errors++; in xcan_err_interrupt()
1189 priv->can.can_stats.bus_error++; in xcan_err_interrupt()
1192 if (priv->ecc_enable && isr & XCAN_IXR_ECC_MASK) { in xcan_err_interrupt()
1195 reg_rx_ecc = priv->read_reg(priv, XCAN_RXFIFO_ECC_OFFSET); in xcan_err_interrupt()
1196 reg_txol_ecc = priv->read_reg(priv, XCAN_TXOLFIFO_ECC_OFFSET); in xcan_err_interrupt()
1197 reg_txtl_ecc = priv->read_reg(priv, XCAN_TXTLFIFO_ECC_OFFSET); in xcan_err_interrupt()
1202 priv->write_reg(priv, XCAN_ECC_CFG_OFFSET, XCAN_ECC_CFG_REECRX_MASK | in xcan_err_interrupt()
1205 u64_stats_update_begin(&priv->syncp); in xcan_err_interrupt()
1208 u64_stats_add(&priv->ecc_rx_2_bit_errors, in xcan_err_interrupt()
1213 u64_stats_add(&priv->ecc_rx_1_bit_errors, in xcan_err_interrupt()
1218 u64_stats_add(&priv->ecc_txol_2_bit_errors, in xcan_err_interrupt()
1223 u64_stats_add(&priv->ecc_txol_1_bit_errors, in xcan_err_interrupt()
1228 u64_stats_add(&priv->ecc_txtl_2_bit_errors, in xcan_err_interrupt()
1233 u64_stats_add(&priv->ecc_txtl_1_bit_errors, in xcan_err_interrupt()
1237 u64_stats_update_end(&priv->syncp); in xcan_err_interrupt()
1245 skb_cf->can_id |= cf.can_id; in xcan_err_interrupt()
1246 memcpy(skb_cf->data, cf.data, CAN_ERR_DLC); in xcan_err_interrupt()
1252 __func__, priv->read_reg(priv, XCAN_ESR_OFFSET)); in xcan_err_interrupt()
1256 * xcan_state_interrupt - It will check the state of the CAN device
1269 priv->can.state = CAN_STATE_SLEEPING; in xcan_state_interrupt()
1273 priv->can.state = CAN_STATE_ERROR_ACTIVE; in xcan_state_interrupt()
1277 * xcan_rx_fifo_get_next_frame - Get register offset of next RX frame
1286 if (priv->devtype.flags & XCAN_FLAG_RX_FIFO_MULTI) { in xcan_rx_fifo_get_next_frame()
1289 /* clear RXOK before the is-empty check so that any newly in xcan_rx_fifo_get_next_frame()
1292 priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_RXOK_MASK); in xcan_rx_fifo_get_next_frame()
1294 fsr = priv->read_reg(priv, XCAN_FSR_OFFSET); in xcan_rx_fifo_get_next_frame()
1297 if (priv->devtype.flags & XCAN_FLAG_CANFD_2) in xcan_rx_fifo_get_next_frame()
1303 return -ENOENT; in xcan_rx_fifo_get_next_frame()
1305 if (priv->devtype.flags & XCAN_FLAG_CANFD_2) in xcan_rx_fifo_get_next_frame()
1314 if (!(priv->read_reg(priv, XCAN_ISR_OFFSET) & in xcan_rx_fifo_get_next_frame()
1316 return -ENOENT; in xcan_rx_fifo_get_next_frame()
1326 * xcan_rx_poll - Poll routine for rx packets (NAPI)
1337 struct net_device *ndev = napi->dev; in xcan_rx_poll()
1350 if (priv->devtype.flags & XCAN_FLAG_RX_FIFO_MULTI) in xcan_rx_poll()
1352 priv->write_reg(priv, XCAN_FSR_OFFSET, in xcan_rx_poll()
1355 /* clear rx-not-empty (will actually clear only if in xcan_rx_poll()
1358 priv->write_reg(priv, XCAN_ICR_OFFSET, in xcan_rx_poll()
1367 ier = priv->read_reg(priv, XCAN_IER_OFFSET); in xcan_rx_poll()
1369 priv->write_reg(priv, XCAN_IER_OFFSET, ier); in xcan_rx_poll()
1376 * xcan_tx_interrupt - Tx Done Isr
1383 struct net_device_stats *stats = &ndev->stats; in xcan_tx_interrupt()
1395 spin_lock_irqsave(&priv->tx_lock, flags); in xcan_tx_interrupt()
1397 frames_in_fifo = priv->tx_head - priv->tx_tail; in xcan_tx_interrupt()
1401 priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_TXOK_MASK); in xcan_tx_interrupt()
1402 spin_unlock_irqrestore(&priv->tx_lock, flags); in xcan_tx_interrupt()
1406 /* Check if 2 frames were sent (TXOK only means that at least 1 in xcan_tx_interrupt()
1410 WARN_ON(frames_in_fifo > priv->tx_max); in xcan_tx_interrupt()
1413 * (1) isr variable is up-to-date at least up to TXOK clear in xcan_tx_interrupt()
1417 * (2) No TXOK is left. Having one could mean leaving a in xcan_tx_interrupt()
1424 priv->write_reg(priv, XCAN_ICR_OFFSET, in xcan_tx_interrupt()
1426 isr = priv->read_reg(priv, XCAN_ISR_OFFSET); in xcan_tx_interrupt()
1435 priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_TXOK_MASK); in xcan_tx_interrupt()
1438 while (frames_sent--) { in xcan_tx_interrupt()
1439 stats->tx_bytes += can_get_echo_skb(ndev, priv->tx_tail % in xcan_tx_interrupt()
1440 priv->tx_max, NULL); in xcan_tx_interrupt()
1441 priv->tx_tail++; in xcan_tx_interrupt()
1442 stats->tx_packets++; in xcan_tx_interrupt()
1447 spin_unlock_irqrestore(&priv->tx_lock, flags); in xcan_tx_interrupt()
1453 * xcan_interrupt - CAN Isr
1461 * IRQ_NONE - If CAN device is in sleep mode, IRQ_HANDLED otherwise
1472 isr = priv->read_reg(priv, XCAN_ISR_OFFSET); in xcan_interrupt()
1478 priv->write_reg(priv, XCAN_ICR_OFFSET, (XCAN_IXR_SLP_MASK | in xcan_interrupt()
1491 if (priv->ecc_enable) in xcan_interrupt()
1497 priv->write_reg(priv, XCAN_ICR_OFFSET, isr_errors); in xcan_interrupt()
1503 ier = priv->read_reg(priv, XCAN_IER_OFFSET); in xcan_interrupt()
1505 priv->write_reg(priv, XCAN_IER_OFFSET, ier); in xcan_interrupt()
1506 napi_schedule(&priv->napi); in xcan_interrupt()
1512 * xcan_chip_stop - Driver stop routine
1528 priv->can.state = CAN_STATE_STOPPED; in xcan_chip_stop()
1532 * xcan_open - Driver open routine
1543 ret = phy_power_on(priv->transceiver); in xcan_open()
1547 ret = pm_runtime_get_sync(priv->dev); in xcan_open()
1554 ret = request_irq(ndev->irq, xcan_interrupt, priv->irq_flags, in xcan_open()
1555 ndev->name, ndev); in xcan_open()
1579 napi_enable(&priv->napi); in xcan_open()
1587 free_irq(ndev->irq, ndev); in xcan_open()
1589 pm_runtime_put(priv->dev); in xcan_open()
1590 phy_power_off(priv->transceiver); in xcan_open()
1596 * xcan_close - Driver close routine
1606 napi_disable(&priv->napi); in xcan_close()
1608 free_irq(ndev->irq, ndev); in xcan_close()
1611 pm_runtime_put(priv->dev); in xcan_close()
1612 phy_power_off(priv->transceiver); in xcan_close()
1618 * xcan_get_berr_counter - error counter routine
1631 ret = pm_runtime_get_sync(priv->dev); in xcan_get_berr_counter()
1635 pm_runtime_put(priv->dev); in xcan_get_berr_counter()
1639 bec->txerr = priv->read_reg(priv, XCAN_ECR_OFFSET) & XCAN_ECR_TEC_MASK; in xcan_get_berr_counter()
1640 bec->rxerr = ((priv->read_reg(priv, XCAN_ECR_OFFSET) & in xcan_get_berr_counter()
1643 pm_runtime_put(priv->dev); in xcan_get_berr_counter()
1649 * xcan_get_auto_tdcv - Get Transmitter Delay Compensation Value
1659 *tdcv = FIELD_GET(XCAN_SR_TDCV_MASK, priv->read_reg(priv, XCAN_SR_OFFSET)); in xcan_get_auto_tdcv()
1679 return -EOPNOTSUPP; in xcan_get_sset_count()
1690 start = u64_stats_fetch_begin(&priv->syncp); in xcan_get_ethtool_stats()
1692 data[XCAN_ECC_RX_2_BIT_ERRORS] = u64_stats_read(&priv->ecc_rx_2_bit_errors); in xcan_get_ethtool_stats()
1693 data[XCAN_ECC_RX_1_BIT_ERRORS] = u64_stats_read(&priv->ecc_rx_1_bit_errors); in xcan_get_ethtool_stats()
1694 data[XCAN_ECC_TXOL_2_BIT_ERRORS] = u64_stats_read(&priv->ecc_txol_2_bit_errors); in xcan_get_ethtool_stats()
1695 data[XCAN_ECC_TXOL_1_BIT_ERRORS] = u64_stats_read(&priv->ecc_txol_1_bit_errors); in xcan_get_ethtool_stats()
1696 data[XCAN_ECC_TXTL_2_BIT_ERRORS] = u64_stats_read(&priv->ecc_txtl_2_bit_errors); in xcan_get_ethtool_stats()
1697 data[XCAN_ECC_TXTL_1_BIT_ERRORS] = u64_stats_read(&priv->ecc_txtl_1_bit_errors); in xcan_get_ethtool_stats()
1698 } while (u64_stats_fetch_retry(&priv->syncp, start)); in xcan_get_ethtool_stats()
1716 * xcan_suspend - Suspend method for the driver
1736 * xcan_resume - Resume from suspend
1768 * xcan_runtime_suspend - Runtime suspend method for the driver
1779 clk_disable_unprepare(priv->bus_clk); in xcan_runtime_suspend()
1780 clk_disable_unprepare(priv->can_clk); in xcan_runtime_suspend()
1786 * xcan_runtime_resume - Runtime resume from suspend
1798 ret = clk_prepare_enable(priv->bus_clk); in xcan_runtime_resume()
1803 ret = clk_prepare_enable(priv->can_clk); in xcan_runtime_resume()
1806 clk_disable_unprepare(priv->bus_clk); in xcan_runtime_resume()
1862 { .compatible = "xlnx,zynq-can-1.0", .data = &xcan_zynq_data },
1863 { .compatible = "xlnx,axi-can-1.00.a", .data = &xcan_axi_data },
1864 { .compatible = "xlnx,canfd-1.0", .data = &xcan_canfd_data },
1865 { .compatible = "xlnx,canfd-2.0", .data = &xcan_canfd2_data },
1871 * xcan_probe - Platform registration call
1898 devtype = device_get_match_data(&pdev->dev); in xcan_probe()
1900 hw_tx_max_property = devtype->flags & XCAN_FLAG_TX_MAILBOXES ? in xcan_probe()
1901 "tx-mailbox-count" : "tx-fifo-depth"; in xcan_probe()
1903 ret = of_property_read_u32(pdev->dev.of_node, hw_tx_max_property, in xcan_probe()
1906 dev_err(&pdev->dev, "missing %s property\n", in xcan_probe()
1911 ret = of_property_read_u32(pdev->dev.of_node, "rx-fifo-depth", in xcan_probe()
1914 dev_err(&pdev->dev, in xcan_probe()
1915 "missing rx-fifo-depth property (mailbox mode is not supported)\n"); in xcan_probe()
1923 * is supported, we can have 2 frames in the FIFO and use TXFEMP in xcan_probe()
1924 * to determine if 1 or 2 frames have been sent. in xcan_probe()
1927 * FIFO, with watermark at 2 frames, it can happen that TXFWMEMP (less in xcan_probe()
1928 * than 2 frames in FIFO) is set anyway with no TXOK (a frame was in xcan_probe()
1929 * sent), which is not a sensible state - possibly TXFWMEMP is not in xcan_probe()
1937 if (!(devtype->flags & XCAN_FLAG_TX_MAILBOXES) && in xcan_probe()
1938 (devtype->flags & XCAN_FLAG_TXFEMP)) in xcan_probe()
1939 tx_max = min(hw_tx_max, 2U); in xcan_probe()
1948 return -ENOMEM; in xcan_probe()
1951 priv->ecc_enable = of_property_read_bool(pdev->dev.of_node, "xlnx,has-ecc"); in xcan_probe()
1952 priv->dev = &pdev->dev; in xcan_probe()
1953 priv->can.bittiming_const = devtype->bittiming_const; in xcan_probe()
1954 priv->can.do_set_mode = xcan_do_set_mode; in xcan_probe()
1955 priv->can.do_get_berr_counter = xcan_get_berr_counter; in xcan_probe()
1956 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | in xcan_probe()
1958 priv->rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); in xcan_probe()
1959 if (IS_ERR(priv->rstc)) { in xcan_probe()
1960 dev_err(&pdev->dev, "Cannot get CAN reset.\n"); in xcan_probe()
1961 ret = PTR_ERR(priv->rstc); in xcan_probe()
1965 ret = reset_control_reset(priv->rstc); in xcan_probe()
1969 if (devtype->cantype == XAXI_CANFD) { in xcan_probe()
1970 priv->can.data_bittiming_const = in xcan_probe()
1972 priv->can.tdc_const = &xcan_tdc_const_canfd; in xcan_probe()
1975 if (devtype->cantype == XAXI_CANFD_2_0) { in xcan_probe()
1976 priv->can.data_bittiming_const = in xcan_probe()
1978 priv->can.tdc_const = &xcan_tdc_const_canfd2; in xcan_probe()
1981 if (devtype->cantype == XAXI_CANFD || in xcan_probe()
1982 devtype->cantype == XAXI_CANFD_2_0) { in xcan_probe()
1983 priv->can.ctrlmode_supported |= CAN_CTRLMODE_FD | in xcan_probe()
1985 priv->can.do_get_auto_tdcv = xcan_get_auto_tdcv; in xcan_probe()
1988 priv->reg_base = addr; in xcan_probe()
1989 priv->tx_max = tx_max; in xcan_probe()
1990 priv->devtype = *devtype; in xcan_probe()
1991 spin_lock_init(&priv->tx_lock); in xcan_probe()
1998 ndev->irq = ret; in xcan_probe()
2000 ndev->flags |= IFF_ECHO; /* We support local echo */ in xcan_probe()
2003 SET_NETDEV_DEV(ndev, &pdev->dev); in xcan_probe()
2004 ndev->netdev_ops = &xcan_netdev_ops; in xcan_probe()
2005 ndev->ethtool_ops = &xcan_ethtool_ops; in xcan_probe()
2008 priv->can_clk = devm_clk_get(&pdev->dev, "can_clk"); in xcan_probe()
2009 if (IS_ERR(priv->can_clk)) { in xcan_probe()
2010 ret = dev_err_probe(&pdev->dev, PTR_ERR(priv->can_clk), in xcan_probe()
2015 priv->bus_clk = devm_clk_get(&pdev->dev, devtype->bus_clk_name); in xcan_probe()
2016 if (IS_ERR(priv->bus_clk)) { in xcan_probe()
2017 ret = dev_err_probe(&pdev->dev, PTR_ERR(priv->bus_clk), in xcan_probe()
2022 transceiver = devm_phy_optional_get(&pdev->dev, NULL); in xcan_probe()
2025 dev_err_probe(&pdev->dev, ret, "failed to get phy\n"); in xcan_probe()
2028 priv->transceiver = transceiver; in xcan_probe()
2030 priv->write_reg = xcan_write_reg_le; in xcan_probe()
2031 priv->read_reg = xcan_read_reg_le; in xcan_probe()
2033 pm_runtime_enable(&pdev->dev); in xcan_probe()
2034 ret = pm_runtime_get_sync(&pdev->dev); in xcan_probe()
2041 if (priv->read_reg(priv, XCAN_SR_OFFSET) != XCAN_SR_CONFIG_MASK) { in xcan_probe()
2042 priv->write_reg = xcan_write_reg_be; in xcan_probe()
2043 priv->read_reg = xcan_read_reg_be; in xcan_probe()
2046 priv->can.clock.freq = clk_get_rate(priv->can_clk); in xcan_probe()
2048 netif_napi_add_weight(ndev, &priv->napi, xcan_rx_poll, rx_max); in xcan_probe()
2052 dev_err(&pdev->dev, "fail to register failed (err=%d)\n", ret); in xcan_probe()
2057 pm_runtime_put(&pdev->dev); in xcan_probe()
2059 if (priv->devtype.flags & XCAN_FLAG_CANFD_2) { in xcan_probe()
2060 priv->write_reg(priv, XCAN_AFR_2_ID_OFFSET, 0x00000000); in xcan_probe()
2061 priv->write_reg(priv, XCAN_AFR_2_MASK_OFFSET, 0x00000000); in xcan_probe()
2065 priv->reg_base, ndev->irq, priv->can.clock.freq, in xcan_probe()
2066 hw_tx_max, priv->tx_max); in xcan_probe()
2068 if (priv->ecc_enable) { in xcan_probe()
2070 priv->write_reg(priv, XCAN_ECC_CFG_OFFSET, XCAN_ECC_CFG_REECRX_MASK | in xcan_probe()
2076 pm_runtime_put(priv->dev); in xcan_probe()
2077 pm_runtime_disable(&pdev->dev); in xcan_probe()
2079 reset_control_assert(priv->rstc); in xcan_probe()
2087 * xcan_remove - Unregister the device after releasing the resources
2099 pm_runtime_disable(&pdev->dev); in xcan_remove()
2100 reset_control_assert(priv->rstc); in xcan_remove()