| /freebsd/sys/contrib/device-tree/Bindings/dma/ |
| H A D | qcom_hidma_mgmt.txt | 14 instance can use like maximum read/write request and number of bytes to
15 read/write in a single burst.
18 - compatible: "qcom,hidma-mgmt-1.0";
19 - reg: Address range for DMA device
20 - dma-channels: Number of channels supported by this DMA controller.
21 - max-write-burst-bytes: Maximum write burst in bytes that HIDMA can
26 - max-read-burst-bytes: Maximum read burst in bytes that HIDMA can
31 - max-write-transactions: This value is how many times a write burst is
34 - max-read-transactions: This value is how many times a read burst is
36 - channel-reset-timeout-cycles: Channel reset timeout in cycles for this SOC.
[all …]
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| H A D | renesas,nbpfaxi.txt | 1 * Renesas "Type-AXI" NBPFAXI* DMA controllers
7 - compatible: must be one of
17 - #dma-cells: must be 2: the first integer is a terminal number, to which this
26 - max-burst-mem-read: limit burst size for memory reads
28 than using the maximum burst size allowed by the hardware's buffer size.
29 - max-burst-mem-write: limit burst size for memory writes
31 than using the maximum burst size allowed by the hardware's buffer size.
32 If both max-burst-mem-read and max-burst-mem-write are set, DMA_MEM_TO_MEM
35 You can use dma-channels and dma-requests as described in dma.txt, although they
40 dma: dma-controller@48000000 {
[all …]
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| H A D | intel,ldma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - chuanhua.lei@intel.com
11 - mallikarjunax.reddy@intel.com
14 - $ref: dma-controller.yaml#
19 - intel,lgm-cdma
20 - intel,lgm-dma2tx
21 - intel,lgm-dma1rx
22 - intel,lgm-dma1tx
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| /freebsd/sys/contrib/device-tree/Bindings/memory-controllers/ |
| H A D | ti,gpmc-child.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ti,gpmc-child.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
11 - Roger Quadros <rogerq@kernel.org>
24 gpmc,sync-clk-ps:
28 # Chip-select signal timings corresponding to GPMC_CONFIG2:
29 gpmc,cs-on-ns:
33 gpmc,cs-rd-off-ns:
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| H A D | omap-gpmc.txt | 7 - compatible: Should be set to one of the following:
9 ti,omap2420-gpmc (omap2420)
10 ti,omap2430-gpmc (omap2430)
11 ti,omap3430-gpmc (omap3430 & omap3630)
12 ti,omap4430-gpmc (omap4430 & omap4460 & omap543x)
13 ti,am3352-gpmc (am335x devices)
15 - reg: A resource specifier for the register space
17 - ti,hwmods: Should be set to "ti,gpmc" until the DT transition is
19 - #address-cells: Must be set to 2 to allow memory address translation
20 - #size-cells: Must be set to 1 to allow CS address passing
[all …]
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| H A D | st,stm32-fmc2-ebi-props.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christophe Kerello <christophe.kerello@foss.st.com>
11 - Marek Vasut <marex@denx.de>
14 st,fmc2-ebi-cs-transaction-type:
25 8: Synchronous read synchronous write PSRAM.
26 9: Synchronous read asynchronous write PSRAM.
27 10: Synchronous read synchronous write NOR.
[all …]
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| H A D | mvebu-devbus.txt | 9 - compatible: Armada 370/XP SoC are supported using the
10 "marvell,mvebu-devbus" compatible string.
13 "marvell,orion-devbus" compatible string.
15 - reg: A resource specifier for the register space.
20 - #address-cells: Must be set to 1
21 - #size-cells: Must be set to 1
22 - ranges: Must be set up to reflect the memory layout with four
23 integer values for each chip-select line in use:
28 - devbus,keep-config This property can optionally be used to keep
35 Read parameters:
[all …]
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| /freebsd/sys/contrib/alpine-hal/ |
| H A D | al_hal_udma_regs_m2s.h | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
63 /* [0x8] Data read master configuration */
65 /* [0xc] Data read master configuration */
67 /* [0x10] Descriptor read master configuration */
69 /* [0x14] Descriptor read master configuration */
71 /* [0x18] Data read master configuration */
73 /* [0x1c] Descriptors read master configuration */
84 * 00 - No pending tasks
98 * 0 - Log is enabled.
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| H A D | al_hal_udma_regs_s2m.h | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
63 /* [0x8] Descriptor read master configuration */
65 /* [0xc] Descriptor read master configuration */
73 /* [0x1c] Descriptors read master configuration */
77 /* [0x24] AXI outstanding read configuration */
86 * 00 - No pending tasks
100 * 0 - Log is enable
101 * 1 - Log is masked.
190 * [0x8] Counting the net length of the data buffers [64-bit]
[all …]
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| H A D | al_hal_udma_config.h | 9 found at http://www.gnu.org/licenses/gpl-2.0.html
53 /* *INDENT-OFF* */
57 /* *INDENT-ON* */
81 uint8_t burst; member
94 al_bool break_on_max_boundary; /* Data read break on max boundary */
95 uint8_t min_axi_beats; /* Minimum burst for writing completion desc. */
107 al_bool break_on_max_boundary; /* Data read break on max boundary */
108 uint8_t min_axi_beats; /* Minimum burst for writing completion desc. */
137 /* in one burst (5b) */
139 uint8_t min_burst_above_thr; /* min burst size when fifo above
[all …]
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| /freebsd/sys/contrib/device-tree/src/arm/ti/omap/ |
| H A D | omap2420-n8x0-common.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
11 stdout-path = &uart3;
16 compatible = "i2c-cbus-gpio";
21 #address-cells = <1>;
22 #size-cells = <0>;
25 interrupt-parent = <&gpio4>;
34 clock-frequency = <400000>;
44 clock-frequency = <400000>;
50 /* gpio-irq for dma: 26 */
53 #address-cells = <1>;
[all …]
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| H A D | omap3-gta04a5one.dts | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014-18 H. Nikolaus Schaller <hns@goldelico.com>
6 #include "omap3-gta04a5.dts"
13 gpmc_pins: gpmc-pins {
14 pinctrl-single,pins = <
45 pinctrl-names = "default";
46 pinctrl-0 = <&gpmc_pins>;
48 /delete-node/ nand@0,0;
52 #address-cells = <1>;
53 #size-cells = <1>;
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| H A D | omap3-igep.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
8 /dts-v1/;
19 stdout-path = &uart3;
23 compatible = "ti,omap-twl4030";
28 vdd33: regulator-vdd33 {
29 compatible = "regulator-fixed";
30 regulator-name = "vdd33";
31 regulator-always-on;
37 gpmc_pins: gpmc-pins {
38 pinctrl-single,pins = <
[all …]
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| H A D | omap3-n950-n9.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * omap3-n950-n9.dtsi - Device Tree file for Nokia N950 & N9 (common stuff)
13 cpu0-supply = <&vcc>;
23 compatible = "regulator-fixed";
24 regulator-name = "VEMMC";
25 regulator-min-microvolt = <2900000>;
26 regulator-max-microvolt = <2900000>;
28 startup-delay-us = <150>;
29 enable-active-high;
33 compatible = "regulator-fixed";
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | snps,dwc-qos-ethernet.txt | 13 - compatible: One of:
14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
15 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
16 - "nvidia,tegra186-eqos", "snps,dwc-qo
[all...] |
| H A D | snps,dwmac.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Torgue <alexandre.torgue@foss.st.com>
11 - Giuseppe Cavallaro <peppe.cavallaro@st.com>
12 - Jos
[all...] |
| /freebsd/share/man/man4/ |
| H A D | sctp.4 | 47 protocol provides reliable, flow-controlled, two-way
57 Internet address format and, in addition, provides a per-host
105 third leg of the four-way handshake.
116 protocol directly supports multi-homing.
129 transport protocol is also multi-streamed.
130 Multi-streaming refers to the ability to send sub-ordered flows of
159 .Bl -tag -width "sctp partial reliability"
172 so that two stacks can pre-share keys.
190 .Bl -tag -width indent
217 For the one-to-many model
[all …]
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| /freebsd/lib/libpmc/pmu-events/arch/x86/bonnell/ |
| H A D | other.json | 107 "BriefDescription": "Outstanding cacheable data read bus requests duration.",
115 "BriefDescription": "Outstanding cacheable data read bus requests duration.",
139 "BriefDescription": "Burst read bus transactions.",
147 "BriefDescription": "Burst read bus transactions.",
155 "BriefDescription": "Burst (full cache-line) bus transactions.",
163 "BriefDescription": "Burst (full cache-line) bus transactions.",
187 "BriefDescription": "Instruction-fetch bus transactions.",
195 "BriefDescription": "Instruction-fetch bus transactions.",
331 "BriefDescription": "Memory cluster signals to block micro-op dispatch for any reason",
|
| /freebsd/sys/contrib/device-tree/Bindings/bus/ |
| H A D | qcom,ebi2.txt | 4 external memory (such as NAND or other memory-mapped peripherals) whereas
18 Also CS1 and CS2 has -A and -B signals. Why they have that is unclear to me.
24 CS0 GPIO134 0x1a800000-0x1b000000 (8MB)
25 CS1 GPIO39 (A) / GPIO123 (B) 0x1b000000-0x1b800000 (8MB)
26 CS2 GPIO40 (A) / GPIO124 (B) 0x1b800000-0x1c000000 (8MB)
27 CS3 GPIO133 0x1d000000-0x25000000 (128 MB)
28 CS4 GPIO132 0x1c800000-0x1d000000 (8MB)
29 CS5 GPIO131 0x1c000000-0x1c800000 (8MB)
31 The APQ8060 Qualcomm Application Processor User Guide, 80-N7150-14 Rev. A,
51 - compatible: should be one of:
[all …]
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| /freebsd/sys/dev/tpm/ |
| H A D | tpm.c | 3 * Copyright (c) 2009, 2010 Hans-Joerg Hoexer
49 #define IRQUNK -1
83 #define TPM_INTF_INT_LEVEL_LOW 0x0010 /* level-low ints supported */
84 #define TPM_INTF_INT_LEVEL_HIGH 0x0008 /* level-high ints supported */
85 #define TPM_INTF_LOCALITY_CHANGE_INT 0x0004 /* locality-change int (mb 1) */
95 #define TPM_STS_BMASK 0x00ffff00 /* ro io burst size */
128 ((struct tpm_softc *)dev->si_drv1)
206 sc->mem_rid = 0; in tpm_attach()
207 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, in tpm_attach()
209 if (sc->mem_res == NULL) in tpm_attach()
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| /freebsd/sys/dev/mlx5/mlx5_en/ |
| H A D | mlx5_en_rl.c | 1 /*-
2 * Copyright (c) 2016-2020 Mellanox Technologies. All rights reserved.
57 void *sqc = param->sqc; in mlx5e_rl_build_sq_param()
59 uint8_t log_sq_size = order_base_2(rl->param.tx_queue_size); in mlx5e_rl_build_sq_param()
63 MLX5_SET(wq, wq, pd, rl->priv->pdn); in mlx5e_rl_build_sq_param()
65 param->wq.linear = 1; in mlx5e_rl_build_sq_param()
72 void *cqc = param->cqc; in mlx5e_rl_build_cq_param()
73 uint8_t log_sq_size = order_base_2(rl->param.tx_queue_size); in mlx5e_rl_build_cq_param()
76 MLX5_SET(cqc, cqc, cq_period, rl->param.tx_coalesce_usecs); in mlx5e_rl_build_cq_param()
77 MLX5_SET(cqc, cqc, cq_max_count, rl->param.tx_coalesce_pkts); in mlx5e_rl_build_cq_param()
[all …]
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| /freebsd/tools/tools/netmap/ |
| H A D | nmreplay.c | 49 * --- Main functions of the program ---
59 * q->cur_pkt points to the buffer containing the packet
60 * q->cur_len packet length, excluding CRC
61 * q->cur_caplen available packet length (may be shorter than cur_len)
62 * q->cur_tt transmission time for the packet, computed from the trace.
66 * q->c_loss (set with the -L command line option) decides
69 * The function is supposed to set q->c_drop = 1 if the
72 * q->c_bw (set with the -B command line option) is used to
74 * in q->cur_tt the transmission time (in nanoseconds) of
76 * of the packet, i.e. q->cur_tt = q->cur_len / <bandwidth>
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| /freebsd/contrib/ntp/ntpd/ |
| H A D | refclock_chu.c | 2 * refclock_chu - clock driver for Canadian CHU time/frequency station
44 * kHz and mu-law companding. This is the same standard as used by the
57 * maximum-likelihood technique which exploits the considerable degree
62 * consists of nine, ten-character bursts transmitted at 300 bps between
65 * digits. The burst data consist of five characters (ten hex digits)
79 * burst synchronization. These digits are then repeated with the same
87 * the DUT1 (d in deciseconds), Gregorian year (yyyy), difference TAI -
98 * By design, the last stop bit of the last character in the burst
101 * coincides with 0.5 - 9 * 11/300 = 0.170 second. Depending on the
110 * connections. With debugging enabled (-d on the ntpd command line),
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| /freebsd/sys/dev/ichiic/ |
| H A D | ig4_iic.c | 75 #define DO_POLL(sc) (cold || kdb_active || SCHEDULER_STOPPED() || sc->poll)
147 * 0 - Try read clock registers from ACPI and fallback to p.1.
148 * 1 - Calculate values based on controller type (IC clock rate).
149 * 2 - Use values inherited from DragonflyBSD driver (old behavior).
150 * 3 - Keep clock registers intact.
157 * Low-level inline support functions
162 bus_write_4(sc->regs_res, reg, value); in reg_write()
163 bus_barrier(sc->regs_res, reg, 4, BUS_SPACE_BARRIER_WRITE); in reg_write()
171 bus_barrier(sc->regs_re in reg_read()
434 int burst, target, lowat = 0; ig4iic_read() local
496 int burst, target; ig4iic_write() local
[all...] |
| /freebsd/sys/dev/igc/ |
| H A D | igc_i225.c | 1 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
22 * igc_init_nvm_params_i225 - Init NVM func ptrs.
27 struct igc_nvm_info *nvm = &hw->nvm; in igc_init_nvm_params_i225()
36 * Added to a constant, "size" becomes the left-shift value in igc_init_nvm_params_i225()
47 nvm->word_size = 1 << size; in igc_init_nvm_params_i225()
48 nvm->opcode_bits = 8; in igc_init_nvm_params_i225()
49 nvm->delay_usec = 1; in igc_init_nvm_params_i225()
50 nvm->type = igc_nvm_eeprom_spi; in igc_init_nvm_params_i225()
53 nvm->page_size = eecd & IGC_EECD_ADDR_BITS ? 32 : 8; in igc_init_nvm_params_i225()
[all …]
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