Lines Matching +full:burst +full:- +full:read
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - chuanhua.lei@intel.com
11 - mallikarjunax.reddy@intel.com
14 - $ref: dma-controller.yaml#
19 - intel,lgm-cdma
20 - intel,lgm-dma2tx
21 - intel,lgm-dma1rx
22 - intel,lgm-dma1tx
23 - intel,lgm-dma0tx
24 - intel,lgm-dma3
25 - intel,lgm-toe-dma30
26 - intel,lgm-toe-dma31
31 "#dma-cells":
36 The third cell is the burst length of the channel.
38 dma-channels:
42 dma-channel-mask:
51 reset-names:
53 - const: ctrl
58 intel,dma-poll-cnt:
64 intel,dma-byte-en:
69 instead of the whole burst.
71 intel,dma-drb:
74 DMA descriptor read back to make sure data and desc synchronization.
76 intel,dma-dburst-wr:
79 Enable RX dynamic burst write. When it is enabled, the DMA does RX dynamic burst;
80 if it is disabled, the DMA RX will still support programmable fixed burst size of 2,4,8,16.
84 - compatible
85 - reg
90 - |
91 dma0: dma-controller@e0e00000 {
92 compatible = "intel,lgm-cdma";
94 #dma-cells = <3>;
95 dma-channels = <16>;
96 dma-channel-mask = <0xFFFF>;
97 interrupt-parent = <&ioapic1>;
100 reset-names = "ctrl";
102 intel,dma-poll-cnt = <4>;
103 intel,dma-byte-en;
104 intel,dma-drb;
106 - |
107 dma3: dma-controller@ec800000 {
108 compatible = "intel,lgm-dma3";
112 #dma-cells = <3>;
113 intel,dma-poll-cnt = <16>;
114 intel,dma-byte-en;
115 intel,dma-dburst-wr;