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/linux/arch/nios2/include/asm/
H A Dasm-macros.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Macro used to simplify coding multi-line assembler.
4 * Some of the bit test macro can simplify down to one line
5 * depending on the mask value.
14 * ANDs reg2 with mask and places the result in reg1.
19 .macro ANDI32 reg1, reg2, mask
20 .if \mask & 0xffff
21 .if \mask & 0xffff0000
22 movhi \reg1, %hi(\mask)
23 movui \reg1, %lo(\mask)
[all …]
/linux/drivers/platform/x86/
H A Dmlx-platform.c1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
5 * Copyright (C) 2016-2018 Mellanox Technologies
6 * Copyright (C) 2016-2018 Vadim Pasternak <vadimp@mellanox.com>
12 #include <linux/i2c-mux.h>
17 #include <linux/platform_data/i2c-mux-reg.h>
211 #define MLXPLAT_CPLD_AGGR_MASK_COMEX BIT(0)
212 #define MLXPLAT_CPLD_AGGR_MASK_LC BIT(3)
216 #define MLXPLAT_CPLD_AGGR_MASK_LC_PRSNT BIT(0)
217 #define MLXPLAT_CPLD_AGGR_MASK_LC_RDY BIT(1)
218 #define MLXPLAT_CPLD_AGGR_MASK_LC_PG BIT(2)
[all …]
/linux/arch/powerpc/sysdev/
H A Dipic.c1 // SPDX-License-Identifier: GPL-2.0-or-later
35 .mask = IPIC_SIMSR_H,
38 .bit = 16,
42 .mask = IPIC_SIMSR_H,
45 .bit = 17,
49 .mask = IPIC_SIMSR_H,
52 .bit = 18,
56 .mask = IPIC_SIMSR_H,
59 .bit = 19,
63 .mask = IPIC_SIMSR_H,
[all …]
/linux/arch/mips/lib/
H A Dbitops.c6 * Copyright (c) 1994-1997, 99, 2000, 06, 07 Ralf Baechle (ralf@linux-mips.org)
16 * __mips_set_bit - Atomically set a bit in memory. This is called by
18 * @nr: the bit to set
24 unsigned int bit = nr % BITS_PER_LONG; in __mips_set_bit() local
25 unsigned long mask; in __mips_set_bit() local
28 mask = 1UL << bit; in __mips_set_bit()
30 *a |= mask; in __mips_set_bit()
37 * __mips_clear_bit - Clears a bit in memory. This is called by clear_bit() if
39 * @nr: Bit to clear
45 unsigned int bit = nr % BITS_PER_LONG; in __mips_clear_bit() local
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/linux/drivers/iio/imu/st_lsm6dsx/
H A Dst_lsm6dsx_core.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * and 3D digital gyroscope system-in-package with a digital I2C/SPI serial
8 * LSM6DSx IMU MEMS series has a dynamic user-selectable full-scale
9 * acceleration range of +-2/+-4/+-8/+-16 g and an angular rate range of
10 * +-125/+-245/+-500/+-1000/+-2000 dps
11 * LSM6DSx series has an integrated First-In-First-Out (FIFO) buffer
18 * - LSM6DS3
19 * - Accelerometer/Gyroscope supported ODR [Hz]: 12.5, 26, 52, 104, 208, 416
20 * - Accelerometer supported full-scale [g]: +-2/+-4/+-8/+-16
21 * - Gyroscope supported full-scale [dps]: +-125/+-245/+-500/+-1000/+-2000
[all …]
/linux/arch/s390/include/asm/
H A Dbitops.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 * big-endian system because, unlike little endian, the number of each
13 * bit depends on the word size.
23 * The main difference is that bit 0-63 in the bit number field needs to be
24 * reversed compared to the LSB0 encoded bit fields. This can be achieved by
42 #define __BITOPS_WORDS(bits) (((bits) + BITS_PER_LONG - 1) / BITS_PER_LONG)
49 addr = (unsigned long)ptr + ((nr ^ (nr & (BITS_PER_LONG - 1))) >> 3); in __bitops_word()
55 return 1UL << (nr & (BITS_PER_LONG - 1)); in __bitops_mask()
61 unsigned long mask = __bitops_mask(nr); in arch_set_bit() local
63 __atomic64_or(mask, (long *)addr); in arch_set_bit()
[all …]
/linux/drivers/crypto/intel/qat/qat_common/
H A Dadf_gen4_ras.h1 /* SPDX-License-Identifier: GPL-2.0-only */
10 /* ERRSOU0 Correctable error mask*/
11 #define ADF_GEN4_ERRSOU0_BIT BIT(0)
18 #define ADF_GEN4_ERRSOU1_HIAEUNCERRLOG_CPP0_BIT BIT(0)
19 #define ADF_GEN4_ERRSOU1_HICPPAGENTCMDPARERRLOG_BIT BIT(1)
20 #define ADF_GEN4_ERRSOU1_RIMEM_PARERR_STS_BIT BIT(2)
21 #define ADF_GEN4_ERRSOU1_TIMEM_PARERR_STS_BIT BIT(3)
22 #define ADF_GEN4_ERRSOU1_RIMISCSTS_BIT BIT(4)
50 * RI Memory parity error mask
51 * BIT(0) - BIT(3) - ri_iosf_pdata_rxq[0:3] parity error
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/linux/drivers/memory/tegra/
H A Dtegra210.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <dt-bindings/memory/tegra210-mc.h>
22 .bit = 1,
27 .mask = 0xff,
38 .bit = 2,
43 .mask = 0xff,
54 .bit = 3,
59 .mask = 0xff,
70 .bit = 4,
75 .mask = 0xff,
[all …]
H A Dtegra114.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/memory/tegra114-mc.h>
22 .mask = 0xff,
33 .bit = 1,
38 .mask = 0xff,
49 .bit = 2,
54 .mask = 0xff,
65 .bit = 3,
70 .mask = 0xff,
81 .bit = 4,
[all …]
H A Dtegra124.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <dt-bindings/memory/tegra124-mc.h>
23 .mask = 0xff,
34 .bit = 1,
39 .mask = 0xff,
50 .bit = 2,
55 .mask = 0xff,
66 .bit = 3,
71 .mask = 0xff,
82 .bit = 4,
[all …]
H A Dtegra30.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <dt-bindings/memory/tegra30-mc.h>
44 .mask = 0xff,
56 .bit = 1,
61 .mask = 0xff,
73 .bit = 2,
78 .mask = 0xff,
90 .bit = 3,
95 .mask = 0xff,
107 .bit = 4,
[all …]
/linux/sound/soc/intel/common/
H A Dsoc-acpi-intel-mtl-match.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * soc-acpi-intel-mtl-match.c - tables and support for MTL ACPI enumeration.
11 #include <sound/soc-acpi.h>
12 #include <sound/soc-acpi-intel-match.h>
13 #include <sound/soc-acpi-intel-ssp-common.h>
14 #include "soc-acpi-intel-sdca-quirks.h"
15 #include "soc-acpi-intel-sdw-mockup-match.h"
38 .sof_tplg_filename = "sof-mtl-es83x6-ssp1-hdmi-ssp02.tplg",
42 .drv_name = "sof-essx8336",
43 .sof_tplg_filename = "sof-mtl-es8336", /* the tplg suffix is added at run time */
[all …]
H A Dsoc-acpi-intel-adl-match.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * soc-apci-intel-adl-match.c - tables and support for ADL ACPI enumeration.
8 #include <sound/soc-acpi.h>
9 #include <sound/soc-acpi-intel-match.h>
10 #include <sound/soc-acpi-intel-ssp-common.h>
132 .name_prefix = "rt1308-1"
141 .name_prefix = "rt1308-2"
177 .name_prefix = "rt1316-1"
186 .name_prefix = "rt1316-2"
195 .name_prefix = "rt1316-2"
[all …]
H A Dsoc-acpi-intel-tgl-match.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * soc-acpi-intel-tgl-match.c - tables and support for TGL ACPI enumeration.
9 #include <sound/soc-acpi.h>
10 #include <sound/soc-acpi-intel-match.h>
11 #include <sound/soc-acpi-intel-ssp-common.h>
12 #include "soc-acpi-intel-sdw-mockup-match.h"
92 .name_prefix = "rt1308-1"
98 .name_prefix = "rt1308-2"
107 .name_prefix = "rt1308-1"
116 .name_prefix = "rt1308-1"
[all …]
H A Dsoc-acpi-intel-lnl-match.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * soc-acpi-intel-lnl-match.c - tables and support for LNL ACPI enumeration.
9 #include <sound/soc-acpi.h>
10 #include <sound/soc-acpi-intel-match.h>
11 #include "soc-acpi-intel-sdca-quirks.h"
12 #include "soc-acpi-intel-sdw-mockup-match.h"
70 * RT722 is a multi-function codec, three endpoints are created for
222 .name_prefix = "rt712-dmic"
249 .name_prefix = "rt1316-1"
258 .name_prefix = "rt1316-2"
[all …]
/linux/drivers/staging/vme_user/
H A Dvme_tsi148.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
50 * Layout of a DMAC Linked-List Descriptor
53 * correctly laid out - It must also be aligned on 64-bit boundaries.
70 * The descriptor needs to be aligned on a 64-bit boundary, we increase
79 * TSI148 ASIC register structure overlays and bit field definitions.
83 * PCFS - PCI Configuration Space Registers
84 * LCSR - Local Control and Status Registers
85 * GCSR - Global Control and Status Registers
86 * CR/CSR - Subset of Configuration ROM /
489 * offset 0x00 0x600 - DEVI/VENI
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/linux/include/media/drv-intf/
H A Dsaa7146.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <linux/delay.h> /* for delay-stuff */
7 #include <linux/pci.h> /* for pci-config-stuff, vendor ids etc. */
16 #include <media/v4l2-device.h>
17 #include <media/v4l2-ctrls.h>
22 #define saa7146_write(sxy,adr,dat) writel((dat),(sxy->mem+(adr)))
23 #define saa7146_read(sxy,adr) readl(sxy->mem+(adr))
33 #define _DBG(mask, fmt, ...) \ argument
35 if (DEBUG_VARIABLE & mask) \
107 u32 irq_mask; /* mask to indicate, which irq-events are handled by the extension */
[all …]
/linux/include/linux/
H A Dpxa2xx_ssp.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * This driver supports the following PXA CPU/SSP ports:-
49 #define SSCR0_DSS GENMASK(3, 0) /* Data Size Select (mask) */
50 #define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */
51 #define SSCR0_FRF GENMASK(5, 4) /* FRame Format (mask) */
55 #define SSCR0_ECS BIT(6) /* External clock select */
56 #define SSCR0_SSE BIT(7) /* Synchronous Serial Port Enable */
57 #define SSCR0_SCR(x) ((x) << 8) /* Serial Clock Rate (mask) */
60 #define SSCR0_EDSS BIT(20) /* Extended data size select */
61 #define SSCR0_NCS BIT(21) /* Network clock select */
[all …]
/linux/tools/testing/selftests/kvm/lib/
H A Dsparsebit.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Sparse bit array
8 * This library provides functions to support a memory efficient bit array,
27 * sparsebit_alloc() and most also take a bit index. Frequently
30 * ---- Query Operations
37 * ---- Modifying Operations
55 * The index of the first bit set needs to be obtained via
60 * is at least 1 bit in the array set. This is because sparsebit_first_set()
63 * sparsebit array has at least a single bit set before calling
75 * At a high-level the state of the bit settings are maintained through
[all …]
/linux/include/asm-generic/bitops/
H A Dgeneric-non-atomic.h1 /* SPDX-License-Identifier: GPL-2.0-only */
14 * Generic definitions for bit operations, should not be used in regular code
19 * generic___set_bit - Set a bit in memory
20 * @nr: the bit to set
23 * Unlike set_bit(), this function is non-atomic and may be reordered.
30 unsigned long mask = BIT_MASK(nr); in generic___set_bit() local
33 *p |= mask; in generic___set_bit()
39 unsigned long mask = BIT_MASK(nr); in generic___clear_bit() local
42 *p &= ~mask; in generic___clear_bit()
46 * generic___change_bit - Toggle a bit in memory
[all …]
/linux/arch/xtensa/include/asm/
H A Dbitops.h2 * include/asm-xtensa/bitops.h
10 * Copyright (C) 2001 - 2007 Tensilica Inc.
24 #include <asm-generic/bitops/non-atomic.h>
37 * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
42 return 31 - __cntlz(~x & -~x); in ffz()
46 * __ffs: Find first bit set in word. Return 0 for bit 0
51 return 31 - __cntlz(x & -x); in __ffs()
55 * ffs: Find first bit set in word. This is defined the same way as
62 return 32 - __cntlz(x & -x); in ffs()
66 * fls: Find last (most-significant) bit set in word.
[all …]
/linux/arch/alpha/kernel/
H A Dsys_sable.c1 // SPDX-License-Identifier: GPL-2.0
9 * Code supporting the Sable, Sable-Gamma, and Lynx systems.
39 /* Note mask bit is true for DISABLED irqs. */
42 void (*update_irq_hw)(unsigned long bit, unsigned long mask);
43 void (*ack_irq_hw)(unsigned long bit);
58 * 0-7 (char at 536)
59 * 8-15 (char at 53a)
60 * 16-23 (char at 53c)
64 * Bit Meaning Kernel IRQ
65 *------------------------------------------
[all …]
/linux/drivers/mfd/
H A Diqs62x.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Azoteq IQS620A/621/622/624/625 Multi-Function Sensors
7 * These devices rely on application-specific register settings and calibration
9 * separate tool converts the GUIs' ASCII-based output into a standard firmware
14 * Link to conversion tool: https://github.com/jlabundy/iqs62x-h2bin.git
49 #define IQS620_PROX_SETTINGS_4_SAR_EN BIT(7)
59 #define IQS62X_SYS_SETTINGS_ACK_RESET BIT(6)
60 #define IQS62X_SYS_SETTINGS_EVENT_MODE BIT(5)
61 #define IQS62X_SYS_SETTINGS_CLK_DIV BIT(4)
62 #define IQS62X_SYS_SETTINGS_COMM_ATI BIT(3)
[all …]
/linux/arch/sparc/include/asm/
H A Dbitops_32.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * bitops.h: Bit string operations on the Sparc.
22 unsigned long sp32___set_bit(unsigned long *addr, unsigned long mask);
23 unsigned long sp32___clear_bit(unsigned long *addr, unsigned long mask);
24 unsigned long sp32___change_bit(unsigned long *addr, unsigned long mask);
27 * Set bit 'nr' in 32-bit quantity at address 'addr' where bit '0'
28 * is in the highest of the four bytes and bit '31' is the high bit
29 * within the first byte. Sparc is BIG-Endian. Unless noted otherwise
30 * all bit-ops return 0 if bit was previously clear and != 0 otherwise.
34 unsigned long *ADDR, mask; in test_and_set_bit() local
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/linux/arch/mips/boot/dts/mti/
H A Dsead3.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/mips-gic.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
13 compatible = "mti,sead-3";
14 model = "MIPS SEAD-3";
17 stdout-path = "serial1:115200";
36 cpu_intc: interrupt-controller {
37 compatible = "mti,cpu-interrupt-controller";
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