1 // SPDX-License-Identifier: GPL-2.0-or-later
35 		.mask	= IPIC_SIMSR_H,
38 		.bit	= 16,
42 		.mask	= IPIC_SIMSR_H,
45 		.bit	= 17,
49 		.mask	= IPIC_SIMSR_H,
52 		.bit	= 18,
56 		.mask	= IPIC_SIMSR_H,
59 		.bit	= 19,
63 		.mask	= IPIC_SIMSR_H,
66 		.bit	= 20,
70 		.mask	= IPIC_SIMSR_H,
73 		.bit	= 21,
77 		.mask	= IPIC_SIMSR_H,
80 		.bit	= 22,
84 		.mask	= IPIC_SIMSR_H,
87 		.bit	= 23,
91 		.mask	= IPIC_SIMSR_H,
94 		.bit	= 24,
98 		.mask	= IPIC_SIMSR_H,
101 		.bit	= 25,
105 		.mask	= IPIC_SIMSR_H,
108 		.bit	= 26,
112 		.mask	= IPIC_SIMSR_H,
115 		.bit	= 27,
119 		.mask	= IPIC_SIMSR_H,
122 		.bit	= 28,
126 		.mask	= IPIC_SIMSR_H,
129 		.bit	= 29,
133 		.mask	= IPIC_SIMSR_H,
136 		.bit	= 30,
140 		.mask	= IPIC_SIMSR_H,
143 		.bit	= 31,
148 		.mask	= IPIC_SEMSR,
151 		.bit	= 1,
156 		.mask	= IPIC_SEMSR,
159 		.bit	= 2,
164 		.mask	= IPIC_SEMSR,
167 		.bit	= 3,
172 		.mask	= IPIC_SEMSR,
175 		.bit	= 4,
180 		.mask	= IPIC_SEMSR,
183 		.bit	= 5,
188 		.mask	= IPIC_SEMSR,
191 		.bit	= 6,
196 		.mask	= IPIC_SEMSR,
199 		.bit	= 7,
203 		.mask	= IPIC_SIMSR_H,
206 		.bit	= 0,
210 		.mask	= IPIC_SIMSR_H,
213 		.bit	= 1,
217 		.mask	= IPIC_SIMSR_H,
220 		.bit	= 2,
224 		.mask	= IPIC_SIMSR_H,
227 		.bit	= 3,
231 		.mask	= IPIC_SIMSR_H,
234 		.bit	= 4,
238 		.mask	= IPIC_SIMSR_H,
241 		.bit	= 5,
245 		.mask	= IPIC_SIMSR_H,
248 		.bit	= 6,
252 		.mask	= IPIC_SIMSR_H,
255 		.bit	= 7,
259 		.mask	= IPIC_SIMSR_H,
262 		.bit	= 8,
266 		.mask	= IPIC_SIMSR_H,
269 		.bit	= 9,
273 		.mask	= IPIC_SIMSR_H,
276 		.bit	= 10,
280 		.mask	= IPIC_SIMSR_H,
283 		.bit	= 11,
287 		.mask	= IPIC_SIMSR_H,
290 		.bit	= 12,
294 		.mask	= IPIC_SIMSR_H,
297 		.bit	= 13,
301 		.mask	= IPIC_SIMSR_H,
304 		.bit	= 14,
308 		.mask	= IPIC_SIMSR_H,
311 		.bit	= 15,
316 		.mask	= IPIC_SEMSR,
319 		.bit	= 0,
323 		.mask	= IPIC_SIMSR_L,
326 		.bit	= 0,
330 		.mask	= IPIC_SIMSR_L,
333 		.bit	= 1,
337 		.mask	= IPIC_SIMSR_L,
340 		.bit	= 2,
344 		.mask	= IPIC_SIMSR_L,
347 		.bit	= 3,
351 		.mask	= IPIC_SIMSR_L,
354 		.bit	= 4,
358 		.mask	= IPIC_SIMSR_L,
361 		.bit	= 5,
365 		.mask	= IPIC_SIMSR_L,
368 		.bit	= 6,
372 		.mask	= IPIC_SIMSR_L,
375 		.bit	= 7,
379 		.mask	= IPIC_SIMSR_L,
382 		.bit	= 8,
385 		.mask	= IPIC_SIMSR_L,
388 		.bit	= 9,
391 		.mask	= IPIC_SIMSR_L,
394 		.bit	= 10,
397 		.mask	= IPIC_SIMSR_L,
400 		.bit	= 11,
403 		.mask	= IPIC_SIMSR_L,
406 		.bit	= 12,
409 		.mask	= IPIC_SIMSR_L,
412 		.bit	= 13,
415 		.mask	= IPIC_SIMSR_L,
418 		.bit	= 14,
421 		.mask	= IPIC_SIMSR_L,
424 		.bit	= 15,
427 		.mask	= IPIC_SIMSR_L,
430 		.bit	= 16,
433 		.mask	= IPIC_SIMSR_L,
436 		.bit	= 17,
439 		.mask	= IPIC_SIMSR_L,
442 		.bit	= 18,
445 		.mask	= IPIC_SIMSR_L,
448 		.bit	= 19,
451 		.mask	= IPIC_SIMSR_L,
454 		.bit	= 20,
457 		.mask	= IPIC_SIMSR_L,
460 		.bit	= 21,
463 		.mask	= IPIC_SIMSR_L,
466 		.bit	= 22,
469 		.mask	= IPIC_SIMSR_L,
472 		.bit	= 23,
475 		.mask	= IPIC_SIMSR_L,
478 		.bit	= 24,
481 		.mask	= IPIC_SIMSR_L,
484 		.bit	= 25,
487 		.mask	= IPIC_SIMSR_L,
490 		.bit	= 26,
493 		.mask	= IPIC_SIMSR_L,
496 		.bit	= 27,
499 		.mask	= IPIC_SIMSR_L,
502 		.bit	= 30,
523 	struct ipic *ipic = ipic_from_irq(d->irq);  in ipic_unmask_irq()
530 	temp = ipic_read(ipic->regs, ipic_info[src].mask);  in ipic_unmask_irq()
531 	temp |= (1 << (31 - ipic_info[src].bit));  in ipic_unmask_irq()
532 	ipic_write(ipic->regs, ipic_info[src].mask, temp);  in ipic_unmask_irq()
539 	struct ipic *ipic = ipic_from_irq(d->irq);  in ipic_mask_irq()
546 	temp = ipic_read(ipic->regs, ipic_info[src].mask);  in ipic_mask_irq()
547 	temp &= ~(1 << (31 - ipic_info[src].bit));  in ipic_mask_irq()
548 	ipic_write(ipic->regs, ipic_info[src].mask, temp);  in ipic_mask_irq()
559 	struct ipic *ipic = ipic_from_irq(d->irq);  in ipic_ack_irq()
566 	temp = 1 << (31 - ipic_info[src].bit);  in ipic_ack_irq()
567 	ipic_write(ipic->regs, ipic_info[src].ack, temp);  in ipic_ack_irq()
578 	struct ipic *ipic = ipic_from_irq(d->irq);  in ipic_mask_irq_and_ack()
585 	temp = ipic_read(ipic->regs, ipic_info[src].mask);  in ipic_mask_irq_and_ack()
586 	temp &= ~(1 << (31 - ipic_info[src].bit));  in ipic_mask_irq_and_ack()
587 	ipic_write(ipic->regs, ipic_info[src].mask, temp);  in ipic_mask_irq_and_ack()
589 	temp = 1 << (31 - ipic_info[src].bit);  in ipic_mask_irq_and_ack()
590 	ipic_write(ipic->regs, ipic_info[src].ack, temp);  in ipic_mask_irq_and_ack()
601 	struct ipic *ipic = ipic_from_irq(d->irq);  in ipic_set_irq_type()
608 	/* ipic supports only low assertion and high-to-low change senses  in ipic_set_irq_type()
613 		return -EINVAL;  in ipic_set_irq_type()
619 		return -EINVAL;  in ipic_set_irq_type()
626 		d->chip = &ipic_level_irq_chip;  in ipic_set_irq_type()
629 		d->chip = &ipic_edge_irq_chip;  in ipic_set_irq_type()
639 			edibit = (14 - (src - IPIC_IRQ_EXT1));  in ipic_set_irq_type()
641 			return (flow_type & IRQ_TYPE_LEVEL_LOW) ? 0 : -EINVAL;  in ipic_set_irq_type()
643 	vold = ipic_read(ipic->regs, IPIC_SECNR);  in ipic_set_irq_type()
650 		ipic_write(ipic->regs, IPIC_SECNR, vnew);  in ipic_set_irq_type()
683 	struct ipic *ipic = h->host_data;  in ipic_host_map()
714 	ipic->irqhost = irq_domain_add_linear(node, NR_IPIC_INTS,  in ipic_init()
716 	if (ipic->irqhost == NULL) {  in ipic_init()
721 	ipic->regs = ioremap(res.start, resource_size(&res));  in ipic_init()
724 	ipic_write(ipic->regs, IPIC_SICNR, 0x0);  in ipic_init()
741 	ipic_write(ipic->regs, IPIC_SICFR, temp);  in ipic_init()
747 	ipic_write(ipic->regs, IPIC_SERCR, temp);  in ipic_init()
750 	temp = ipic_read(ipic->regs, IPIC_SEMSR);  in ipic_init()
757 	ipic_write(ipic->regs, IPIC_SEMSR, temp);  in ipic_init()
760 	irq_set_default_host(primary_ipic->irqhost);  in ipic_init()
762 	ipic_write(ipic->regs, IPIC_SIMSR_H, 0);  in ipic_init()
763 	ipic_write(ipic->regs, IPIC_SIMSR_L, 0);  in ipic_init()
766 			primary_ipic->regs);  in ipic_init()
773 	ipic_write(primary_ipic->regs, IPIC_SIPRR_A, IPIC_PRIORITY_DEFAULT);  in ipic_set_default_priority()
774 	ipic_write(primary_ipic->regs, IPIC_SIPRR_B, IPIC_PRIORITY_DEFAULT);  in ipic_set_default_priority()
775 	ipic_write(primary_ipic->regs, IPIC_SIPRR_C, IPIC_PRIORITY_DEFAULT);  in ipic_set_default_priority()
776 	ipic_write(primary_ipic->regs, IPIC_SIPRR_D, IPIC_PRIORITY_DEFAULT);  in ipic_set_default_priority()
777 	ipic_write(primary_ipic->regs, IPIC_SMPRR_A, IPIC_PRIORITY_DEFAULT);  in ipic_set_default_priority()
778 	ipic_write(primary_ipic->regs, IPIC_SMPRR_B, IPIC_PRIORITY_DEFAULT);  in ipic_set_default_priority()
783 	return primary_ipic ? ipic_read(primary_ipic->regs, IPIC_SERSR) : 0;  in ipic_get_mcp_status()
786 void ipic_clear_mcp_status(u32 mask)  in ipic_clear_mcp_status()  argument
788 	ipic_write(primary_ipic->regs, IPIC_SERSR, mask);  in ipic_clear_mcp_status()
799 	irq = ipic_read(primary_ipic->regs, IPIC_SIVCR) & IPIC_SIVCR_VECTOR_MASK;  in ipic_get_irq()
801 	if (irq == 0)    /* 0 --> no irq is pending */  in ipic_get_irq()
804 	return irq_linear_revmap(primary_ipic->irqhost, irq);  in ipic_get_irq()
824 	ipic_saved_state.sicfr = ipic_read(ipic->regs, IPIC_SICFR);  in ipic_suspend()
825 	ipic_saved_state.siprr[0] = ipic_read(ipic->regs, IPIC_SIPRR_A);  in ipic_suspend()
826 	ipic_saved_state.siprr[1] = ipic_read(ipic->regs, IPIC_SIPRR_D);  in ipic_suspend()
827 	ipic_saved_state.simsr[0] = ipic_read(ipic->regs, IPIC_SIMSR_H);  in ipic_suspend()
828 	ipic_saved_state.simsr[1] = ipic_read(ipic->regs, IPIC_SIMSR_L);  in ipic_suspend()
829 	ipic_saved_state.sicnr = ipic_read(ipic->regs, IPIC_SICNR);  in ipic_suspend()
830 	ipic_saved_state.smprr[0] = ipic_read(ipic->regs, IPIC_SMPRR_A);  in ipic_suspend()
831 	ipic_saved_state.smprr[1] = ipic_read(ipic->regs, IPIC_SMPRR_B);  in ipic_suspend()
832 	ipic_saved_state.semsr = ipic_read(ipic->regs, IPIC_SEMSR);  in ipic_suspend()
833 	ipic_saved_state.secnr = ipic_read(ipic->regs, IPIC_SECNR);  in ipic_suspend()
834 	ipic_saved_state.sermr = ipic_read(ipic->regs, IPIC_SERMR);  in ipic_suspend()
835 	ipic_saved_state.sercr = ipic_read(ipic->regs, IPIC_SERCR);  in ipic_suspend()
842 		ipic_write(ipic->regs, IPIC_SIMSR_H, 0);  in ipic_suspend()
843 		ipic_write(ipic->regs, IPIC_SIMSR_L, 0);  in ipic_suspend()
844 		ipic_write(ipic->regs, IPIC_SEMSR, 0);  in ipic_suspend()
845 		ipic_write(ipic->regs, IPIC_SERMR, 0);  in ipic_suspend()
855 	ipic_write(ipic->regs, IPIC_SICFR, ipic_saved_state.sicfr);  in ipic_resume()
856 	ipic_write(ipic->regs, IPIC_SIPRR_A, ipic_saved_state.siprr[0]);  in ipic_resume()
857 	ipic_write(ipic->regs, IPIC_SIPRR_D, ipic_saved_state.siprr[1]);  in ipic_resume()
858 	ipic_write(ipic->regs, IPIC_SIMSR_H, ipic_saved_state.simsr[0]);  in ipic_resume()
859 	ipic_write(ipic->regs, IPIC_SIMSR_L, ipic_saved_state.simsr[1]);  in ipic_resume()
860 	ipic_write(ipic->regs, IPIC_SICNR, ipic_saved_state.sicnr);  in ipic_resume()
861 	ipic_write(ipic->regs, IPIC_SMPRR_A, ipic_saved_state.smprr[0]);  in ipic_resume()
862 	ipic_write(ipic->regs, IPIC_SMPRR_B, ipic_saved_state.smprr[1]);  in ipic_resume()
863 	ipic_write(ipic->regs, IPIC_SEMSR, ipic_saved_state.semsr);  in ipic_resume()
864 	ipic_write(ipic->regs, IPIC_SECNR, ipic_saved_state.secnr);  in ipic_resume()
865 	ipic_write(ipic->regs, IPIC_SERMR, ipic_saved_state.sermr);  in ipic_resume()
866 	ipic_write(ipic->regs, IPIC_SERCR, ipic_saved_state.sercr);  in ipic_resume()
880 	if (!primary_ipic || !primary_ipic->regs)  in init_ipic_syscore()
881 		return -ENODEV;  in init_ipic_syscore()