Lines Matching +full:bit +full:- +full:mask
1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <linux/delay.h> /* for delay-stuff */
7 #include <linux/pci.h> /* for pci-config-stuff, vendor ids etc. */
16 #include <media/v4l2-device.h>
17 #include <media/v4l2-ctrls.h>
22 #define saa7146_write(sxy,adr,dat) writel((dat),(sxy->mem+(adr)))
23 #define saa7146_read(sxy,adr) readl(sxy->mem+(adr))
33 #define _DBG(mask, fmt, ...) \ argument
35 if (DEBUG_VARIABLE & mask) \
107 u32 irq_mask; /* mask to indicate, which irq-events are handled by the extension */
129 u32 revision; /* chip revision; needed for bug-workarounds*/
131 /* pci-device & irq stuff*/
146 /* i2c-stuff */
184 #define SAA7146_I2C_TIMEOUT 100 /* i2c-timeout-value in ms */
185 #define SAA7146_I2C_RETRIES 3 /* how many times shall we retry an i2c-operation? */
186 #define SAA7146_I2C_DELAY 5 /* time we wait after certain i2c-operations */
215 #define CMD_WR_REG_MASK 0xc0000000 /* Write register with mask */
236 /* Bit mask constants */
237 #define MASK_00 0x00000001 /* Mask value for bit 0 */
238 #define MASK_01 0x00000002 /* Mask value for bit 1 */
239 #define MASK_02 0x00000004 /* Mask value for bit 2 */
240 #define MASK_03 0x00000008 /* Mask value for bit 3 */
241 #define MASK_04 0x00000010 /* Mask value for bit 4 */
242 #define MASK_05 0x00000020 /* Mask value for bit 5 */
243 #define MASK_06 0x00000040 /* Mask value for bit 6 */
244 #define MASK_07 0x00000080 /* Mask value for bit 7 */
245 #define MASK_08 0x00000100 /* Mask value for bit 8 */
246 #define MASK_09 0x00000200 /* Mask value for bit 9 */
247 #define MASK_10 0x00000400 /* Mask value for bit 10 */
248 #define MASK_11 0x00000800 /* Mask value for bit 11 */
249 #define MASK_12 0x00001000 /* Mask value for bit 12 */
250 #define MASK_13 0x00002000 /* Mask value for bit 13 */
251 #define MASK_14 0x00004000 /* Mask value for bit 14 */
252 #define MASK_15 0x00008000 /* Mask value for bit 15 */
253 #define MASK_16 0x00010000 /* Mask value for bit 16 */
254 #define MASK_17 0x00020000 /* Mask value for bit 17 */
255 #define MASK_18 0x00040000 /* Mask value for bit 18 */
256 #define MASK_19 0x00080000 /* Mask value for bit 19 */
257 #define MASK_20 0x00100000 /* Mask value for bit 20 */
258 #define MASK_21 0x00200000 /* Mask value for bit 21 */
259 #define MASK_22 0x00400000 /* Mask value for bit 22 */
260 #define MASK_23 0x00800000 /* Mask value for bit 23 */
261 #define MASK_24 0x01000000 /* Mask value for bit 24 */
262 #define MASK_25 0x02000000 /* Mask value for bit 25 */
263 #define MASK_26 0x04000000 /* Mask value for bit 26 */
264 #define MASK_27 0x08000000 /* Mask value for bit 27 */
265 #define MASK_28 0x10000000 /* Mask value for bit 28 */
266 #define MASK_29 0x20000000 /* Mask value for bit 29 */
267 #define MASK_30 0x40000000 /* Mask value for bit 30 */
268 #define MASK_31 0x80000000 /* Mask value for bit 31 */
270 #define MASK_B0 0x000000ff /* Mask value for byte 0 */
271 #define MASK_B1 0x0000ff00 /* Mask value for byte 1 */
272 #define MASK_B2 0x00ff0000 /* Mask value for byte 2 */
273 #define MASK_B3 0xff000000 /* Mask value for byte 3 */
275 #define MASK_W0 0x0000ffff /* Mask value for word 0 */
276 #define MASK_W1 0xffff0000 /* Mask value for word 1 */
278 #define MASK_PA 0xfffffffc /* Mask value for physical address */
279 #define MASK_PR 0xfffffffe /* Mask value for protection register */
280 #define MASK_ER 0xffffffff /* Mask value for the entire register */
282 #define MASK_NONE 0x00000000 /* No mask */
362 #define GPIO_CTRL 0xE0 /* GPIO 0-3 register */
395 #define A_TIME_SLOT1 0x180, /* from 180 - 1BC */
396 #define A_TIME_SLOT2 0x1C0, /* from 1C0 - 1FC */
419 #define SPCI_AFOU 0x00000800 /* Audio FIFO over- / underflow */
421 #define SPCI_VFOU 0x00000200 /* Video FIFO over- / underflow */
459 spin_lock_irqsave(&x->int_slock, flags); in SAA7146_IER_DISABLE()
461 spin_unlock_irqrestore(&x->int_slock, flags); in SAA7146_IER_DISABLE()
467 spin_lock_irqsave(&x->int_slock, flags); in SAA7146_IER_ENABLE()
469 spin_unlock_irqrestore(&x->int_slock, flags); in SAA7146_IER_ENABLE()