Lines Matching +full:bit +full:- +full:mask
1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * This driver supports the following PXA CPU/SSP ports:-
49 #define SSCR0_DSS GENMASK(3, 0) /* Data Size Select (mask) */
50 #define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */
51 #define SSCR0_FRF GENMASK(5, 4) /* FRame Format (mask) */
55 #define SSCR0_ECS BIT(6) /* External clock select */
56 #define SSCR0_SSE BIT(7) /* Synchronous Serial Port Enable */
57 #define SSCR0_SCR(x) ((x) << 8) /* Serial Clock Rate (mask) */
60 #define SSCR0_EDSS BIT(20) /* Extended data size select */
61 #define SSCR0_NCS BIT(21) /* Network clock select */
62 #define SSCR0_RIM BIT(22) /* Receive FIFO overrun interrupt mask */
63 #define SSCR0_TUM BIT(23) /* Transmit FIFO underrun interrupt mask */
64 #define SSCR0_FRDC GENMASK(26, 24) /* Frame rate divider control (mask) */
65 #define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */
66 #define SSCR0_FPCKE BIT(29) /* FIFO packing enable */
67 #define SSCR0_ACS BIT(30) /* Audio clock select */
68 #define SSCR0_MOD BIT(31) /* Mode (normal or network) */
70 #define SSCR1_RIE BIT(0) /* Receive FIFO Interrupt Enable */
71 #define SSCR1_TIE BIT(1) /* Transmit FIFO Interrupt Enable */
72 #define SSCR1_LBM BIT(2) /* Loop-Back Mode */
73 #define SSCR1_SPO BIT(3) /* Motorola SPI SSPSCLK polarity setting */
74 #define SSCR1_SPH BIT(4) /* Motorola SPI SSPSCLK phase setting */
75 #define SSCR1_MWDS BIT(5) /* Microwire Transmit Data Size */
78 #define SSSR_TNF BIT(2) /* Transmit FIFO Not Full */
79 #define SSSR_RNE BIT(3) /* Receive FIFO Not Empty */
80 #define SSSR_BSY BIT(4) /* SSP Busy */
81 #define SSSR_TFS BIT(5) /* Transmit FIFO Service Request */
82 #define SSSR_RFS BIT(6) /* Receive FIFO Service Request */
83 #define SSSR_ROR BIT(7) /* Receive FIFO Overrun */
88 #define SSSR_TFL_MASK GENMASK(11, 8) /* Transmit FIFO Level mask */
89 #define SSSR_RFL_MASK GENMASK(15, 12) /* Receive FIFO Level mask */
91 #define SSCR1_TFT GENMASK(9, 6) /* Transmit FIFO Threshold (mask) */
92 #define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */
93 #define SSCR1_RFT GENMASK(13, 10) /* Receive FIFO Threshold (mask) */
94 #define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */
99 #define CE4100_SSSR_TFL_MASK GENMASK(9, 8) /* Transmit FIFO Level mask */
100 #define CE4100_SSSR_RFL_MASK GENMASK(13, 12) /* Receive FIFO Level mask */
102 #define CE4100_SSCR1_TFT GENMASK(7, 6) /* Transmit FIFO Threshold (mask) */
103 #define CE4100_SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..4] */
104 #define CE4100_SSCR1_RFT GENMASK(11, 10) /* Receive FIFO Threshold (mask) */
105 #define CE4100_SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..4] */
110 /* QUARK_X1000 SSCR0 bit definition */
111 #define QUARK_X1000_SSCR0_DSS GENMASK(4, 0) /* Data Size Select (mask) */
112 #define QUARK_X1000_SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..32] */
113 #define QUARK_X1000_SSCR0_FRF GENMASK(6, 5) /* FRame Format (mask) */
119 #define QUARK_X1000_SSSR_TFL_MASK GENMASK(12, 8) /* Transmit FIFO Level mask */
120 #define QUARK_X1000_SSSR_RFL_MASK GENMASK(17, 13) /* Receive FIFO Level mask */
122 #define QUARK_X1000_SSCR1_TFT GENMASK(10, 6) /* Transmit FIFO Threshold (mask) */
123 #define QUARK_X1000_SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..32] */
124 #define QUARK_X1000_SSCR1_RFT GENMASK(15, 11) /* Receive FIFO Threshold (mask) */
125 #define QUARK_X1000_SSCR1_RxTresh(x) (((x) - 1) << 11) /* level [1..32] */
126 #define QUARK_X1000_SSCR1_EFWR BIT(16) /* Enable FIFO Write/Read */
127 #define QUARK_X1000_SSCR1_STRF BIT(17) /* Select FIFO or EFWR */
131 #define SSCR0_PSP (3 << 4) /* PSP - Programmable Serial Protocol */
133 #define SSCR1_EFWR BIT(14) /* Enable FIFO Write/Read */
134 #define SSCR1_STRF BIT(15) /* Select FIFO or EFWR */
135 #define SSCR1_IFS BIT(16) /* Invert Frame Signal */
136 #define SSCR1_PINTE BIT(18) /* Peripheral Trailing Byte Interrupt Enable */
137 #define SSCR1_TINTE BIT(19) /* Receiver Time-out Interrupt enable */
138 #define SSCR1_RSRE BIT(20) /* Receive Service Request Enable */
139 #define SSCR1_TSRE BIT(21) /* Transmit Service Request Enable */
140 #define SSCR1_TRAIL BIT(22) /* Trailing Byte */
141 #define SSCR1_RWOT BIT(23) /* Receive Without Transmit */
142 #define SSCR1_SFRMDIR BIT(24) /* Frame Direction */
143 #define SSCR1_SCLKDIR BIT(25) /* Serial Bit Rate Clock Direction */
144 #define SSCR1_ECRB BIT(26) /* Enable Clock request B */
145 #define SSCR1_ECRA BIT(27) /* Enable Clock Request A */
146 #define SSCR1_SCFR BIT(28) /* Slave Clock free Running */
147 #define SSCR1_EBCEI BIT(29) /* Enable Bit Count Error interrupt */
148 #define SSCR1_TTE BIT(30) /* TXD Tristate Enable */
149 #define SSCR1_TTELP BIT(31) /* TXD Tristate Enable Last Phase */
151 #define SSSR_PINT BIT(18) /* Peripheral Trailing Byte Interrupt */
152 #define SSSR_TINT BIT(19) /* Receiver Time-out Interrupt */
153 #define SSSR_EOC BIT(20) /* End Of Chain */
154 #define SSSR_TUR BIT(21) /* Transmit FIFO Under Run */
155 #define SSSR_CSS BIT(22) /* Clock Synchronisation Status */
156 #define SSSR_BCE BIT(23) /* Bit Count Error */
158 #define SSPSP_SCMODE(x) ((x) << 0) /* Serial Bit Rate Clock Mode */
159 #define SSPSP_SFRMP BIT(2) /* Serial Frame Polarity */
160 #define SSPSP_ETDS BIT(3) /* End of Transfer data State */
166 #define SSPSP_FSRT BIT(25) /* Frame Sync Relative Timing */
180 #define SSACD_SCDB BIT(3) /* SSPSYSCLK Divider Bypass */
184 #define SSACD_SCDX8 BIT(7) /* SYSCLK division ratio select */
193 #define SFIFOL_TFL_MASK GENMASK(15, 0) /* Transmit FIFO Level mask */
194 #define SFIFOL_RFL_MASK GENMASK(31, 16) /* Receive FIFO Level mask */
196 #define SFIFOTT_TFT GENMASK(15, 0) /* Transmit FIFO Threshold (mask) */
197 #define SFIFOTT_TxThresh(x) (((x) - 1) << 0) /* TX FIFO trigger threshold / level */
198 #define SFIFOTT_RFT GENMASK(31, 16) /* Receive FIFO Threshold (mask) */
199 #define SFIFOTT_RxThresh(x) (((x) - 1) << 16) /* RX FIFO trigger threshold / level */
203 #define SSITF_TxHiThresh(x) (((x) - 1) << 0)
204 #define SSITF_TxLoThresh(x) (((x) - 1) << 8)
207 #define SSIRF_RxThresh(x) ((x) - 1)
253 * pxa_ssp_write_reg - Write to a SSP register
261 __raw_writel(val, dev->mmio_base + reg); in pxa_ssp_write_reg()
265 * pxa_ssp_read_reg - Read from a SSP register
272 return __raw_readl(dev->mmio_base + reg); in pxa_ssp_read_reg()