1b2441318SGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0
21da177e4SLinus Torvalds /*
31da177e4SLinus Torvalds * linux/arch/alpha/kernel/sys_sable.c
41da177e4SLinus Torvalds *
51da177e4SLinus Torvalds * Copyright (C) 1995 David A Rusling
61da177e4SLinus Torvalds * Copyright (C) 1996 Jay A Estabrook
71da177e4SLinus Torvalds * Copyright (C) 1998, 1999 Richard Henderson
81da177e4SLinus Torvalds *
91da177e4SLinus Torvalds * Code supporting the Sable, Sable-Gamma, and Lynx systems.
101da177e4SLinus Torvalds */
111da177e4SLinus Torvalds
121da177e4SLinus Torvalds #include <linux/kernel.h>
131da177e4SLinus Torvalds #include <linux/types.h>
141da177e4SLinus Torvalds #include <linux/mm.h>
151da177e4SLinus Torvalds #include <linux/sched.h>
161da177e4SLinus Torvalds #include <linux/pci.h>
171da177e4SLinus Torvalds #include <linux/init.h>
181da177e4SLinus Torvalds
191da177e4SLinus Torvalds #include <asm/ptrace.h>
201da177e4SLinus Torvalds #include <asm/dma.h>
211da177e4SLinus Torvalds #include <asm/irq.h>
221da177e4SLinus Torvalds #include <asm/mmu_context.h>
231da177e4SLinus Torvalds #include <asm/io.h>
241da177e4SLinus Torvalds #include <asm/core_t2.h>
251da177e4SLinus Torvalds #include <asm/tlbflush.h>
261da177e4SLinus Torvalds
271da177e4SLinus Torvalds #include "proto.h"
281da177e4SLinus Torvalds #include "irq_impl.h"
291da177e4SLinus Torvalds #include "pci_impl.h"
301da177e4SLinus Torvalds #include "machvec_impl.h"
311da177e4SLinus Torvalds
321da177e4SLinus Torvalds DEFINE_SPINLOCK(sable_lynx_irq_lock);
331da177e4SLinus Torvalds
341da177e4SLinus Torvalds typedef struct irq_swizzle_struct
351da177e4SLinus Torvalds {
361da177e4SLinus Torvalds char irq_to_mask[64];
371da177e4SLinus Torvalds char mask_to_irq[64];
381da177e4SLinus Torvalds
391da177e4SLinus Torvalds /* Note mask bit is true for DISABLED irqs. */
401da177e4SLinus Torvalds unsigned long shadow_mask;
411da177e4SLinus Torvalds
421da177e4SLinus Torvalds void (*update_irq_hw)(unsigned long bit, unsigned long mask);
431da177e4SLinus Torvalds void (*ack_irq_hw)(unsigned long bit);
441da177e4SLinus Torvalds
451da177e4SLinus Torvalds } irq_swizzle_t;
461da177e4SLinus Torvalds
471da177e4SLinus Torvalds static irq_swizzle_t *sable_lynx_irq_swizzle;
481da177e4SLinus Torvalds
494b1135a2SThomas Gleixner static void sable_lynx_init_irq(int nr_of_irqs);
501da177e4SLinus Torvalds
511da177e4SLinus Torvalds #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_SABLE)
521da177e4SLinus Torvalds
531da177e4SLinus Torvalds /***********************************************************************/
541da177e4SLinus Torvalds /*
551da177e4SLinus Torvalds * For SABLE, which is really baroque, we manage 40 IRQ's, but the
561da177e4SLinus Torvalds * hardware really only supports 24, not via normal ISA PIC,
571da177e4SLinus Torvalds * but cascaded custom 8259's, etc.
581da177e4SLinus Torvalds * 0-7 (char at 536)
591da177e4SLinus Torvalds * 8-15 (char at 53a)
601da177e4SLinus Torvalds * 16-23 (char at 53c)
611da177e4SLinus Torvalds *
621da177e4SLinus Torvalds * Summary Registers (536/53a/53c):
631da177e4SLinus Torvalds *
641da177e4SLinus Torvalds * Bit Meaning Kernel IRQ
651da177e4SLinus Torvalds *------------------------------------------
661da177e4SLinus Torvalds * 0 PCI slot 0 34
671da177e4SLinus Torvalds * 1 NCR810 (builtin) 33
681da177e4SLinus Torvalds * 2 TULIP (builtin) 32
691da177e4SLinus Torvalds * 3 mouse 12
701da177e4SLinus Torvalds * 4 PCI slot 1 35
711da177e4SLinus Torvalds * 5 PCI slot 2 36
721da177e4SLinus Torvalds * 6 keyboard 1
731da177e4SLinus Torvalds * 7 floppy 6
741da177e4SLinus Torvalds * 8 COM2 3
751da177e4SLinus Torvalds * 9 parallel port 7
761da177e4SLinus Torvalds *10 EISA irq 3 -
771da177e4SLinus Torvalds *11 EISA irq 4 -
781da177e4SLinus Torvalds *12 EISA irq 5 5
791da177e4SLinus Torvalds *13 EISA irq 6 -
801da177e4SLinus Torvalds *14 EISA irq 7 -
811da177e4SLinus Torvalds *15 COM1 4
821da177e4SLinus Torvalds *16 EISA irq 9 9
831da177e4SLinus Torvalds *17 EISA irq 10 10
841da177e4SLinus Torvalds *18 EISA irq 11 11
851da177e4SLinus Torvalds *19 EISA irq 12 -
861da177e4SLinus Torvalds *20 EISA irq 13 -
871da177e4SLinus Torvalds *21 EISA irq 14 14
881da177e4SLinus Torvalds *22 NC 15
891da177e4SLinus Torvalds *23 IIC -
901da177e4SLinus Torvalds */
911da177e4SLinus Torvalds
921da177e4SLinus Torvalds static void
sable_update_irq_hw(unsigned long bit,unsigned long mask)931da177e4SLinus Torvalds sable_update_irq_hw(unsigned long bit, unsigned long mask)
941da177e4SLinus Torvalds {
951da177e4SLinus Torvalds int port = 0x537;
961da177e4SLinus Torvalds
971da177e4SLinus Torvalds if (bit >= 16) {
981da177e4SLinus Torvalds port = 0x53d;
991da177e4SLinus Torvalds mask >>= 16;
1001da177e4SLinus Torvalds } else if (bit >= 8) {
1011da177e4SLinus Torvalds port = 0x53b;
1021da177e4SLinus Torvalds mask >>= 8;
1031da177e4SLinus Torvalds }
1041da177e4SLinus Torvalds
1051da177e4SLinus Torvalds outb(mask, port);
1061da177e4SLinus Torvalds }
1071da177e4SLinus Torvalds
1081da177e4SLinus Torvalds static void
sable_ack_irq_hw(unsigned long bit)1091da177e4SLinus Torvalds sable_ack_irq_hw(unsigned long bit)
1101da177e4SLinus Torvalds {
1111da177e4SLinus Torvalds int port, val1, val2;
1121da177e4SLinus Torvalds
1131da177e4SLinus Torvalds if (bit >= 16) {
1141da177e4SLinus Torvalds port = 0x53c;
1151da177e4SLinus Torvalds val1 = 0xE0 | (bit - 16);
1161da177e4SLinus Torvalds val2 = 0xE0 | 4;
1171da177e4SLinus Torvalds } else if (bit >= 8) {
1181da177e4SLinus Torvalds port = 0x53a;
1191da177e4SLinus Torvalds val1 = 0xE0 | (bit - 8);
1201da177e4SLinus Torvalds val2 = 0xE0 | 3;
1211da177e4SLinus Torvalds } else {
1221da177e4SLinus Torvalds port = 0x536;
1231da177e4SLinus Torvalds val1 = 0xE0 | (bit - 0);
1241da177e4SLinus Torvalds val2 = 0xE0 | 1;
1251da177e4SLinus Torvalds }
1261da177e4SLinus Torvalds
1271da177e4SLinus Torvalds outb(val1, port); /* ack the slave */
1281da177e4SLinus Torvalds outb(val2, 0x534); /* ack the master */
1291da177e4SLinus Torvalds }
1301da177e4SLinus Torvalds
1311da177e4SLinus Torvalds static irq_swizzle_t sable_irq_swizzle = {
1321da177e4SLinus Torvalds {
1331da177e4SLinus Torvalds -1, 6, -1, 8, 15, 12, 7, 9, /* pseudo PIC 0-7 */
1341da177e4SLinus Torvalds -1, 16, 17, 18, 3, -1, 21, 22, /* pseudo PIC 8-15 */
1351da177e4SLinus Torvalds -1, -1, -1, -1, -1, -1, -1, -1, /* pseudo EISA 0-7 */
1361da177e4SLinus Torvalds -1, -1, -1, -1, -1, -1, -1, -1, /* pseudo EISA 8-15 */
1371da177e4SLinus Torvalds 2, 1, 0, 4, 5, -1, -1, -1, /* pseudo PCI */
1381da177e4SLinus Torvalds -1, -1, -1, -1, -1, -1, -1, -1, /* */
1391da177e4SLinus Torvalds -1, -1, -1, -1, -1, -1, -1, -1, /* */
1401da177e4SLinus Torvalds -1, -1, -1, -1, -1, -1, -1, -1 /* */
1411da177e4SLinus Torvalds },
1421da177e4SLinus Torvalds {
1431da177e4SLinus Torvalds 34, 33, 32, 12, 35, 36, 1, 6, /* mask 0-7 */
1441da177e4SLinus Torvalds 3, 7, -1, -1, 5, -1, -1, 4, /* mask 8-15 */
1451da177e4SLinus Torvalds 9, 10, 11, -1, -1, 14, 15, -1, /* mask 16-23 */
1461da177e4SLinus Torvalds -1, -1, -1, -1, -1, -1, -1, -1, /* */
1471da177e4SLinus Torvalds -1, -1, -1, -1, -1, -1, -1, -1, /* */
1481da177e4SLinus Torvalds -1, -1, -1, -1, -1, -1, -1, -1, /* */
1491da177e4SLinus Torvalds -1, -1, -1, -1, -1, -1, -1, -1, /* */
1501da177e4SLinus Torvalds -1, -1, -1, -1, -1, -1, -1, -1 /* */
1511da177e4SLinus Torvalds },
1521da177e4SLinus Torvalds -1,
1531da177e4SLinus Torvalds sable_update_irq_hw,
1541da177e4SLinus Torvalds sable_ack_irq_hw
1551da177e4SLinus Torvalds };
1561da177e4SLinus Torvalds
1571da177e4SLinus Torvalds static void __init
sable_init_irq(void)1581da177e4SLinus Torvalds sable_init_irq(void)
1591da177e4SLinus Torvalds {
1601da177e4SLinus Torvalds outb(-1, 0x537); /* slave 0 */
1611da177e4SLinus Torvalds outb(-1, 0x53b); /* slave 1 */
1621da177e4SLinus Torvalds outb(-1, 0x53d); /* slave 2 */
1631da177e4SLinus Torvalds outb(0x44, 0x535); /* enable cascades in master */
1641da177e4SLinus Torvalds
1651da177e4SLinus Torvalds sable_lynx_irq_swizzle = &sable_irq_swizzle;
1661da177e4SLinus Torvalds sable_lynx_init_irq(40);
1671da177e4SLinus Torvalds }
1681da177e4SLinus Torvalds
1691da177e4SLinus Torvalds /*
1701da177e4SLinus Torvalds * PCI Fixup configuration for ALPHA SABLE (2100).
1711da177e4SLinus Torvalds *
1721da177e4SLinus Torvalds * The device to slot mapping looks like:
1731da177e4SLinus Torvalds *
1741da177e4SLinus Torvalds * Slot Device
1751da177e4SLinus Torvalds * 0 TULIP
1761da177e4SLinus Torvalds * 1 SCSI
1771da177e4SLinus Torvalds * 2 PCI-EISA bridge
1781da177e4SLinus Torvalds * 3 none
1791da177e4SLinus Torvalds * 4 none
1801da177e4SLinus Torvalds * 5 none
1811da177e4SLinus Torvalds * 6 PCI on board slot 0
1821da177e4SLinus Torvalds * 7 PCI on board slot 1
1831da177e4SLinus Torvalds * 8 PCI on board slot 2
1841da177e4SLinus Torvalds *
1851da177e4SLinus Torvalds *
1861da177e4SLinus Torvalds * This two layered interrupt approach means that we allocate IRQ 16 and
1871da177e4SLinus Torvalds * above for PCI interrupts. The IRQ relates to which bit the interrupt
1881da177e4SLinus Torvalds * comes in on. This makes interrupt processing much easier.
1891da177e4SLinus Torvalds */
1901da177e4SLinus Torvalds /*
1911da177e4SLinus Torvalds * NOTE: the IRQ assignments below are arbitrary, but need to be consistent
1921da177e4SLinus Torvalds * with the values in the irq swizzling tables above.
1931da177e4SLinus Torvalds */
1941da177e4SLinus Torvalds
195814eae59SLorenzo Pieralisi static int
sable_map_irq(const struct pci_dev * dev,u8 slot,u8 pin)196d5341942SRalf Baechle sable_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
1971da177e4SLinus Torvalds {
198814eae59SLorenzo Pieralisi static char irq_tab[9][5] = {
1991da177e4SLinus Torvalds /*INT INTA INTB INTC INTD */
2001da177e4SLinus Torvalds { 32+0, 32+0, 32+0, 32+0, 32+0}, /* IdSel 0, TULIP */
2011da177e4SLinus Torvalds { 32+1, 32+1, 32+1, 32+1, 32+1}, /* IdSel 1, SCSI */
2021da177e4SLinus Torvalds { -1, -1, -1, -1, -1}, /* IdSel 2, SIO */
2031da177e4SLinus Torvalds { -1, -1, -1, -1, -1}, /* IdSel 3, none */
2041da177e4SLinus Torvalds { -1, -1, -1, -1, -1}, /* IdSel 4, none */
2051da177e4SLinus Torvalds { -1, -1, -1, -1, -1}, /* IdSel 5, none */
2061da177e4SLinus Torvalds { 32+2, 32+2, 32+2, 32+2, 32+2}, /* IdSel 6, slot 0 */
2071da177e4SLinus Torvalds { 32+3, 32+3, 32+3, 32+3, 32+3}, /* IdSel 7, slot 1 */
2081da177e4SLinus Torvalds { 32+4, 32+4, 32+4, 32+4, 32+4} /* IdSel 8, slot 2 */
2091da177e4SLinus Torvalds };
2101da177e4SLinus Torvalds long min_idsel = 0, max_idsel = 8, irqs_per_slot = 5;
2111da177e4SLinus Torvalds return COMMON_TABLE_LOOKUP;
2121da177e4SLinus Torvalds }
2131da177e4SLinus Torvalds #endif /* defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_SABLE) */
2141da177e4SLinus Torvalds
2151da177e4SLinus Torvalds /***********************************************************************/
2161da177e4SLinus Torvalds /* GENERIC irq routines */
2171da177e4SLinus Torvalds
2181da177e4SLinus Torvalds static inline void
sable_lynx_enable_irq(struct irq_data * d)219c90c10c8SThomas Gleixner sable_lynx_enable_irq(struct irq_data *d)
2201da177e4SLinus Torvalds {
2211da177e4SLinus Torvalds unsigned long bit, mask;
2221da177e4SLinus Torvalds
223c90c10c8SThomas Gleixner bit = sable_lynx_irq_swizzle->irq_to_mask[d->irq];
2241da177e4SLinus Torvalds spin_lock(&sable_lynx_irq_lock);
2251da177e4SLinus Torvalds mask = sable_lynx_irq_swizzle->shadow_mask &= ~(1UL << bit);
2261da177e4SLinus Torvalds sable_lynx_irq_swizzle->update_irq_hw(bit, mask);
2271da177e4SLinus Torvalds spin_unlock(&sable_lynx_irq_lock);
2281da177e4SLinus Torvalds #if 0
2295f0e3da6SRandy Dunlap printk("%s: mask 0x%lx bit 0x%lx irq 0x%x\n",
230bbb8d343SHarvey Harrison __func__, mask, bit, irq);
2311da177e4SLinus Torvalds #endif
2321da177e4SLinus Torvalds }
2331da177e4SLinus Torvalds
2341da177e4SLinus Torvalds static void
sable_lynx_disable_irq(struct irq_data * d)235c90c10c8SThomas Gleixner sable_lynx_disable_irq(struct irq_data *d)
2361da177e4SLinus Torvalds {
2371da177e4SLinus Torvalds unsigned long bit, mask;
2381da177e4SLinus Torvalds
239c90c10c8SThomas Gleixner bit = sable_lynx_irq_swizzle->irq_to_mask[d->irq];
2401da177e4SLinus Torvalds spin_lock(&sable_lynx_irq_lock);
2411da177e4SLinus Torvalds mask = sable_lynx_irq_swizzle->shadow_mask |= 1UL << bit;
2421da177e4SLinus Torvalds sable_lynx_irq_swizzle->update_irq_hw(bit, mask);
2431da177e4SLinus Torvalds spin_unlock(&sable_lynx_irq_lock);
2441da177e4SLinus Torvalds #if 0
2455f0e3da6SRandy Dunlap printk("%s: mask 0x%lx bit 0x%lx irq 0x%x\n",
246bbb8d343SHarvey Harrison __func__, mask, bit, irq);
2471da177e4SLinus Torvalds #endif
2481da177e4SLinus Torvalds }
2491da177e4SLinus Torvalds
2501da177e4SLinus Torvalds static void
sable_lynx_mask_and_ack_irq(struct irq_data * d)251c90c10c8SThomas Gleixner sable_lynx_mask_and_ack_irq(struct irq_data *d)
2521da177e4SLinus Torvalds {
2531da177e4SLinus Torvalds unsigned long bit, mask;
2541da177e4SLinus Torvalds
255c90c10c8SThomas Gleixner bit = sable_lynx_irq_swizzle->irq_to_mask[d->irq];
2561da177e4SLinus Torvalds spin_lock(&sable_lynx_irq_lock);
2571da177e4SLinus Torvalds mask = sable_lynx_irq_swizzle->shadow_mask |= 1UL << bit;
2581da177e4SLinus Torvalds sable_lynx_irq_swizzle->update_irq_hw(bit, mask);
2591da177e4SLinus Torvalds sable_lynx_irq_swizzle->ack_irq_hw(bit);
2601da177e4SLinus Torvalds spin_unlock(&sable_lynx_irq_lock);
2611da177e4SLinus Torvalds }
2621da177e4SLinus Torvalds
26344377f62SThomas Gleixner static struct irq_chip sable_lynx_irq_type = {
2648ab1221cSThomas Gleixner .name = "SABLE/LYNX",
265c90c10c8SThomas Gleixner .irq_unmask = sable_lynx_enable_irq,
266c90c10c8SThomas Gleixner .irq_mask = sable_lynx_disable_irq,
267c90c10c8SThomas Gleixner .irq_mask_ack = sable_lynx_mask_and_ack_irq,
2681da177e4SLinus Torvalds };
2691da177e4SLinus Torvalds
2701da177e4SLinus Torvalds static void
sable_lynx_srm_device_interrupt(unsigned long vector)2717ca56053SAl Viro sable_lynx_srm_device_interrupt(unsigned long vector)
2721da177e4SLinus Torvalds {
2731da177e4SLinus Torvalds /* Note that the vector reported by the SRM PALcode corresponds
2741da177e4SLinus Torvalds to the interrupt mask bits, but we have to manage via the
2751da177e4SLinus Torvalds so-called legacy IRQs for many common devices. */
2761da177e4SLinus Torvalds
2771da177e4SLinus Torvalds int bit, irq;
2781da177e4SLinus Torvalds
2791da177e4SLinus Torvalds bit = (vector - 0x800) >> 4;
2801da177e4SLinus Torvalds irq = sable_lynx_irq_swizzle->mask_to_irq[bit];
2811da177e4SLinus Torvalds #if 0
2821da177e4SLinus Torvalds printk("%s: vector 0x%lx bit 0x%x irq 0x%x\n",
283bbb8d343SHarvey Harrison __func__, vector, bit, irq);
2841da177e4SLinus Torvalds #endif
2853dbb8c62SAl Viro handle_irq(irq);
2861da177e4SLinus Torvalds }
2871da177e4SLinus Torvalds
2881da177e4SLinus Torvalds static void __init
sable_lynx_init_irq(int nr_of_irqs)2894b1135a2SThomas Gleixner sable_lynx_init_irq(int nr_of_irqs)
2901da177e4SLinus Torvalds {
2911da177e4SLinus Torvalds long i;
2921da177e4SLinus Torvalds
2934b1135a2SThomas Gleixner for (i = 0; i < nr_of_irqs; ++i) {
294a9eb076bSThomas Gleixner irq_set_chip_and_handler(i, &sable_lynx_irq_type,
2957d209c81SKyle McMartin handle_level_irq);
296c90c10c8SThomas Gleixner irq_set_status_flags(i, IRQ_LEVEL);
2971da177e4SLinus Torvalds }
2981da177e4SLinus Torvalds
2991da177e4SLinus Torvalds common_init_isa_dma();
3001da177e4SLinus Torvalds }
3011da177e4SLinus Torvalds
3021da177e4SLinus Torvalds static void __init
sable_lynx_init_pci(void)3031da177e4SLinus Torvalds sable_lynx_init_pci(void)
3041da177e4SLinus Torvalds {
3051da177e4SLinus Torvalds common_init_pci();
3061da177e4SLinus Torvalds }
3071da177e4SLinus Torvalds
3081da177e4SLinus Torvalds /*****************************************************************/
3091da177e4SLinus Torvalds /*
3101da177e4SLinus Torvalds * The System Vectors
3111da177e4SLinus Torvalds *
3121da177e4SLinus Torvalds * In order that T2_HAE_ADDRESS should be a constant, we play
3131da177e4SLinus Torvalds * these games with GAMMA_BIAS.
3141da177e4SLinus Torvalds */
3151da177e4SLinus Torvalds
316*d2b1e353SArnd Bergmann #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_SABLE)
3171da177e4SLinus Torvalds #undef GAMMA_BIAS
3181da177e4SLinus Torvalds #define GAMMA_BIAS _GAMMA_BIAS
3191da177e4SLinus Torvalds struct alpha_machine_vector sable_gamma_mv __initmv = {
3201da177e4SLinus Torvalds .vector_name = "Sable-Gamma",
3211da177e4SLinus Torvalds DO_EV5_MMU,
3221da177e4SLinus Torvalds DO_DEFAULT_RTC,
3231da177e4SLinus Torvalds DO_T2_IO,
3241da177e4SLinus Torvalds .machine_check = t2_machine_check,
3251da177e4SLinus Torvalds .max_isa_dma_address = ALPHA_SABLE_MAX_ISA_DMA_ADDRESS,
3261da177e4SLinus Torvalds .min_io_address = EISA_DEFAULT_IO_BASE,
3271da177e4SLinus Torvalds .min_mem_address = T2_DEFAULT_MEM_BASE,
3281da177e4SLinus Torvalds
3291da177e4SLinus Torvalds .nr_irqs = 40,
3301da177e4SLinus Torvalds .device_interrupt = sable_lynx_srm_device_interrupt,
3311da177e4SLinus Torvalds
3321da177e4SLinus Torvalds .init_arch = t2_init_arch,
3331da177e4SLinus Torvalds .init_irq = sable_init_irq,
3341da177e4SLinus Torvalds .init_rtc = common_init_rtc,
3351da177e4SLinus Torvalds .init_pci = sable_lynx_init_pci,
3361da177e4SLinus Torvalds .kill_arch = t2_kill_arch,
3371da177e4SLinus Torvalds .pci_map_irq = sable_map_irq,
3381da177e4SLinus Torvalds .pci_swizzle = common_swizzle,
3391da177e4SLinus Torvalds
3401da177e4SLinus Torvalds .sys = { .t2 = {
3411da177e4SLinus Torvalds .gamma_bias = _GAMMA_BIAS
3421da177e4SLinus Torvalds } }
3431da177e4SLinus Torvalds };
3441da177e4SLinus Torvalds ALIAS_MV(sable_gamma)
345*d2b1e353SArnd Bergmann #endif /* GENERIC || SABLE */
346