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/linux/Documentation/devicetree/bindings/reset/
H A Dbrcm,bcm6345-reset.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/brcm,bcm6345-reset.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: BCM6345 reset controller
9 description: This document describes the BCM6345 reset controller.
12 - Álvaro Fernández Rojas <noltari@gmail.com>
16 const: brcm,bcm6345-reset
21 "#reset-cells":
25 - compatible
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/linux/arch/mips/boot/dts/brcm/
H A Dbcm63268.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include "dt-bindings/clock/bcm63268-clock.h"
4 #include "dt-bindings/reset/bcm63268-reset.h"
5 #include "dt-bindings/soc/bcm63268-pm.h"
8 #address-cells = <1>;
9 #size-cells = <1>;
13 #address-cells = <1>;
14 #size-cells = <0>;
16 mips-hpt-frequency = <200000000>;
32 periph_osc: periph-osc {
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H A Dbcm6362.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include "dt-bindings/clock/bcm6362-clock.h"
4 #include "dt-bindings/reset/bcm6362-reset.h"
5 #include "dt-bindings/soc/bcm6362-pm.h"
8 #address-cells = <1>;
9 #size-cells = <1>;
13 #address-cells = <1>;
14 #size-cells = <0>;
16 mips-hpt-frequency = <200000000>;
32 periph_osc: periph-osc {
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H A Dbcm6328.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include "dt-bindings/clock/bcm6328-clock.h"
4 #include "dt-bindings/reset/bcm6328-reset.h"
5 #include "dt-bindings/soc/bcm6328-pm.h"
8 #address-cells = <1>;
9 #size-cells = <1>;
13 #address-cells = <1>;
14 #size-cells = <0>;
16 mips-hpt-frequency = <160000000>;
32 periph_osc: periph-osc {
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/linux/drivers/reset/
H A Dreset-bcm6345.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * BCM6345 Reset Controller Driver
13 #include <linux/reset-controller.h>
38 spin_lock_irqsave(&bcm6345_reset->lock, flags); in bcm6345_reset_update()
39 val = __raw_readl(bcm6345_reset->base); in bcm6345_reset_update()
44 __raw_writel(val, bcm6345_reset->base); in bcm6345_reset_update()
45 spin_unlock_irqrestore(&bcm6345_reset->lock, flags); in bcm6345_reset_update()
71 * Ensure component is taken out reset state by sleeping also after in bcm6345_reset_reset()
72 * deasserting the reset. Otherwise, the component may not be ready in bcm6345_reset_reset()
86 return !(__raw_readl(bcm6345_reset->base) & BIT(id)); in bcm6345_reset_status()
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
6 bool "Reset Controller Support"
9 Generic Reset Controller support.
11 This framework is designed to abstract reset handling of devices
12 via GPIOs or SoC-internal reset controller modules.
19 tristate "Altera Arria10 System Resource Reset"
22 This option enables support for the external reset functions for
26 bool "AR71xx Reset Driver" if COMPILE_TEST
29 This enables the ATH79 reset controller driver that supports the
30 AR71xx SoC reset controller.
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H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-y += core.o
3 obj-y += amlogic/
4 obj-y += hisilicon/
5 obj-y += starfive/
6 obj-y += sti/
7 obj-y += tegra/
8 obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o
9 obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
10 obj-$(CONFIG_RESET_AXS10X) += reset-axs10x.o
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/linux/arch/arm/boot/dts/broadcom/
H A Dbcm63138.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 interrupt-parent = <&gic>;
22 #address-cells = <1>;
23 #size-cells = <0>;
27 compatible = "arm,cortex-a9";
28 next-level-cache = <&L2>;
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/linux/drivers/tty/serial/
H A Dbcm63xx_uart.c1 // SPDX-License-Identifier: GPL-2.0
37 * - rx fifo full
38 * - rx fifo above threshold
39 * - rx fifo not empty for too long
53 * - tx fifo empty
54 * - tx fifo below threshold
76 return __raw_readl(port->membase + offset); in bcm_uart_readl()
82 __raw_writel(value, port->membase + offset); in bcm_uart_writel()
221 return (port->type == PORT_BCM63XX) ? "bcm63xx_uart" : NULL; in bcm_uart_type()
229 struct tty_port *tty_port = &port->state->port; in bcm_uart_do_rx()
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/linux/arch/mips/include/asm/mach-bcm63xx/
H A Dbcm63xx_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
90 /* BCM6345 clock bits are shifted by 16 on the left, because of the test
91 * control register which is 16-bits wide. That way we do not have any
92 * specific BCM6345 code for handling clocks, and writing 0 to the test
269 /* Soft Reset register */
460 /* Watchdog reset length register */
463 /* Watchdog soft reset register (BCM6328 only) */
996 /* Endpoint<->DMA mappings */
1003 /* Misc per-endpoint settings */
1267 #define SPI_6348_CMD 0x00 /* 16-bits register */
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