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/freebsd/sys/dev/qat/qat_common/
H A Dadf_freebsd_transport_debug.c1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2022 Intel Corporation */
21 struct adf_etr_bank_data *bank = ring->bank; in adf_ring_show() local
22 struct adf_hw_csr_ops *csr_ops = GET_CSR_OPS(bank->accel_dev); in adf_ring_show()
23 struct resource *csr = ring->bank->csr_addr; in adf_ring_show()
32 head = csr_ops->read_csr_ring_head(csr, in adf_ring_show()
33 bank->bank_number, in adf_ring_show()
34 ring->ring_number); in adf_ring_show()
35 tail = csr_ops->read_csr_ring_tail(csr, in adf_ring_show()
36 bank->bank_number, in adf_ring_show()
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/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DRegisterBankEmitter.cpp1 //===- RegisterBankEmitter.cpp - Generate a Register Bank Desc. -*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 // register bank for a code generator.
12 //===----------------------------------------------------------------------===//
23 #define DEBUG_TYPE "register-bank-emitter"
30 /// A vector of register classes that are included in the register bank.
36 /// The register classes that are covered by the register bank.
46 /// Get the human-readable name for the bank.
47 StringRef getName() const { return TheDef.getValueAsString("Name"); } in getName()
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/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dpinctrl-st.txt3 Each multi-function pin is controlled, driven and routed through the
5 and multiple alternate functions(ALT1 - ALTx) that directly connect
14 GPIO bank can have one of the two possible types of interrupt-wirings.
20 | |----> [gpio-bank (n) ]
21 | |----> [gpio-bank (n + 1)]
22 [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
23 | |----> [gpio-bank (... )]
24 |_________|----> [gpio-bank (n + 7)]
26 Second type has a dedicated interrupt per gpio bank.
28 [irqN]----> [gpio-bank (n)]
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H A Datmel,at91-pinctrl.txt10 Please refer to pinctrl-bindings.txt in this directory for details of the
18 such as pull-up, multi drive, etc.
21 - compatible: "atmel,at91rm9200-pinctrl" or "atmel,at91sam9x5-pinctrl"
22 or "atmel,sama5d3-pinctrl" or "microchip,sam9x60-pinctrl"
23 - atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be
24 configured in this periph mode. All the periph and bank need to be describe.
29 Each line will represent a pio bank
33 Bank: 3 (A, B and C)
41 For each peripheral/bank we will describe in a u32 if a pin can be
45 From the datasheet Table 10-2.
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H A Dallwinner,sun4i-a10-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/allwinner,sun4i-a10-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Che
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H A Dsamsung,pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Sylweste
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H A Dst,stm32-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/st,stm32-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schema
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H A Dsamsung-pinctrl.txt6 on-chip controllers onto these pads.
9 - compatible: should be one of the following.
10 - "samsung,s3c2412-pinctrl": for S3C2412-compatible pin-controller,
11 - "samsung,s3c2416-pinctrl": for S3C2416-compatible pin-controller,
12 - "samsung,s3c2440-pinctrl": for S3C2440-compatible pin-controller,
13 - "samsung,s3c2450-pinctrl": for S3C2450-compatible pin-controller,
14 - "samsung,s3c64xx-pinctrl": for S3C64xx-compatible pin-controller,
15 - "samsung,s5pv210-pinctrl": for S5PV210-compatible pin-controller,
16 - "samsung,exynos3250-pinctrl": for Exynos3250 compatible pin-controller.
17 - "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller.
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H A Dpinctrl-sirf.txt4 - compatible : "sirf,prima2-pinctrl"
5 - reg : Address range of the pinctrl registers
6 - interrupts : Interrupts used by every GPIO group
7 - gpio-controller : Indicates this device is a GPIO controller
8 - interrupt-controller : Marks the device node as an interrupt controller
10 - sirf,pullups : if n-th bit of m-th bank is set, set a pullup on GPIO-n of bank m
11 - sirf,pulldowns : if n-th bit of m-th bank is set, set a pulldown on GPIO-n of bank m
13 Please refer to pinctrl-bindings.txt in this directory for details of the common
19 Required subnode-properties:
20 - sirf,pins : An array of strings. Each string contains the name of a group.
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DRegisterBank.h1 //==-- llvm/CodeGen/RegisterBank.h - Register Bank ------
31 const char *Name; global() variable
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/freebsd/sys/contrib/device-tree/src/arm64/st/
H A Dstm32mp251.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
6 #include <dt-bindings/interrupt-controlle
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/freebsd/sys/arm/broadcom/bcm2835/
H A Dbcm2835_gpio.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
5 * Copyright (c) 2012-2015 Luiz Otavio O Souza <loos@FreeBSD.org>
94 { SYS_RES_IRQ, 0, RF_ACTIVE }, /* bank 0 interrupt */
95 { SYS_RES_IRQ, 1, RF_ACTIVE }, /* bank 1 interrupt */
96 { -1, 0, 0 }
135 #define BCM_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx)
136 #define BCM_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx)
137 #define BCM_GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
139 bus_space_write_4((_sc)->sc_bst, (_sc)->sc_bsh, _off, _val)
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/freebsd/sys/arm/allwinner/
H A Daw_gpio.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
210 {"allwinner,sun4i-a10-pinctrl", (uintptr_t)&a10_gpio_conf},
213 {"allwinner,sun5i-a13-pinctrl", (uintptr_t)&a13_gpio_conf},
216 {"allwinner,sun7i-a20-pinctrl", (uintptr_t)&a20_gpio_conf},
219 {"allwinner,sun6i-a31-pinctrl", (uintptr_t)&a31_gpio_conf},
222 {"allwinner,sun6i-a31s-pinctrl", (uintptr_t)&a31s_gpio_conf},
225 {"allwinner,sun6i-a31-r-pinctrl", (uintptr_t)&a31_r_gpio_conf},
228 {"allwinner,sun6i-a33-pinctrl", (uintptr_t)&a33_gpio_conf},
231 {"allwinner,sun8i-a83t-pinctrl", (uintptr_t)&a83t_gpio_conf},
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/freebsd/sys/contrib/device-tree/Bindings/mtd/
H A Dmtd-physmap.txt1 CFI or JEDEC memory-mapped NOR flash, MTD-RAM (NVRAM...)
6 - compatible : should contain the specific model of mtd chip(s)
7 used, if known, followed by either "cfi-flash", "jedec-flash",
8 "mtd-ram" or "mtd-rom".
9 - reg : Address range(s) of the mtd chip(s)
11 non-identical chips can be described in one node.
12 - bank-width : Width (in bytes) of the bank. Equal to the
14 - device-width : (optional) Width of a single mtd chip. If
15 omitted, assumed to be equal to 'bank-width'.
16 - #address-cells, #size-cells : Must be present if the device has
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H A Dmtd-physmap.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mtd/mtd-physmap.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: CFI or JEDEC memory-mapped NOR flash, MTD-RAM (NVRAM...)
10 - Rob Herring <robh@kernel.org>
17 - $ref: mtd.yaml#
18 - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
23 - items:
24 - enum:
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/freebsd/sys/contrib/device-tree/src/arm/st/
H A Dstm32f7-pinctrl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
7 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
8 #include <dt-bindings/mfd/stm32f7-rc
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H A Dstih407-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "st-pincfg.h"
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 /* 0-5: PIO_SBC */
18 /* 10-19: PIO_FRONT0 */
31 /* 30-35: PIO_REAR */
38 /* 40-42: PIO_FLASH */
45 pin-controller-sbc@961f080 {
46 #address-cells = <1>;
47 #size-cells = <1>;
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/freebsd/sys/contrib/device-tree/src/arm64/amlogic/
H A Dmeson-gxbb-odroidc2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "meson-gxbb.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/sound/meson-aiu.h>
15 compatible = "hardkernel,odroid-c2", "amlogic,meson-gxb
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H A Dmeson-gxl-s805x-libretech-ac.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/sound/meson-aiu.h>
13 #include "meson-gxl-s805x.dtsi"
16 compatible = "libretech,aml-s805
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H A Dmeson-gxl-s905x-libretech-cc.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/sound/meson-aiu.h>
13 #include "meson-gxl-s905x.dtsi"
16 compatible = "libretech,aml-s905
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DRegisterBank.cpp1 //===- llvm/CodeGen/GlobalISel/RegisterBank.cpp - Register Bank --*- C++ -*-==//
5 // SPDX-License-Identifie
25 RegisterBank(unsigned ID,const char * Name,const uint32_t * CoveredClasses,unsigned NumRegClasses) RegisterBank() argument
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/freebsd/sys/contrib/device-tree/Bindings/gpio/
H A Dgpio.txt5 -----------------
7 GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
8 of this GPIO for the device. While a non-existent <name> is considered valid
10 for new bindings. Also, GPIO properties named "[<name>-]gpio" are valid and old
17 meaningful name. The only case where an array of GPIOs is accepted is when
24 and bit-banged data signals:
27 gpio-controller;
28 #gpio-cells = <2>;
32 data-gpios = <&gpio1 12 0>,
44 recommended to use the two-cell approach.
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/freebsd/sys/x86/x86/
H A Dmca.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
71 * State maintained for each monitored MCx bank to control the
100 static int mca_banks; /* Number of per-CPU register banks. */
101 static int mca_maxcount = -1; /* Limit on records stored. (-1 = unlimited) */
138 mca_ia32_ctl_reg(int bank) in mca_ia32_ctl_reg() argument
140 return (MSR_MC_CTL(bank)); in mca_ia32_ctl_reg()
144 mca_ia32_status_reg(int bank) in mca_ia32_status_reg() argument
146 return (MSR_MC_STATUS(bank)); in mca_ia32_status_reg()
150 mca_ia32_addr_reg(int bank) in mca_ia32_addr_reg() argument
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/freebsd/sys/powerpc/powermac/
H A Dhrowpicvar.h1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
14 * 3. The name of the author may not be used to endorse or promote products
36 #define HROWPIC_IRQ_MASK ((HROWPIC_IRQMAX-1) >> 1) /* irq bit pos in word */
39 * Register offsets within bank. There are two identical banks,
40 * separated by 16 bytes. Interrupts 0->31 are processed in the
41 * second bank, and 32->63 in the first bank.
48 #define HPIC_PRIMARY 1 /* primary register bank */
49 #define HPIC_SECONDARY 0 /* secondary register bank */
52 * Convert an interrupt into a prim/sec bank number
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/freebsd/sys/contrib/device-tree/src/arm/amlogic/
H A Dmeson8b-odroidc1.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
12 model = "Hardkernel ODROID-C1";
13 compatible = "hardkernel,odroid-c1", "amlogic,meson8b";
22 stdout-path = "serial0:115200n8";
30 emmc_pwrseq: emmc-pwrseq {
31 compatible = "mmc-pwrseq-emmc";
32 reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
36 compatible = "gpio-leds";
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