1 //===- RegisterBankEmitter.cpp - Generate a Register Bank Desc. -*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 // register bank for a code generator.
12 //===----------------------------------------------------------------------===//
23 #define DEBUG_TYPE "register-bank-emitter"
30   /// A vector of register classes that are included in the register bank.
36   /// The register classes that are covered by the register bank.
46   /// Get the human-readable name for the bank.
47   StringRef getName() const { return TheDef.getValueAsString("Name"); }  in getName()
48   /// Get the name of the enumerator in the ID enumeration.
53   /// Get the name of the array holding the register class coverage data;
58   /// Get the name of the global instance variable.
73   /// Add a register class to the bank without duplicates.
88       else if (RCsWithLargestRegSize[M]->RSI.get(M).SpillSize <  in addRegisterClass()
89                RC->RSI.get(M).SpillSize)  in addRegisterClass()
139   for (const auto &Bank : Banks)  in emitHeader()  local
140     OS << "  " << Bank.getEnumeratorName() << " = " << ID++ << ",\n";  in emitHeader()
159 /// Visit each register class belonging to the given register bank.
161 /// A class belongs to the bank iff any of these apply:
165 ///   is a member. This is known as a subreg-class.
192     if (RC != &PossibleSubclass && RC->hasSubClass(&PossibleSubclass))  in visitRegisterBankClasses()
194                                TmpKind + " " + RC->getName() + " subclass",  in visitRegisterBankClasses()
198     // subregister-index.  in visitRegisterBankClasses()
200     // More precisely, PossibleSubclass is a subreg-class iff Reg:SubIdx is in  in visitRegisterBankClasses()
202     // subregister-index SubReg  in visitRegisterBankClasses()
206       if (BV.test(RC->EnumValue)) {  in visitRegisterBankClasses()
207         std::string TmpKind2 = (Twine(TmpKind) + " " + RC->getName() +  in visitRegisterBankClasses()
208                                 " class-with-subregs: " + RC->getName())  in visitRegisterBankClasses()
223   for (const auto &Bank : Banks) {  in emitBaseClassImplementation()  local
227     for (const auto &RC : Bank.register_classes())  in emitBaseClassImplementation()
228       RCsGroupedByWord[RC->EnumValue / 32].push_back(RC);  in emitBaseClassImplementation()
230     OS << "const uint32_t " << Bank.getCoverageArrayName() << "[] = {\n";  in emitBaseClassImplementation()
233       OS << "    // " << LowestIdxInWord << "-" << (LowestIdxInWord + 31)  in emitBaseClassImplementation()
236         OS << "    (1u << (" << RC->getQualifiedIdName() << " - "  in emitBaseClassImplementation()
246   for (const auto &Bank : Banks) {  in emitBaseClassImplementation()  local
248         (TargetName + "::" + Bank.getEnumeratorName()).str();  in emitBaseClassImplementation()
249     OS << "constexpr RegisterBank " << Bank.getInstanceVarName() << "(/* ID */ "  in emitBaseClassImplementation()
250        << QualifiedBankID << ", /* Name */ \"" << Bank.getName() << "\", "  in emitBaseClassImplementation()
251        << "/* CoveredRegClasses */ " << Bank.getCoverageArrayName()  in emitBaseClassImplementation()
260   for (const auto &Bank : Banks)  in emitBaseClassImplementation()  local
261     OS << "    &" << TargetName << "::" << Bank.getInstanceVarName() << ",\n";  in emitBaseClassImplementation()
271       OS << CGH.getMode(M).Name;  in emitBaseClassImplementation()
273     for (const auto &Bank : Banks) {  in emitBaseClassImplementation()  local
274       const CodeGenRegisterClass &RC = *Bank.getRCWithLargestRegSize(M);  in emitBaseClassImplementation()
288      << "    assert(RB.index() == RB.value()->getID() && \"Index != ID\");\n"  in emitBaseClassImplementation()
303     RegisterBank Bank(*V, CGH.getNumModeIds());  in run()  local
306          Bank.getExplicitlySpecifiedRegisterClasses(RegisterClassHierarchy)) {  in run()
309           [&Bank](const CodeGenRegisterClass *RC, StringRef Kind) {  in run()
311                        << "Added " << RC->getName() << "(" << Kind << ")\n");  in run()
312             Bank.addRegisterClass(RC);  in run()
317     Banks.push_back(Bank);  in run()
320   // Warn about ambiguous MIR caused by register bank/class name clashes.  in run()
323     for (const auto &Bank : Banks) {  in run()  local
324       if (Bank.getName().lower() == StringRef(Class.getName()).lower()) {  in run()
325         PrintWarning(Bank.getDef().getLoc(), "Register bank names should be "  in run()
328         PrintNote(Bank.getDef().getLoc(), "RegisterBank was declared here");  in run()
329         PrintNote(Class.getDef()->getLoc(), "RegisterClass was declared here");  in run()
335   emitSourceFileHeader("Register Bank Source Fragments", OS);  in run()
351     X("gen-register-bank", "Generate registers bank descriptions");