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/linux/tools/perf/pmu-events/arch/x86/graniterapids/
H A D	frontend.json	7 …"PublicDescription": "Number of times the front-end is resteered when it finds a branch instructio… 16 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length … 29 "BriefDescription": "DSB-to-MITE switch true penalty cycles.", 33 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou… 57 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", 69 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th… 110 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", 117 …r an interval where the front-end delivered no uops for a period of at least 1 cycle which was not… 122 …fter an interval where the front-end delivered no uops for a period of 128 cycles which was not in… 129 …fter an interval where the front-end delivered no uops for a period of 128 cycles which was not in… [all …]
/linux/tools/perf/pmu-events/arch/x86/sapphirerapids/
H A D	frontend.json	7 …"PublicDescription": "Number of times the front-end is resteered when it finds a branch instructio… 16 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length … 29 "BriefDescription": "DSB-to-MITE switch true penalty cycles.", 33 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou… 45 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", 57 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th… 98 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", 105 …r an interval where the front-end delivered no uops for a period of at least 1 cycle which was not… 110 …fter an interval where the front-end delivered no uops for a period of 128 cycles which was not in… 117 …fter an interval where the front-end delivered no uops for a period of 128 cycles which was not in… [all …]
/linux/tools/perf/pmu-events/arch/x86/emeraldrapids/
H A D	frontend.json	7 …"PublicDescription": "Number of times the front-end is resteered when it finds a branch instructio… 16 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length … 29 "BriefDescription": "DSB-to-MITE switch true penalty cycles.", 33 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou… 45 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", 57 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th… 98 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", 105 …r an interval where the front-end delivered no uops for a period of at least 1 cycle which was not… 110 …fter an interval where the front-end delivered no uops for a period of 128 cycles which was not in… 117 …fter an interval where the front-end delivered no uops for a period of 128 cycles which was not in… [all …]
/linux/tools/perf/pmu-events/arch/x86/alderlake/
H A D	frontend.json	17 …"PublicDescription": "Number of times the front-end is resteered when it finds a branch instructio… 27 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length … 42 "BriefDescription": "DSB-to-MITE switch true penalty cycles.", 46 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou… 59 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", 72 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th… 117 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", 124 …r an interval where the front-end delivered no uops for a period of at least 1 cycle which was not… 130 …fter an interval where the front-end delivered no uops for a period of 128 cycles which was not in… 137 …fter an interval where the front-end delivered no uops for a period of 128 cycles which was not in… [all …]
/linux/tools/perf/pmu-events/arch/x86/meteorlake/
H A D	frontend.json	17 …"PublicDescription": "Number of times the front-end is resteered when it finds a branch instructio… 27 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length … 42 "BriefDescription": "DSB-to-MITE switch true penalty cycles.", 46 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou… 72 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", 85 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th… 139 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", 146 …r an interval where the front-end delivered no uops for a period of at least 1 cycle which was not… 152 …fter an interval where the front-end delivered no uops for a period of 128 cycles which was not in… 159 …fter an interval where the front-end delivered no uops for a period of 128 cycles which was not in… [all …]
/linux/tools/perf/pmu-events/arch/x86/rocketlake/
H A D	frontend.json	3 …t end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected … 7 …"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch… 16 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length … 21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.", 27 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe… 32 "BriefDescription": "DSB-to-MITE switch true penalty cycles.", 36 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou… 48 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", 60 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th… 101 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", [all …]
/linux/tools/perf/pmu-events/arch/x86/icelakex/
H A D	frontend.json	3 …t end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected … 7 …"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch… 16 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length … 21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.", 27 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe… 32 "BriefDescription": "DSB-to-MITE switch true penalty cycles.", 36 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou… 48 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", 60 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th… 101 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", [all …]
/linux/tools/perf/pmu-events/arch/x86/tigerlake/
H A D	frontend.json	3 …t end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected … 7 …"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch… 16 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length … 21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.", 27 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe… 32 "BriefDescription": "DSB-to-MITE switch true penalty cycles.", 36 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou… 48 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", 60 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th… 101 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", [all …]
/linux/tools/perf/pmu-events/arch/x86/icelake/
H A D	frontend.json	3 …t end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected … 7 …"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch… 16 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length … 21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.", 27 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe… 32 "BriefDescription": "DSB-to-MITE switch true penalty cycles.", 36 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou… 48 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", 60 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th… 101 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", [all …]
/linux/include/uapi/linux/media/raspberrypi/
H A D	pisp_be_config.h	1 /* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note / 3 PiSP Back End configuration definitions. 5 * Copyright (C) 2021 - Raspberry Pi Ltd 97 * struct pisp_be_global_config - PiSP global enable bitmaps 111 * struct pisp_be_input_buffer_config - PiSP Back End input buffer 120 * struct pisp_be_dpc_config - PiSP Back End DPC config 138 * struct pisp_be_geq_config - PiSP Back End GEQ config 150 #define PISP_BE_GEQ_SLOPE ((1 << 10) - 1) 158 * struct pisp_be_tdn_input_buffer_config - PiSP Back End TDN input buffer 167 * struct pisp_be_tdn_config - PiSP Back End TDN config [all …]
/linux/tools/perf/pmu-events/arch/x86/skylake/
H A D	frontend.json	3 …t end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected … 7 …"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch… 16 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length … 21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", 25 …e Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Strea… 30 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 34 …-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of th… 46 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", 58 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th… 97 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", [all …]
/linux/tools/perf/pmu-events/arch/x86/cascadelakex/
H A D	frontend.json	3 …t end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected … 7 …"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch… 16 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length … 21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", 25 …e Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Strea… 30 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 34 …-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of th… 46 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", 58 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th… 97 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", [all …]
/linux/tools/perf/pmu-events/arch/x86/skylakex/
H A D	frontend.json	3 …t end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected … 7 …"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch… 16 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length … 21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", 25 …e Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Strea… 30 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 34 …-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of th… 46 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", 58 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th… 97 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", [all …]
/linux/tools/perf/pmu-events/arch/x86/goldmontplus/
H A D	pipeline.json	229 "BriefDescription": "Instructions retired - using Reduced Skid PEBS feature", 250 …ocation is stalled waiting for a mispredicted jump to retire or other branch-like conditions (e.g.… 259 …ource in the backend. Including but not limited to resources such as the Re-order Buffer (ROB), r… 335 …r of times that the machines clears due to a page fault. Covers both I-side and D-side(Loads/Store… 340 "BriefDescription": "Self-Modifying Code detected", 344 …ction and has to perform a machine clear because of that modification. Self-modifying code (SMC) … 349 "BriefDescription": "Uops issued to the back end per cycle", 353 …end and allocated into the back end of the machine. This event counts uops that retire as well as… 357 "BriefDescription": "Uops requested but not-delivered to the back-end per cycle", 361 …-end inefficiencies. I.e. when front-end of the machine is not delivering uops to the back-end and… [all …]
/linux/tools/perf/pmu-events/arch/x86/goldmont/
H A D	pipeline.json	240 …ocation is stalled waiting for a mispredicted jump to retire or other branch-like conditions (e.g.… 249 …ource in the backend. Including but not limited to resources such as the Re-order Buffer (ROB), r… 321 "BriefDescription": "Self-Modifying Code detected", 325 …ction and has to perform a machine clear because of that modification. Self-modifying code (SMC) … 330 "BriefDescription": "Uops issued to the back end per cycle", 334 …end and allocated into the back end of the machine. This event counts uops that retire as well as… 338 "BriefDescription": "Uops requested but not-delivered to the back-end per cycle", 342 …-end inefficiencies. I.e. when front-end of the machine is not delivering uops to the back-end and… 370 …ued by the micro-sequencer (MS). Counts both the uops from a micro-coded instruction, and the uop…
/linux/sound/soc/fsl/
H A D	fsl_asrc_dma.c	1 // SPDX-License-Identifier: GPL-2.0 9 #include <linux/dma-mapping.h> 11 #include <linux/dma/imx-dma.h> 37 chan->private = param; in filter() 45 struct snd_pcm_runtime runtime = substream->runtime; in fsl_asrc_dma_complete() 46 struct fsl_asrc_pair pair = runtime->private_data; in fsl_asrc_dma_complete() 48 pair->pos += snd_pcm_lib_period_bytes(substream); in fsl_asrc_dma_complete() 49 if (pair->pos >= snd_pcm_lib_buffer_bytes(substream)) in fsl_asrc_dma_complete() 50 pair->pos = 0; in fsl_asrc_dma_complete() 58 u8 dir = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? OUT : IN; in fsl_asrc_dma_prepare_and_submit() [all …]
/linux/drivers/media/i2c/
H A D	ccs-pll.h	`1 /* SPDX-License-Identifier: GPL-2.0-only / 3 drivers/media/i2c/ccs-pll.h 17 /* CSI-2 or CCP-2 / 37 struct ccs_pll_branch_fr - CCS PLL configuration (front) 39 * A single branch front-end of the CCS PLL tree. 41 * @pre_pll_clk_div: Pre-PLL clock divisor 54 * struct ccs_pll_branch_bk - CCS PLL configuration (back) 56 * A single branch back-end of the CCS PLL tree. 71 * struct ccs_pll - Full CCS PLL configuration 78 * @csi2: CSI-2 related parameters [all …]`
/linux/fs/erofs/
H A D	namei.c	1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (C) 2017-2018 HUAWEI, Inc. 12 const unsigned char end; member 15 / based on the end of qn is accurate and it must have the trailing '\0' / 23 on-disk error, let's only BUG_ON in the debugging mode. in erofs_dirnamecmp() 27 DBG_BUGON(qd->name > qd->end); in erofs_dirnamecmp() 30 /* However it is absolutely safe if < qd->end */ in erofs_dirnamecmp() 31 while (qd->name + i < qd->end && qd->name[i] != '\0') { in erofs_dirnamecmp() 32 if (qn->name[i] != qd->name[i]) { in erofs_dirnamecmp() 34 return qn->name[i] > qd->name[i] ? 1 : -1; in erofs_dirnamecmp() [all …]
/linux/Documentation/userspace-api/media/v4l/
H A D	metafmt-pisp-be.rst	1 .. SPDX-License-Identifier: GPL-2.0 3 .. _v4l2-meta-fmt-rpi-be-cfg: 9 Raspberry Pi PiSP Back End configuration format 12 The Raspberry Pi PiSP Back End memory-to-memory image signal processor is 14 to the `pispbe-config` output video device node using the 17 The PiSP Back End processes images in tiles, and its configuration requires 22 <https://datasheets.raspberrypi.com/camera/raspberry-pi-image-signal-processor-specification.pdf>`_ 23 provide detailed description of the ISP back end configuration and programming 27 ------------------------- 38 --------------- [all …]
/linux/Documentation/admin-guide/media/
H A D	raspberrypi-pisp-be.rst	1 .. SPDX-License-Identifier: GPL-2.0 4 Raspberry Pi PiSP Back End Memory-to-Memory ISP (pisp-be) 7 The PiSP Back End 10 The PiSP Back End is a memory-to-memory Image Signal Processor (ISP) which reads 13 pixel data back to memory through two distinct output channels. 18 The PiSP Back End ISP processes images in tiles. The handling of image 19 tessellation and the computation of low-level configuration parameters is 24 an image sensor through a MIPI CSI-2 compatible capture interface, storing them 25 in DRAM memory and processing them in the PiSP Back End to obtain images usable 29 The pisp-be driver [all …]
/linux/lib/lz4/
H A D	lz4hc_compress.c	2 * LZ4 HC - High Compression Mode of LZ4 3 * Copyright (C) 2011-2015, Yann Collet. 5 * BSD 2 - Clause License (http://www.opensource.org/licenses/bsd - license.php) 27 * - LZ4 homepage : http://www.lz4.org 28 * - LZ4 source repository : https://github.com/lz4/lz4 31 * Sven Schmidt <4sschmid@informatik.uni-hamburg.de> 34 /-*********************************** 47 #define OPTIMAL_ML (int)((ML_MASK - 1) + MINMATCH) 50 >> ((MINMATCH8) - LZ4HC_HASH_LOG)) 63 memset((void )hc4->hashTable, 0, sizeof(hc4->hashTable)); in LZ4HC_init() [all …]
/linux/arch/sh/mm/
H A D	cache-sh2a.c	1 // SPDX-License-Identifier: GPL-2.0-only 3 * arch/sh/mm/cache-sh2a.c 47 * Write back the dirty D-caches, but not invalidate them. 53 unsigned long begin, end; in sh2a__flush_wback_region() local 57 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1); in sh2a__flush_wback_region() 58 end = ((unsigned long)start + size + L1_CACHE_BYTES-1) in sh2a__flush_wback_region() 59 & ~(L1_CACHE_BYTES-1); in sh2a__flush_wback_region() 66 if (((end - begin) >> PAGE_SHIFT) >= MAX_OCACHE_PAGES) { in sh2a__flush_wback_region() 68 end = begin + (nr_ways * current_cpu_data.dcache.way_size); in sh2a__flush_wback_region() 70 for (v = begin; v < end; v += L1_CACHE_BYTES) { in sh2a__flush_wback_region() [all …]
H A D	flush-sh4.c	1 // SPDX-License-Identifier: GPL-2.0 9 * Write back the dirty D-caches, but not invalidate them. 16 reg_size_t aligned_start, v, cnt, end; in sh4__flush_wback_region() local 19 v = aligned_start & ~(L1_CACHE_BYTES-1); in sh4__flush_wback_region() 20 end = (aligned_start + size + L1_CACHE_BYTES-1) in sh4__flush_wback_region() 21 & ~(L1_CACHE_BYTES-1); in sh4__flush_wback_region() 22 cnt = (end - v) / L1_CACHE_BYTES; in sh4__flush_wback_region() 33 cnt -= 8; in sh4__flush_wback_region() 38 cnt--; in sh4__flush_wback_region() 43 * Write back the dirty D-caches and invalidate them. [all …]
/linux/tools/perf/pmu-events/arch/x86/lunarlake/
H A D	frontend.json	`12 …s line or being redirected by a jump and the instruction cache registers bytes are not present. -", 21 … were no operation was delivered to the back-end pipeline due to instruction fetch limitations whe… 25 …back-end pipeline due to instruction fetch limitations when the back-end could have accepted more …`
/linux/arch/arm/mm/
H A D	cache-fa.S	`1 /* SPDX-License-Identifier: GPL-2.0-only / 3 linux/arch/arm/mm/cache-fa.S 6 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> 8 * Based on cache-v4wb.S: 9 * Copyright (C) 1997-2002 Russell king 19 #include "proc-macros.S" 76 * flush_user_cache_range(start, end, flags) 81 * - start - start address (inclusive, page aligned) 82 * - end - end address (exclusive, page aligned) 83 * - flags - vma_area_struct flags describing address space [all …]`

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