Lines Matching +full:back +full:- +full:end

7 …"PublicDescription": "Number of times the front-end is resteered when it finds a branch instructio…
16 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
29         "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
33 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou…
57 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
69 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th…
110         "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
117 …r an interval where the front-end delivered no uops for a period of at least 1 cycle which was not…
122 …fter an interval where the front-end delivered no uops for a period of 128 cycles which was not in…
129 …fter an interval where the front-end delivered no uops for a period of 128 cycles which was not in…
134 …fter an interval where the front-end delivered no uops for a period of 16 cycles which was not int…
141 …tions that are delivered to the back-end after a front-end stall of at least 16 cycles. During thi…
146         "BriefDescription": "Retired instructions after front-end starvation of at least 2 cycles",
153 … an interval where the front-end delivered no uops for a period of at least 2 cycles which was not…
158 …fter an interval where the front-end delivered no uops for a period of 256 cycles which was not in…
165 …fter an interval where the front-end delivered no uops for a period of 256 cycles which was not in…
170 … an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not…
177 …e delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycle…
182 …fter an interval where the front-end delivered no uops for a period of 32 cycles which was not int…
189 …tions that are delivered to the back-end after a front-end stall of at least 32 cycles. During thi…
194 …after an interval where the front-end delivered no uops for a period of 4 cycles which was not int…
201 …after an interval where the front-end delivered no uops for a period of 4 cycles which was not int…
206 …fter an interval where the front-end delivered no uops for a period of 512 cycles which was not in…
213 …fter an interval where the front-end delivered no uops for a period of 512 cycles which was not in…
218 …fter an interval where the front-end delivered no uops for a period of 64 cycles which was not int…
225 …fter an interval where the front-end delivered no uops for a period of 64 cycles which was not int…
230 …after an interval where the front-end delivered no uops for a period of 8 cycles which was not int…
237 …ctions that are delivered to the back-end after a front-end stall of at least 8 cycles. During thi…
242         "BriefDescription": "I-Cache miss too close to Code Prefetch Instruction",
249 …tion": "Number of Instruction Cache demand miss in shadow of an on-going i-fetch cache-line trigge…
416 … when no operation was delivered to the back-end pipeline due to instruction fetch limitations whe…
420 …back-end pipeline due to instruction fetch limitations when the back-end could have accepted more …
430 …vered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back…
435 …ion": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not s…
441 …vered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back…
450 …ed to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back…
460 …vered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back…
465 …ion": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not s…
471 …vered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back…