Lines Matching +full:back +full:- +full:end

3 …t end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected …
7 …"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch…
16 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
21         "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
25 …e Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Strea…
30         "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
34 …-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of th…
46 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
58 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th…
97         "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
104 …r an interval where the front-end delivered no uops for a period of at least 1 cycle which was not…
109 …fter an interval where the front-end delivered no uops for a period of 128 cycles which was not in…
120 …fter an interval where the front-end delivered no uops for a period of 16 cycles which was not int…
127 …tions that are delivered to the back-end after a front-end stall of at least 16 cycles. During thi…
132 …after an interval where the front-end delivered no uops for a period of 2 cycles which was not int…
143 …fter an interval where the front-end delivered no uops for a period of 256 cycles which was not in…
154 … an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not…
161 …e delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycle…
166 … an interval where the front-end had at least 2 bubble-slots for a period of 2 cycles which was no…
177 … an interval where the front-end had at least 3 bubble-slots for a period of 2 cycles which was no…
188 …fter an interval where the front-end delivered no uops for a period of 32 cycles which was not int…
195 …tions that are delivered to the back-end after a front-end stall of at least 32 cycles. During thi…
200 …after an interval where the front-end delivered no uops for a period of 4 cycles which was not int…
211 …fter an interval where the front-end delivered no uops for a period of 512 cycles which was not in…
222 …fter an interval where the front-end delivered no uops for a period of 64 cycles which was not int…
233 …after an interval where the front-end delivered no uops for a period of 8 cycles which was not int…
240 …ctions that are delivered to the back-end after a front-end stall of at least 8 cycles. During thi…
266 …etch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity…
274 …tch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity…
449 …) (where x belongs to {0,1,2,3}). Counting does not cover cases when: a. IDQ-Resource Allocation T…
459 …"PublicDescription": "Counts, on the per-thread basis, cycles when no uops are delivered to Resour…
479 …"PublicDescription": "Counts, on the per-thread basis, cycles when less than 1 uop is delivered to…
484         "BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
489         "PublicDescription": "Cycles with less than 2 uops delivered by the front-end.",
494         "BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
499         "PublicDescription": "Cycles with less than 3 uops delivered by the front-end.",