Lines Matching +full:back +full:- +full:end

3 …t end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected …
7 …"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch…
16 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
21         "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.",
27 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe…
32         "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
36 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou…
48 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
60 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th…
101         "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
108 …r an interval where the front-end delivered no uops for a period of at least 1 cycle which was not…
113 …fter an interval where the front-end delivered no uops for a period of 128 cycles which was not in…
120 …fter an interval where the front-end delivered no uops for a period of 128 cycles which was not in…
125 …fter an interval where the front-end delivered no uops for a period of 16 cycles which was not int…
132 …tions that are delivered to the back-end after a front-end stall of at least 16 cycles. During thi…
137         "BriefDescription": "Retired instructions after front-end starvation of at least 2 cycles",
144 … an interval where the front-end delivered no uops for a period of at least 2 cycles which was not…
149 …fter an interval where the front-end delivered no uops for a period of 256 cycles which was not in…
156 …fter an interval where the front-end delivered no uops for a period of 256 cycles which was not in…
161 … an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not…
168 …e delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycle…
173 …fter an interval where the front-end delivered no uops for a period of 32 cycles which was not int…
180 …tions that are delivered to the back-end after a front-end stall of at least 32 cycles. During thi…
185 …after an interval where the front-end delivered no uops for a period of 4 cycles which was not int…
192 …after an interval where the front-end delivered no uops for a period of 4 cycles which was not int…
197 …fter an interval where the front-end delivered no uops for a period of 512 cycles which was not in…
204 …fter an interval where the front-end delivered no uops for a period of 512 cycles which was not in…
209 …fter an interval where the front-end delivered no uops for a period of 64 cycles which was not int…
216 …fter an interval where the front-end delivered no uops for a period of 64 cycles which was not int…
221 …after an interval where the front-end delivered no uops for a period of 8 cycles which was not int…
228 …ctions that are delivered to the back-end after a front-end stall of at least 8 cycles. During thi…
254 …etch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity…
258 …etch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity…
263 …tch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity…
267 …tch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity…
381 …ed to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back…
391 …vered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back…
396 …ion": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not s…
402 …vered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back…