| /freebsd/sys/contrib/alpine-hal/ |
| H A D | al_hal_udma_regs_s2m.h | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
77 /* [0x24] AXI outstanding read configuration */
79 /* [0x28] AXI outstanding write configuration */
86 * 00 - No pending tasks
100 * 0 - Log is enable
101 * 1 - Log is masked.
131 /* [0x30] S2M AXI data FIFO status */
190 * [0x8] Counting the net length of the data buffers [64-bit]
195 * [0xc] Counting the net length of the data buffers [64-bit]
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| H A D | al_hal_udma_regs_m2s.h | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
77 /* [0x24] AXI outstanding configuration */
84 * 00 - No pending tasks
98 * 0 - Log is enabled.
99 * 1 - Log is masked.
213 * 0 - Rate limit is active.
214 * 1 - Rate limit is masked.
235 /* [0x4] Counting number of descriptors with First-bit set. */
238 * [0x8] Counting the net length of the data buffers [64-bit]
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| H A D | al_hal_udma_iofic.h | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
56 /* *INDENT-OFF* */
60 /* *INDENT-ON* */
69 AL_IOFIC_MODE_LEGACY, /**< level-sensitive interrupt wire */
70 AL_IOFIC_MODE_MSIX_PER_Q, /**< per UDMA queue MSI-X interrupt */
82 * interrupt controller of each bus-master unit in the I/O Fabric.
164 /** AXI data buffer parity error */
208 * Prefetch AXI timeout
213 * Prefetch AXI response
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| H A D | al_hal_pcie.c | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
72 /** RC - Revisions 1/2 */
77 /** EP - Revisions 1/2 */
82 /** RC - Revision 3 */
87 /** EP - Revision 3 */
96 #define AL_PCIE_PARSE_LANES(v) (((1 << v) - 1) << \
113 al_reg_write32(&pcie_port->regs->port_regs->rd_only_wr_en, in al_pcie_port_wr_to_ro_set()
131 (pcie_port->rev_id == AL_PCIE_REV_ID_3) ? 0x4000 : 0x1000; in al_reg_write32_dbi_cs2()
154 struct al_pcie_regs *regs = pcie_port->regs; in al_pcie_port_link_speed_ctrl_set()
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| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | xlnx,axi-ethernet.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/xlnx,axi-ethernet.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: AXI 1G/2.5G Ethernet Subsystem
10 Also called AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core
16 Management configuration is done through the AXI interface, while payload is
17 sent and received through means of an AXI DMA controller. This driver
18 includes the DMA driver code, so this driver is incompatible with AXI DMA
22 - Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
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| H A D | xilinx_axienet.txt | 1 XILINX AXI ETHERNET Device Tree Bindings
2 --------------------------------------------------------
4 Also called AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core
10 Management configuration is done through the AXI interface, while payload is
11 sent and received through means of an AXI DMA controller. This driver
12 includes the DMA driver code, so this driver is incompatible with AXI DMA
18 - compatible : Must be one of "xlnx,axi-ethernet-1.00.a",
19 "xlnx,axi-ethernet-1.01.a", "xlnx,axi-ethernet-2.01.a"
20 - reg : Address and length of the IO space, as well as the address
21 and length of the AXI DMA controller IO space, unless
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| /freebsd/sys/contrib/device-tree/Bindings/display/imx/ |
| H A D | fsl-imx-drm.txt | 8 - compatible: Should be "fsl,imx-display-subsystem"
9 - ports: Should contain a list of phandles pointing to display interface ports
14 display-subsystem {
15 compatible = "fsl,imx-display-subsystem";
24 - compatible: Should be "fsl,<chip>-ipu" where <chip> is one of
25 - imx51
26 - imx53
27 - imx6q
28 - imx6qp
29 - reg: should be register base and length as documented in the
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| H A D | nxp,imx8mq-dcss.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/imx/nxp,imx8mq-dcss.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Laurentiu Palcu <laurentiu.palcu@nxp.com>
17 2.2) or MIPI-DSI. The DCSS is intended to support up to 4kp60 displays. HDR10
23 const: nxp,imx8mq-dcss
27 - description: DCSS base address and size, up to IRQ steer start
28 - description: DCSS BLKCTL base address and size
32 - description: Context loader completion and error interrupt
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| /freebsd/sys/contrib/device-tree/Bindings/fpga/ |
| H A D | xilinx-pr-decoupler.txt | 10 Xilinx LogiCORE Dynamic Function eXchange(DFX) AXI shutdown manager
11 Softcore is compatible with the Xilinx LogiCORE pr-decoupler.
13 The Dynamic Function eXchange AXI shutdown manager prevents AXI traffic
15 and AXI4-Lite interfaces on a Reconfigurable Partition when it is
17 that can occur if AXI transactions are interrupted by DFX
24 - compatible : Should contain "xlnx,pr-decoupler-1.00" followed by
25 "xlnx,pr-decoupler" or
26 "xlnx,dfx-axi-shutdown-manager-1.00" followed by
27 "xlnx,dfx-axi-shutdown-manager"
28 - regs : base address and size for decoupler module
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| /freebsd/sys/contrib/device-tree/Bindings/net/can/ |
| H A D | xilinx_can.txt | 1 Xilinx Axi CAN/Zynq CANPS controller Device Tree Bindings
2 ---------------------------------------------------------
5 - compatible : Should be:
6 - "xlnx,zynq-can-1.0" for Zynq CAN controllers
7 - "xlnx,axi-can-1.00.a" for Axi CAN controllers
8 - "xlnx,canfd-1.0" for CAN FD controllers
9 - "xlnx,canfd-2.0" for CAN FD 2.0 controllers
10 - reg : Physical base address and size of the controller
12 - interrupts : Property with a value describing the interrupt
14 - clock-names : List of input clock names
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| /freebsd/sys/contrib/device-tree/Bindings/pci/ |
| H A D | rockchip,rk3399-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip AXI PCIe Root Port Bridge Host
10 - Shawn Lin <shawn.lin@rock-chips.com>
13 - $ref: /schemas/pci/pci-host-bridge.yaml#
14 - $ref: rockchip,rk3399-pcie-common.yaml#
18 const: rockchip,rk3399-pcie
22 reg-names:
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| H A D | rockchip-pcie-host.txt | 1 * Rockchip AXI PCIe Root Port Bridge DT description
4 - #address-cells: Address representation for root ports, set to <3>
5 - #size-cells: Size representation for root ports, set to <2>
6 - #interrupt-cells: specifies the number of cells needed to encode an
8 - compatible: Should contain "rockchip,rk3399-pcie"
9 - reg: Two register ranges as listed in the reg-names property
10 - reg-names: Must include the following names
11 - "axi-base"
12 - "apb-base"
13 - clocks: Must contain an entry for each entry in clock-names.
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| H A D | brcm,iproc-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/brcm,iproc-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ray Jui <ray.jui@broadcom.com>
11 - Scott Branden <scott.branden@broadcom.com>
14 - $ref: /schemas/pci/pci-host-bridge.yaml#
19 - enum:
22 - brcm,iproc-pcie
23 # for the second generation of PAXB-based controllers, used in
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| H A D | brcm,iproc-pcie.txt | 4 - compatible:
5 "brcm,iproc-pcie" for the first generation of PAXB based controller,
7 "brcm,iproc-pcie-paxb-v2" for the second generation of PAXB-based
9 "brcm,iproc-pcie-paxc" for the first generation of PAXC based
11 "brcm,iproc-pcie-paxc-v2" for the second generation of PAXC based
13 PAXB-based root complex is used for external endpoint devices. PAXC-based
15 - reg: base address and length of the PCIe controller I/O register space
16 - #interrupt-cells: set to <1>
17 - interrupt-map-mask and interrupt-map, standard PCI properties to define the
19 - linux,pci-domain: PCI domain ID. Should be unique for each host controller
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/ata/ |
| H A D | ahci-mtk.txt | 4 - compatible : Must be "mediatek,<chip>-ahci", "mediatek,mtk-ahci".
5 When using "mediatek,mtk-ahci" compatible strings, you
7 - "mediatek,mt7622-ahci"
8 - reg : Physical base addresses and length of register sets.
9 - interrupts : Interrupt associated with the SATA device.
10 - interrupt-names : Associated name must be: "hostc".
11 - clocks : A list of phandle and clock specifier pairs, one for each
12 entry in clock-names.
13 - clock-names : Associated names must be: "ahb", "axi", "asic", "rbc", "pm".
14 - phys : A phandle and PHY specifier pair for the PHY port.
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/spi/ |
| H A D | adi,axi-spi-engine.txt | 1 Analog Devices AXI SPI Engine controller Device Tree Bindings
4 - compatible : Must be "adi,axi-spi-engine-1.00.a""
5 - reg : Physical base address and size of the register map.
6 - interrupts : Property with a value describing the interrupt
8 - clock-names : List of input clock names - "s_axi_aclk", "spi_clk"
9 - clocks : Clock phandles and specifiers (See clock bindings for
10 details on clock-names and clocks).
11 - #address-cells : Must be <1>
12 - #size-cells : Must be <0>
16 master. They follow the generic SPI bindings as outlined in spi-bus.txt.
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/media/ |
| H A D | fsl-pxp.txt | 4 The Pixel Pipeline (PXP) is a memory-to-memory graphics processing engine
10 - compatible: should be "fsl,<soc>-pxp", where SoC can be one of imx23, imx28,
12 - reg: the register base and size for the device registers
13 - interrupts: the PXP interrupt, two interrupts for imx6ull and imx7d.
14 - clock-names: should be "axi"
15 - clocks: the PXP AXI clock
20 compatible = "fsl,imx6ull-pxp";
24 clock-names = "axi";
|
| H A D | marvell,mmp2-ccic.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/media/marvell,mmp2-ccic.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Lubomir Rintel <lkundrak@v3.sk>
15 pattern: '^camera@[a-f0-9]+$'
18 const: marvell,mmp2-ccic
26 power-domains:
30 $ref: /schemas/graph.yaml#/$defs/port-base
35 $ref: video-interfaces.yaml#
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| H A D | nxp,imx-mipi-csi2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/nxp,imx-mipi-csi2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX7 and i.MX8 MIPI CSI-2 receiver
10 - Rui Miguel Silva <rmfrfs@gmail.com>
11 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
13 description: |-
14 The NXP i.MX7 and i.MX8 families contain SoCs that include a MIPI CSI-2
19 While the CSI-2 receiver is separate from the MIPI D-PHY IP core, the PHY is
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| H A D | nxp,imx7-mipi-csi2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/nxp,imx7-mipi-csi2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX7 and i.MX8 MIPI CSI-2 receiver
10 - Rui Miguel Silva <rmfrfs@gmail.com>
11 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
13 description: |-
14 The NXP i.MX7 and i.MX8 families contain SoCs that include a MIPI CSI-2
19 While the CSI-2 receiver is separate from the MIPI D-PHY IP core, the PHY is
[all …]
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| /freebsd/sys/dev/bhnd/bcma/ |
| H A D | bcma_eromreg.h | 1 /*-
2 * SPDX-License-Identifier: ISC
35 #define BCMA_EROM_TABLE_SIZE BCMA_EROM_REMAPCONTROL - BCMA_EROM_TABLE_START
77 #define BCMA_EROM_COREA_DESIGNER_MASK 0xFFF00000 /* core designer (JEP-106 mfg id) */
79 #define BCMA_EROM_COREA_ID_MASK 0x000FFF00 /* broadcom-assigned core id */
93 #define BCMA_EROM_COREB_REV_MASK 0xFF000000 /* broadcom-assigned core revision */
99 * on the AXI bus and PL301 interconnect, but are undocumented
102 #define BCMA_EROM_MPORT_NUM_MASK 0x0000FF00 /* AXI master number (unique per interconnect) */
104 #define BCMA_EROM_MPORT_ID_MASK 0x000000F0 /* AXI master ID (unique per master). */
108 #define BCMA_EROM_REGION_BASE_MASK 0xFFFFF000 /* region base address */
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| /freebsd/sys/contrib/device-tree/Bindings/serial/ |
| H A D | xlnx,opb-uartlite.txt | 1 Xilinx Axi Uartlite controller Device Tree Bindings
2 ---------------------------------------------------------
5 - compatible : Can be either of
6 "xlnx,xps-uartlite-1.00.a"
7 "xlnx,opb-uartlite-1.00.b"
8 - reg : Physical base address and size of the Axi Uartlite
10 - interrupts : Should contain the UART controller interrupt.
13 - port-number : Set Uart port number
14 - clock-names : Should be "s_axi_aclk"
15 - clocks : Input clock specifier. Refer to common clock bindings.
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/watchdog/ |
| H A D | of-xilinx-wdt.txt | 1 Xilinx AXI/PLB soft-core watchdog Device Tree Bindings
2 ---------------------------------------------------------
5 - compatible : Should be "xlnx,xps-timebase-wdt-1.00.a" or
6 "xlnx,xps-timebase-wdt-1.01.a".
7 - reg : Physical base address and size
10 - clocks : Input clock specifier. Refer to common clock
12 - clock-frequency : Frequency of clock in Hz
13 - xlnx,wdt-enable-once : 0 - Watchdog can be restarted
14 1 - Watchdog can be enabled just once
15 - xlnx,wdt-interval : Watchdog timeout interval in 2^<val> clock cycles,
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/bus/ |
| H A D | nvidia,tegra210-aconnect.txt | 3 The Tegra ACONNECT bus is an AXI switch which is used to connnect various
5 the APE subsystem go through the ACONNECT via an APB to AXI wrapper.
8 - compatible: Must be "nvidia,tegra210-aconnect".
9 - clocks: Must contain the entries for the APE clock (TEGRA210_CLK_APE),
11 - clock-names: Must contain the names "ape" and "apb2ape" for the corresponding
13 - power-domains: Must contain a phandle that points to the audio powergate
15 - #address-cells: The number of cells used to represent physical base addresses
17 - #size-cells: The number of cells used to represent the size of an address
19 - ranges: Mapping of the aconnect address space to the CPU address space.
21 All devices accessed via the ACONNNECT are described by child-nodes.
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| /freebsd/sys/contrib/device-tree/Bindings/display/rockchip/ |
| H A D | rockchip-vop.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip-vop.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Sandy Huang <hjc@rock-chip
[all...] |