1*c66ec88fSEmmanuel VadotFreescale Pixel Pipeline 2*c66ec88fSEmmanuel Vadot======================== 3*c66ec88fSEmmanuel Vadot 4*c66ec88fSEmmanuel VadotThe Pixel Pipeline (PXP) is a memory-to-memory graphics processing engine 5*c66ec88fSEmmanuel Vadotthat supports scaling, colorspace conversion, alpha blending, rotation, and 6*c66ec88fSEmmanuel Vadotpixel conversion via lookup table. Different versions are present on various 7*c66ec88fSEmmanuel Vadoti.MX SoCs from i.MX23 to i.MX7. 8*c66ec88fSEmmanuel Vadot 9*c66ec88fSEmmanuel VadotRequired properties: 10*c66ec88fSEmmanuel Vadot- compatible: should be "fsl,<soc>-pxp", where SoC can be one of imx23, imx28, 11*c66ec88fSEmmanuel Vadot imx6dl, imx6sl, imx6sll, imx6ul, imx6sx, imx6ull, or imx7d. 12*c66ec88fSEmmanuel Vadot- reg: the register base and size for the device registers 13*c66ec88fSEmmanuel Vadot- interrupts: the PXP interrupt, two interrupts for imx6ull and imx7d. 14*c66ec88fSEmmanuel Vadot- clock-names: should be "axi" 15*c66ec88fSEmmanuel Vadot- clocks: the PXP AXI clock 16*c66ec88fSEmmanuel Vadot 17*c66ec88fSEmmanuel VadotExample: 18*c66ec88fSEmmanuel Vadot 19*c66ec88fSEmmanuel Vadotpxp@21cc000 { 20*c66ec88fSEmmanuel Vadot compatible = "fsl,imx6ull-pxp"; 21*c66ec88fSEmmanuel Vadot reg = <0x021cc000 0x4000>; 22*c66ec88fSEmmanuel Vadot interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 23*c66ec88fSEmmanuel Vadot <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 24*c66ec88fSEmmanuel Vadot clock-names = "axi"; 25*c66ec88fSEmmanuel Vadot clocks = <&clks IMX6UL_CLK_PXP>; 26*c66ec88fSEmmanuel Vadot}; 27