Lines Matching +full:axi +full:- +full:base
1 Xilinx Axi Uartlite controller Device Tree Bindings
2 ---------------------------------------------------------
5 - compatible : Can be either of
6 "xlnx,xps-uartlite-1.00.a"
7 "xlnx,opb-uartlite-1.00.b"
8 - reg : Physical base address and size of the Axi Uartlite
10 - interrupts : Should contain the UART controller interrupt.
13 - port-number : Set Uart port number
14 - clock-names : Should be "s_axi_aclk"
15 - clocks : Input clock specifier. Refer to common clock bindings.
19 compatible = "xlnx,xps-uartlite-1.00.a";
22 port-number = <0>;