Lines Matching +full:axi +full:- +full:base
1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
56 /* *INDENT-OFF* */
60 /* *INDENT-ON* */
69 AL_IOFIC_MODE_LEGACY, /**< level-sensitive interrupt wire */
70 AL_IOFIC_MODE_MSIX_PER_Q, /**< per UDMA queue MSI-X interrupt */
82 * interrupt controller of each bus-master unit in the I/O Fabric.
164 /** AXI data buffer parity error */
208 * Prefetch AXI timeout
213 * Prefetch AXI response
218 * Prefetch AXI parity
223 * Data AXI timeout
228 * Data AXI response
233 * Data AXI parity
238 * Completion AXI timeout
243 * Completion AXI response
248 * Completion AXI parity
286 /** PRE-UNACK packets buffer parity error */
351 * Completion AXI timeout
356 * Completion AXI response
361 * Completion AXI parity
381 * Prefetch AXI timeout
386 * Prefetch AXI response
391 * Prefetch AXI parity
439 * Data AXI timeout
444 * Data AXI response
449 * Data AXI parity
464 * interrupt and MSIX modes. The m2s/s2m errors/abort are a set of bit-wise
468 * The bit-mask that the _errors_disable and _aborts_disable are described in
472 * @param mode interrupt scheme mode (legacy, MSI-X..)
474 * This is a bit-wise mask, to indicate which one of the error causes in
479 * This is a bit-wise mask, to indicate which one of the error causes in
484 * This is a bit-wise mask, to indicate which one of the error causes in
489 * This is a bit-wise mask, to indicate which one of the error causes in
494 * @return 0 on success. -EINVAL otherwise.
518 * Get the interrupt controller base address for either the primary or secondary
524 * @returns The interrupt controller base address
532 (void __iomem *)®s->gen.interrupt_regs.main_iofic : in al_udma_iofic_reg_base_get()
533 (void __iomem *)®s->gen.interrupt_regs.secondary_iofic_ctrl; in al_udma_iofic_reg_base_get()
544 * @returns 0 - invalid, 1 - valid