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/linux/Documentation/devicetree/bindings/serial/
H A Dserial-peripheral-props.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/serial/serial-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Common Properties for Serial-attached Devices
10 - Rob Herring <robh@kernel.org>
11 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
15 controller, might need similar properties, e.g. for configuring the baud
19 max-speed:
22 The maximum baud rate the device operates at.
[all …]
/linux/drivers/net/hamradio/
H A Dz8530.h1 /* SPDX-License-Identifier: GPL-2.0 */
61 #define AUTO_ENAB 0x20 /* Auto Enables */
91 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
100 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
102 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
145 /* Write Register 12 (lower byte of baud rate generator time constant) */
147 /* Write Register 13 (upper byte of baud rate generator time constant) */
150 #define BRENABL 1 /* Baud rate generator enable */
151 #define BRSRC 2 /* Baud rate generator source */
153 #define AUTOECHO 8 /* Auto Echo */
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/linux/drivers/tty/serial/
H A Dmxs-auart.c1 // SPDX-License-Identifier: GPL-2.0+
9 * Copyright 2014 Oleksij Rempel <linux@rempel-privat.de>
11 * Copyright 2008-2010 Freescale Semiconductor, Inc.
34 #include <linux/dma-mapping.h>
90 #define AUART_LINECTRL_WLEN(v) ((((v) - 5) & 0x3) << 5)
138 * RW. Receive Timeout Counter Value: number of 8-bit-time to wait before
140 * input is idle, then the watchdog counter will decrement each bit-time. Note
141 * 7-bit-time is added to the programmed value, so a value of zero will set
142 * the counter to 7-bit-time, a value of 0x1 gives 15-bit-time and so on. Also
146 * value is 0x3 (31 bit-time).
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H A Dsuncore.c1 // SPDX-License-Identifier: GPL-2.0
32 drv->minor = sunserial_current_minor; in sunserial_register_minors()
33 drv->nr += count; in sunserial_register_minors()
35 if (drv->nr == count) in sunserial_register_minors()
39 drv->tty_driver->name_base = drv->minor - 64; in sunserial_register_minors()
47 drv->nr -= count; in sunserial_unregister_minors()
48 sunserial_current_minor -= count; in sunserial_unregister_minors()
50 if (drv->nr == 0) in sunserial_unregister_minors()
61 drv->cons = con; in sunserial_console_match()
78 con->index = line; in sunserial_console_match()
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H A Dmilbeaut_usio.c1 // SPDX-License-Identifier: GPL-2.0
15 #define USIO_NAME "mlb-usio-uart"
67 writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FTIE, in mlb_usio_stop_tx()
68 port->membase + MLB_USIO_REG_FCR); in mlb_usio_stop_tx()
69 writeb(readb(port->membase + MLB_USIO_REG_SCR) & ~MLB_USIO_SCR_TBIE, in mlb_usio_stop_tx()
70 port->membase + MLB_USIO_REG_SCR); in mlb_usio_stop_tx()
75 struct tty_port *tport = &port->state->port; in mlb_usio_tx_chars()
78 writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FTIE, in mlb_usio_tx_chars()
79 port->membase + MLB_USIO_REG_FCR); in mlb_usio_tx_chars()
80 writeb(readb(port->membase + MLB_USIO_REG_SCR) & in mlb_usio_tx_chars()
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H A Dip22zilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
32 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
94 #define AUTO_ENAB 0x20 /* Auto Enables */
126 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
136 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
138 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
181 /* Write Register 12 (lower byte of baud rate generator time constant) */
183 /* Write Register 13 (upper byte of baud rate generator time constant) */
186 #define BRENAB 1 /* Baud rate generator enable */
187 #define BRSRC 2 /* Baud rate generator source */
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H A Dma35d1_serial.c1 // SPDX-License-Identifier: GPL-2.0+
36 /* MA35_IER_REG - Interrupt Enable Register */
40 #define MA35_IER_RTO_IEN BIT(4) /* RX Time-out Interrupt Enable */
42 #define MA35_IER_TIME_OUT_EN BIT(11) /* RX Buffer Time-out Counter Enable */
43 #define MA35_IER_AUTO_RTS BIT(12) /* nRTS Auto-flow Control Enable */
44 #define MA35_IER_AUTO_CTS BIT(13) /* nCTS Auto-flow Control Enable */
46 /* MA35_FCR_REG - FIFO Control Register */
62 /* MA35_LCR_REG - Line Control Register */
74 /* MA35_MCR_REG - Modem Control Register */
79 /* MA35_MSR_REG - Modem Status Register */
[all …]
H A Dzs.h1 /* SPDX-License-Identifier: GPL-2.0 */
38 * Per-SCC state for locking and the interrupt handler.
53 #define ZS_BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
113 #define AUTO_ENAB 0x20 /* Auto Enables */
144 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
154 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
156 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
200 /* Write Register 12 (Lower Byte of Baud Rate Generator Time Constant) */
202 /* Write Register 13 (Upper Byte of Baud Rate Generator Time Constant) */
205 #define BRENABL 1 /* Baud rate generator enable */
[all …]
H A Dsunzilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
24 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
86 #define AUTO_ENAB 0x20 /* Auto Enables */
118 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
128 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
130 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
183 /* Write Register 12 (lower byte of baud rate generator time constant) */
185 /* Write Register 13 (upper byte of baud rate generator time constant) */
188 #define BRENAB 1 /* Baud rate generator enable */
189 #define BRSRC 2 /* Baud rate generator source */
[all …]
H A Dpmac_zilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
25 * of "escc" node (ie. ch-a or ch-b)
64 if (uap->flags & PMACZILOG_FLAG_IS_CHANNEL_A) in pmz_get_port_A()
66 return uap->mate; in pmz_get_port_A()
78 writeb(reg, port->control_reg); in read_zsreg()
79 return readb(port->control_reg); in read_zsreg()
85 writeb(reg, port->control_reg); in write_zsreg()
86 writeb(value, port->control_reg); in write_zsreg()
91 return readb(port->data_reg); in read_zsdata()
96 writeb(data, port->data_reg); in write_zsdata()
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H A Desp32_uart.c1 // SPDX-License-Identifier: GPL-2.0-or-later
19 #define DRIVER_NAME "esp32-uart"
128 .compatible = "esp,esp32-uart",
131 .compatible = "esp,esp32s3-uart",
141 return port->private_data; in port_variant()
146 writel(v, port->membase + reg); in esp32_uart_write()
151 return readl(port->membase + reg); in esp32_uart_read()
158 return (status & port_variant(port)->txfifo_cnt_mask) >> UART_TXFIFO_CNT_SHIFT; in esp32_uart_tx_fifo_cnt()
165 return (status & port_variant(port)->rxfifo_cnt_mask) >> UART_RXFIFO_CNT_SHIFT; in esp32_uart_rx_fifo_cnt()
216 struct tty_port *tty_port = &port->state->port; in esp32_uart_rxint()
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H A Dliteuart.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2019-2020 Antmicro <www.antmicro.com>
25 * The definitions below are true for LiteX SoC configured for 8-bit CSR Bus,
26 * 32-bit aligned.
76 uart->irq_reg |= mask; in liteuart_update_irq_reg()
78 uart->irq_reg &= ~mask; in liteuart_update_irq_reg()
80 if (port->irq) in liteuart_update_irq_reg()
81 litex_write8(port->membase + OFF_EV_ENABLE, uart->irq_reg); in liteuart_update_irq_reg()
99 del_timer(&uart->timer); in liteuart_stop_rx()
104 unsigned char __iomem *membase = port->membase; in liteuart_rx_chars()
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H A Dfsl_lpuart.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright 2012-2014 Freescale Semiconductor, Inc.
14 #include <linux/dma-mapping.h>
30 /* All registers are 8-bit width */
119 /* 32-bit global registers only for i.MX7ULP/i.MX8x
124 /* 32-bit register definition */
246 #define DRIVER_NAME "fsl-lpuart"
339 .rx_watermark = 7, /* A lower watermark is ideal for low baud rates. */
349 { .compatible = "fsl,vf610-lpuart", .data = &vf_data, },
350 { .compatible = "fsl,ls1021a-lpuart", .data = &ls1021a_data, },
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H A Dsc16is7xx.c1 // SPDX-License-Identifier: GPL-2.0+
3 * SC16IS7xx tty serial driver - common code
53 * - only on 75x/76x
56 * - only on 75x/76x
59 * - only on 75x/76x
62 * - only on 75x/76x
90 /* IER register bits - write only if (EFR[4] == 1) */
103 /* FCR register bits - write only if (EFR[4] == 1) */
113 #define SC16IS7XX_IIR_RTOI_SRC 0x0c /* RX time-out interrupt */
115 * - only on 75x/76x
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H A Dxilinx_uartps.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (c) 2011 - 2014 Xilinx, Inc.
7 * This driver has originally been pushed by Xilinx using a Zynq-branding. This
42 MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");
47 MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
56 #define CDNS_UART_BAUDGEN 0x18 /* Baud Rate Generator */
63 #define CDNS_UART_BAUDDIV 0x34 /* Baud Rate Divider */
90 #define CDNS_UART_MR_CLKSEL 0x00000001 /* Pre-scalar selection */
183 /* baud dividers min/max values */
190 * struct cdns_uart - device data
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H A Damba-pl011.c1 // SPDX-License-Identifier: GPL-2.0+
9 * Copyright (C) 2010 ST-Ericsson SA
11 * This is a generic driver for ARM AMBA-type serial ports. They
12 * have a lot of 16550-like features, but are not register compatible.
35 #include <linux/dma-mapping.h>
82 /* The size of the array - must be last */
261 unsigned int fifosize; /* vendor-specific */
262 unsigned int fixed_baud; /* vendor-set fixed baud rate */
282 return uap->reg_offset[reg]; in pl011_reg_to_offset()
288 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg); in pl011_read()
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H A Dpic32_uart.c1 // SPDX-License-Identifier: GPL-2.0+
8 * Sorin-Andrei Pistirica <andrei.pistirica@microchip.com>
26 #include <asm/mach-pic32/pic32.h>
29 #define PIC32_DEV_NAME "pic32-uart"
43 /* struct pic32_sport - pic32 serial port descriptor
82 __raw_writel(val, sport->port.membase + reg); in pic32_uart_writel()
87 return __raw_readl(sport->port.membase + reg); in pic32_uart_readl()
166 if (!sport->cts_gpiod) in pic32_uart_get_mctrl()
168 else if (gpiod_get_value(sport->cts_gpiod)) in pic32_uart_get_mctrl()
181 * the status of irq to control the irq-depth.
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H A Dserial_core.c1 // SPDX-License-Identifier: GPL-2.0+
8 * Copyright (C) 2000-2001 Deep Blue Solutions Ltd.
43 * lockdep: port->lock is initialized in two places, but we
44 * want only one lock-class:
48 #define HIGH_BITS_OFFSET ((sizeof(long)-sizeof(int))*8)
62 return !!(uport->status & UPSTAT_DCD_ENABLE); in uart_dcd_enabled()
67 if (atomic_add_unless(&state->refcount, 1, 0)) in uart_port_ref()
68 return state->uart_port; in uart_port_ref()
74 if (atomic_dec_and_test(&uport->state->refcount)) in uart_port_deref()
75 wake_up(&uport->state->remove_wait); in uart_port_deref()
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/linux/drivers/tty/serial/8250/
H A D8250_fintek.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2016 Ricardo Ribalda, Qtechnology A/S
105 outb(reg, pdata->base_port + ADDR_PORT); in sio_read_reg()
106 return inb(pdata->base_port + DATA_PORT); in sio_read_reg()
111 outb(reg, pdata->base_port + ADDR_PORT); in sio_write_reg()
112 outb(data, pdata->base_port + DATA_PORT); in sio_write_reg()
127 return -EBUSY; in fintek_8250_enter_key()
149 return -ENODEV; in fintek_8250_check_id()
152 return -ENODEV; in fintek_8250_check_id()
167 return -ENODEV; in fintek_8250_check_id()
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H A D8250_exar.c1 // SPDX-License-Identifier: GPL-2.0
3 * Probe module for 8250/16550-type Exar chips PCI serial ports.
106 #define UART_FCTR_EXAR_485 0x20 /* Auto 485 half duplex dir ctl */
112 #define UART_EXAR_TXTRG 0x0a /* Tx FIFO trigger level write-only */
113 #define UART_EXAR_RXTRG 0x0b /* Rx FIFO trigger level write-only */
131 #define UART_EXAR_DLD_485_POLARITY 0x80 /* RS-485 Enable Signal Polarity */
148 * ---- ---- --------
152 * 3 - <reserved>
156 * 7 - <reserved>
159 * 10 - Red LED
[all …]
H A D8250_port.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Base port operations for 8250/16550-type serial ports
244 * tx_loadsz is set to 63-bytes instead of 64-bytes to implement
245 * workaround of errata A-008006 which states that tx_loadsz should
257 .name = "Palmchip BK-3103",
344 offset = offset << p->regshift; in hub6_serial_in()
345 outb(p->hub6 - 1 + offset, p->iobase); in hub6_serial_in()
346 return inb(p->iobase + 1); in hub6_serial_in()
351 offset = offset << p->regshift; in hub6_serial_out()
352 outb(p->hub6 - 1 + offset, p->iobase); in hub6_serial_out()
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H A D8250_of.c1 // SPDX-License-Identifier: GPL-2.0+
50 static unsigned int npcm_get_divisor(struct uart_port *port, unsigned int baud, in npcm_get_divisor() argument
53 return DIV_ROUND_CLOSEST(port->uartclk, 16 * baud + 2) - 2; in npcm_get_divisor()
58 port->get_divisor = npcm_get_divisor; in npcm_setup()
59 port->startup = npcm_startup; in npcm_setup()
72 struct uart_8250_port *port8250 = serial8250_get_port(info->line); in of_platform_serial_clk_notifier_cb()
76 serial8250_update_uartclk(&port8250->port, ndata->new_rate); in of_platform_serial_clk_notifier_cb()
91 struct device *dev = &ofdev->dev; in of_platform_serial_setup()
92 struct device_node *np = dev->of_node; in of_platform_serial_setup()
93 struct uart_port *port = &up->port; in of_platform_serial_setup()
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/linux/arch/m68k/include/asm/
H A Dmcfuart.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * mcfuart.h -- ColdFire internal UART support defines.
7 * (C) Copyright 1999-2003, Greg Ungerer (gerg@snapgear.com)
39 #define MCFUART_UBG1 0x18 /* Baud Rate MSB (r/w) */
40 #define MCFUART_UBG2 0x1c /* Baud Rate LSB (r/w) */
59 #define MCFUART_MR1_RXRTS 0x80 /* Auto RTS flow control */
83 #define MCFUART_MR2_TXCTS 0x10 /* Auto CTS flow control */
/linux/drivers/media/dvb-frontends/
H A Dbcm3510_priv.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Copyright (C) 2001-5, B2C2 inc.
267 /* auto reacquire */
301 u8 PE :1; /* baud clock pin */
303 u8 BE :1; /* baud clock pin */
364 u8 ARI :1; /* auto reacquire */
/linux/include/soc/fsl/qe/
H A Dqe.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
35 QE_BRG1, /* Baud Rate Generator 1 */
36 QE_BRG2, /* Baud Rate Generator 2 */
37 QE_BRG3, /* Baud Rate Generator 3 */
38 QE_BRG4, /* Baud Rate Generator 4 */
39 QE_BRG5, /* Baud Rate Generator 5 */
40 QE_BRG6, /* Baud Rate Generator 6 */
41 QE_BRG7, /* Baud Rate Generator 7 */
42 QE_BRG8, /* Baud Rate Generator 8 */
43 QE_BRG9, /* Baud Rate Generator 9 */
[all …]

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