Lines Matching +full:auto +full:- +full:baud
1 // SPDX-License-Identifier: GPL-2.0
3 * Probe module for 8250/16550-type Exar chips PCI serial ports.
106 #define UART_FCTR_EXAR_485 0x20 /* Auto 485 half duplex dir ctl */
112 #define UART_EXAR_TXTRG 0x0a /* Tx FIFO trigger level write-only */
113 #define UART_EXAR_RXTRG 0x0b /* Rx FIFO trigger level write-only */
131 #define UART_EXAR_DLD_485_POLARITY 0x80 /* RS-485 Enable Signal Polarity */
148 * ---- ---- --------
152 * 3 - <reserved>
156 * 7 - <reserved>
159 * 10 - Red LED
160 * 11..15 - <unused>
237 * struct exar8250_board - board information
240 * @setup: quirk run at ->probe() stage for each port
241 * @exit: quirk run at ->remove() stage
263 writeb(value, priv->virt + reg); in exar_write_reg()
268 return readb(priv->virt + reg); in exar_read_reg()
273 struct exar8250 *priv = eeprom->data; in exar_eeprom_93cx6_reg_read()
277 eeprom->reg_data_out = regb & UART_EXAR_REGB_EEDO; in exar_eeprom_93cx6_reg_read()
282 struct exar8250 *priv = eeprom->data; in exar_eeprom_93cx6_reg_write()
285 if (eeprom->reg_data_in) in exar_eeprom_93cx6_reg_write()
287 if (eeprom->reg_data_clock) in exar_eeprom_93cx6_reg_write()
289 if (eeprom->reg_chip_select) in exar_eeprom_93cx6_reg_write()
297 priv->eeprom.data = priv; in exar_eeprom_init()
298 priv->eeprom.register_read = exar_eeprom_93cx6_reg_read; in exar_eeprom_init()
299 priv->eeprom.register_write = exar_eeprom_93cx6_reg_write; in exar_eeprom_init()
300 priv->eeprom.width = PCI_EEPROM_WIDTH_93C46; in exar_eeprom_init()
301 priv->eeprom.quirks |= PCI_EEPROM_QUIRK_EXTRA_READ_CYCLE; in exar_eeprom_init()
305 * exar_mpio_config_output() - Configure an Exar MPIO as an output
330 mpio_offset = mpio_num - 8; in exar_mpio_config_output()
332 return -EINVAL; in exar_mpio_config_output()
335 // Disable MPIO pin tri-state in exar_mpio_config_output()
348 * _exar_mpio_set() - Set an Exar MPIO output high or low
370 mpio_offset = mpio_num - 8; in _exar_mpio_set()
372 return -EINVAL; in _exar_mpio_set()
398 bool is_rs485 = !!(rs485->flags & SER_RS485_ENABLED); in generic_rs485_config()
399 u8 __iomem *p = port->membase; in generic_rs485_config()
433 * Calculate divisor with extra 4-bit fractional portion
435 static unsigned int xr17v35x_get_divisor(struct uart_port *p, unsigned int baud, in xr17v35x_get_divisor() argument
440 quot_16 = DIV_ROUND_CLOSEST(p->uartclk, baud); in xr17v35x_get_divisor()
446 static void xr17v35x_set_divisor(struct uart_port *p, unsigned int baud, in xr17v35x_set_divisor() argument
449 serial8250_do_set_divisor(p, baud, quot); in xr17v35x_set_divisor()
481 struct tty_port *tport = &port->state->port; in exar_shutdown()
492 } while (!kfifo_is_empty(&tport->xmit_fifo) && in exar_shutdown()
502 const struct exar8250_board *board = priv->board; in default_setup()
506 err = serial8250_pci_setup_port(pcidev, port, 0, offset, board->reg_shift); in default_setup()
517 status = readb(port->port.membase + UART_EXAR_DVID); in default_setup()
519 port->port.type = PORT_XR17V35X; in default_setup()
521 port->port.get_divisor = xr17v35x_get_divisor; in default_setup()
522 port->port.set_divisor = xr17v35x_set_divisor; in default_setup()
524 port->port.startup = xr17v35x_startup; in default_setup()
526 port->port.type = PORT_XR17D15X; in default_setup()
529 port->port.pm = exar_pm; in default_setup()
530 port->port.shutdown = exar_shutdown; in default_setup()
540 unsigned int baud = 1843200; in pci_fastcom335_setup() local
544 port->port.uartclk = baud * 16; in pci_fastcom335_setup()
550 p = port->port.membase; in pci_fastcom335_setup()
564 switch (pcidev->device) { in pci_fastcom335_setup()
588 * cti_tristate_disable() - Disable RS485 transciever tristate
593 * the RS422/RS485 transceiver does not drive a multi-drop RS485 bus when it is
597 * Some Exar UARTs have an auto-tristate feature while others require setting
614 * cti_plx_int_enable() - Enable UART interrupts to PLX bridge
618 * interrupts from the UART to the PLX PCI->PCIe bridge.
634 * cti_read_osc_freq() - Read the UART oscillator frequency from EEPROM
648 eeprom_93cx6_multiread(&priv->eeprom, eeprom_offset, ee_words, ARRAY_SIZE(ee_words)); in cti_read_osc_freq()
652 return -EIO; in cti_read_osc_freq()
658 * cti_get_port_type_xr17c15x_xr17v25x() - Get port type of xr17c15x/xr17v25x
671 switch (pcidev->subsystem_device) { in cti_get_port_type_xr17c15x_xr17v25x()
728 dev_err(&pcidev->dev, "unknown/unsupported device\n"); in cti_get_port_type_xr17c15x_xr17v25x()
734 * cti_get_port_type_fpga() - Get the port type of a CTI FPGA card
747 switch (pcidev->device) { in cti_get_port_type_fpga()
753 dev_err(&pcidev->dev, "unknown/unsupported device\n"); in cti_get_port_type_fpga()
759 * cti_get_port_type_xr17v35x() - Read port type from the EEPROM
778 eeprom_93cx6_read(&priv->eeprom, offset, &port_flags); in cti_get_port_type_xr17v35x()
791 dev_warn(&pcidev->dev, "failed to get port %d type from EEPROM\n", port_num); in cti_get_port_type_xr17v35x()
800 struct exar8250 *priv = (struct exar8250 *)port->private_data; in cti_rs485_config_mpio_tristate()
807 // Disable power-on RS485 tri-state via MPIO in cti_rs485_config_mpio_tristate()
808 return cti_tristate_disable(priv, port->port_id); in cti_rs485_config_mpio_tristate()
817 dev_warn(&pcidev->dev, "failed to read OSC freq from EEPROM, using default\n"); in cti_board_init_osc_freq()
821 priv->osc_freq = osc_freq; in cti_board_init_osc_freq()
831 port->port.port_id = idx; in cti_port_setup_common()
832 port->port.uartclk = priv->osc_freq; in cti_port_setup_common()
838 port->port.private_data = (void *)priv; in cti_port_setup_common()
839 port->port.pm = exar_pm; in cti_port_setup_common()
840 port->port.shutdown = exar_shutdown; in cti_port_setup_common()
851 priv->osc_freq = CTI_DEFAULT_FPGA_OSC_FREQ; in cti_board_init_fpga()
888 port->port.type = PORT_XR17D15X; in cti_port_setup_fpga()
890 port->port.get_divisor = xr17v35x_get_divisor; in cti_port_setup_fpga()
891 port->port.set_divisor = xr17v35x_set_divisor; in cti_port_setup_fpga()
892 port->port.startup = xr17v35x_startup; in cti_port_setup_fpga()
895 port->port.rs485_config = generic_rs485_config; in cti_port_setup_fpga()
896 port->port.rs485_supported = generic_rs485_supported; in cti_port_setup_fpga()
905 priv->osc_freq = CTI_DEFAULT_PCIE_OSC_FREQ; in cti_board_init_xr17v35x()
923 port->port.type = PORT_XR17V35X; in cti_port_setup_xr17v35x()
925 port->port.get_divisor = xr17v35x_get_divisor; in cti_port_setup_xr17v35x()
926 port->port.set_divisor = xr17v35x_set_divisor; in cti_port_setup_xr17v35x()
927 port->port.startup = xr17v35x_startup; in cti_port_setup_xr17v35x()
932 port->port.rs485_config = cti_rs485_config_mpio_tristate; in cti_port_setup_xr17v35x()
933 port->port.rs485_supported = generic_rs485_supported; in cti_port_setup_xr17v35x()
938 port->port.rs485_config = generic_rs485_config; in cti_port_setup_xr17v35x()
939 port->port.rs485_supported = generic_rs485_supported; in cti_port_setup_xr17v35x()
962 switch (pcidev->subsystem_device) { in cti_board_init_xr17v25x()
988 port->port.type = PORT_XR17D15X; in cti_port_setup_xr17v25x()
991 port->port.get_divisor = xr17v35x_get_divisor; in cti_port_setup_xr17v25x()
992 port->port.set_divisor = xr17v35x_set_divisor; in cti_port_setup_xr17v25x()
993 port->port.startup = xr17v35x_startup; in cti_port_setup_xr17v25x()
996 switch (pcidev->subsystem_device) { in cti_port_setup_xr17v25x()
997 // These cards support power on 485 tri-state via MPIO in cti_port_setup_xr17v25x()
1009 port->port.rs485_config = cti_rs485_config_mpio_tristate; in cti_port_setup_xr17v25x()
1011 // Otherwise auto or no power on 485 tri-state support in cti_port_setup_xr17v25x()
1013 port->port.rs485_config = generic_rs485_config; in cti_port_setup_xr17v25x()
1017 port->port.rs485_supported = generic_rs485_supported; in cti_port_setup_xr17v25x()
1037 switch (pcidev->subsystem_device) { in cti_board_init_xr17c15x()
1065 port->port.type = PORT_XR17D15X; in cti_port_setup_xr17c15x()
1068 switch (pcidev->subsystem_device) { in cti_port_setup_xr17c15x()
1069 // These cards support power on 485 tri-state via MPIO in cti_port_setup_xr17c15x()
1081 port->port.rs485_config = cti_rs485_config_mpio_tristate; in cti_port_setup_xr17c15x()
1083 // Otherwise auto or no power on 485 tri-state support in cti_port_setup_xr17c15x()
1085 port->port.rs485_config = generic_rs485_config; in cti_port_setup_xr17c15x()
1089 port->port.rs485_supported = generic_rs485_supported; in cti_port_setup_xr17c15x()
1100 unsigned int baud = 921600; in pci_xr17c154_setup() local
1102 port->port.uartclk = baud * 16; in pci_xr17c154_setup()
1110 * devices will export them as GPIOs, so we pre-configure them safely in setup_gpio()
1115 if ((pcidev->vendor == PCI_VENDOR_ID_EXAR) && in setup_gpio()
1116 (pcidev->subsystem_vendor != PCI_VENDOR_ID_SEALEVEL)) { in setup_gpio()
1147 pdev->dev.parent = &pcidev->dev; in __xr17v35x_register_gpio()
1148 device_set_node(&pdev->dev, dev_fwnode(&pcidev->dev)); in __xr17v35x_register_gpio()
1150 if (device_add_software_node(&pdev->dev, node) < 0 || in __xr17v35x_register_gpio()
1161 device_remove_software_node(&pdev->dev); in __xr17v35x_unregister_gpio()
1166 PROPERTY_ENTRY_U32("exar,first-pin", 0),
1177 if (pcidev->vendor == PCI_VENDOR_ID_EXAR) in xr17v35x_register_gpio()
1178 port->port.private_data = in xr17v35x_register_gpio()
1186 if (!port->port.private_data) in xr17v35x_unregister_gpio()
1189 __xr17v35x_unregister_gpio(port->port.private_data); in xr17v35x_unregister_gpio()
1190 port->port.private_data = NULL; in xr17v35x_unregister_gpio()
1196 u8 __iomem *p = port->membase; in sealevel_rs485_config()
1206 if (!(rs485->flags & SER_RS485_ENABLED)) in sealevel_rs485_config()
1216 /* Set MCR to use DTR as Auto-RS485 Enable signal */ in sealevel_rs485_config()
1242 bool is_rs485 = !!(rs485->flags & SER_RS485_ENABLED); in iot2040_rs485_config()
1243 u8 __iomem *p = port->membase; in iot2040_rs485_config()
1248 if (rs485->flags & SER_RS485_RX_DURING_TX) in iot2040_rs485_config()
1253 if (rs485->flags & SER_RS485_TERMINATE_BUS) in iot2040_rs485_config()
1259 if (port->line == 3) { in iot2040_rs485_config()
1278 PROPERTY_ENTRY_U32("exar,first-pin", 10),
1290 u8 __iomem *p = port->port.membase; in iot2040_register_gpio()
1297 port->port.private_data = in iot2040_register_gpio()
1331 return dmi_match->driver_data; in exar_get_platform()
1342 unsigned int baud = 7812500; in pci_xr17v35x_setup() local
1346 port->port.uartclk = baud * 16; in pci_xr17v35x_setup()
1347 port->port.rs485_config = platform->rs485_config; in pci_xr17v35x_setup()
1348 port->port.rs485_supported = *(platform->rs485_supported); in pci_xr17v35x_setup()
1350 if (pcidev->subsystem_vendor == PCI_VENDOR_ID_SEALEVEL) in pci_xr17v35x_setup()
1351 port->port.rs485_config = sealevel_rs485_config; in pci_xr17v35x_setup()
1358 port->port.uartclk /= 2; in pci_xr17v35x_setup()
1364 p = port->port.membase; in pci_xr17v35x_setup()
1375 ret = platform->register_gpio(pcidev, port); in pci_xr17v35x_setup()
1385 struct uart_8250_port *port = serial8250_get_port(priv->line[0]); in pci_xr17v35x_exit()
1387 platform->unregister_gpio(port); in pci_xr17v35x_exit()
1393 readb(priv->virt + UART_EXAR_INT0); in exar_misc_clear()
1396 if (priv->board->num_ports > 8) in exar_misc_clear()
1397 readb(priv->virt + 0x2000 + UART_EXAR_INT0); in exar_misc_clear()
1418 if (pcidev->vendor == PCI_VENDOR_ID_ACCESSIO) in exar_get_nr_ports()
1419 return BIT(((pcidev->device & 0x38) >> 3) - 1); in exar_get_nr_ports()
1422 if (board->num_ports > 0) in exar_get_nr_ports()
1423 return board->num_ports; in exar_get_nr_ports()
1426 if (pcidev->vendor == PCI_VENDOR_ID_EXAR) in exar_get_nr_ports()
1427 return pcidev->device & 0x0f; in exar_get_nr_ports()
1430 if (pcidev->vendor == PCI_VENDOR_ID_CONNECT_TECH) { in exar_get_nr_ports()
1431 switch (pcidev->device) { in exar_get_nr_ports()
1454 board = (struct exar8250_board *)ent->driver_data; in exar_pci_probe()
1456 return -EINVAL; in exar_pci_probe()
1462 maxnr = pci_resource_len(pcidev, bar) >> (board->reg_shift + 3); in exar_pci_probe()
1466 return dev_err_probe(&pcidev->dev, -ENODEV, "failed to get number of ports\n"); in exar_pci_probe()
1468 priv = devm_kzalloc(&pcidev->dev, struct_size(priv, line, nr_ports), GFP_KERNEL); in exar_pci_probe()
1470 return -ENOMEM; in exar_pci_probe()
1472 priv->board = board; in exar_pci_probe()
1473 priv->virt = pcim_iomap(pcidev, bar, 0); in exar_pci_probe()
1474 if (!priv->virt) in exar_pci_probe()
1475 return -ENOMEM; in exar_pci_probe()
1486 uart.port.dev = &pcidev->dev; in exar_pci_probe()
1491 rc = devm_request_irq(&pcidev->dev, uart.port.irq, exar_misc_handler, in exar_pci_probe()
1499 rc = board->setup(priv, pcidev, &uart, i); in exar_pci_probe()
1501 dev_err_probe(&pcidev->dev, rc, "Failed to setup port %u\n", i); in exar_pci_probe()
1505 dev_dbg(&pcidev->dev, "Setup PCI port: port %lx, irq %d, type %d\n", in exar_pci_probe()
1508 priv->line[i] = serial8250_register_8250_port(&uart); in exar_pci_probe()
1509 if (priv->line[i] < 0) { in exar_pci_probe()
1510 dev_err_probe(&pcidev->dev, priv->line[i], in exar_pci_probe()
1516 priv->nr = i; in exar_pci_probe()
1526 for (i = 0; i < priv->nr; i++) in exar_pci_remove()
1527 serial8250_unregister_port(priv->line[i]); in exar_pci_remove()
1530 if (priv->board->exit) in exar_pci_remove()
1531 priv->board->exit(pcidev); in exar_pci_remove()
1539 for (i = 0; i < priv->nr; i++) in exar_suspend()
1540 if (priv->line[i] >= 0) in exar_suspend()
1541 serial8250_suspend_port(priv->line[i]); in exar_suspend()
1553 for (i = 0; i < priv->nr; i++) in exar_resume()
1554 if (priv->line[i] >= 0) in exar_resume()
1555 serial8250_resume_port(priv->line[i]); in exar_resume()
1695 /* USRobotics USR298x-OEM PCI Modems */