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/linux/Documentation/devicetree/bindings/timer/
H A Darm,arch_timer.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/timer/arm,arch_timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM architected timer
10 - Marc Zyngier <marc.zyngier@arm.com>
11 - Mark Rutland <mark.rutland@arm.com>
13 ARM cores may have a per-core architected timer, which provides per-cpu timers,
14 or a memory mapped architected timer, which provides up to 8 frames with a
15 physical and optional virtual timer per frame.
[all …]
H A Darm,arch_timer_mmio.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/timer/arm,arch_timer_mmio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM memory mapped architected timer
10 - Marc Zyngier <marc.zyngier@arm.com>
11 - Mark Rutland <mark.rutland@arm.com>
14 ARM cores may have a memory mapped architected timer, which provides up to 8
15 frames with a physical and optional virtual timer per frame.
17 The memory mapped timer is attached to a GIC to deliver its interrupts via SPIs.
[all …]
H A Darm,armv7m-systick.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/arm,armv7m-systick.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARMv7M System Timer
10 - Alexandre Torgue <alexandre.torgue@foss.st.com>
11 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
13 description: ARMv7-M includes a system timer, known as SysTick.
17 const: arm,armv7m-systick
25 clock-frequency: true
[all …]
/linux/arch/arm/mach-at91/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
14 bool "SAM Cortex-M7 family" if ARM_SINGLE_ARMV7M
73 bool "ARMv7 based Microchip LAN966 SoC family"
79 This enables support for ARMv7 based Microchip LAN966 SoC family.
163 bool "Periodic Interval Timer (PIT) support"
169 Timer. It has a relatively low resolution and the TC Block clocksource
173 bool "Timer Counter Blocks (TCB) support"
179 On platforms with 16-bit counters, two timer channels are combined
180 to make a single 32-bit timer.
184 bool "64-bit Periodic Interval Timer (PIT64B) support"
[all …]
/linux/arch/arm/boot/dts/allwinner/
H A Dsun8i-t113s.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <riscv/allwinner/sunxi-d1s-t113.dtsi>
8 #include <riscv/allwinner/sunxi-d1-t113.dtsi>
11 interrupt-parent = <&gic>;
14 #address-cells = <1>;
15 #size-cells = <0>;
18 compatible = "arm,cortex-a7";
22 clock-names = "cpu";
26 compatible = "arm,cortex-a7";
[all …]
/linux/arch/arm/boot/dts/socionext/
H A Dmilbeaut-m10v.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/interrupt-controller/irq.h>
3 #include <dt-bindings/input/input.h>
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 interrupt-parent = <&gic>;
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
[all …]
/linux/arch/arm/boot/dts/calxeda/
H A Decx-2000.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2011-2012 Calxeda, Inc.
6 /dts-v1/;
12 model = "Calxeda ECX-2000";
13 compatible = "calxeda,ecx-2000";
14 #address-cells = <2>;
15 #size-cells = <2>;
18 #address-cells = <1>;
19 #size-cells = <0>;
22 compatible = "arm,cortex-a15";
[all …]
/linux/arch/arm/boot/dts/xen/
H A Dxenvm-4.2.dts1 // SPDX-License-Identifier: GPL-2.0
6 * Cortex-A15 MPCore (V2P-CA15)
10 /dts-v1/;
13 model = "XENVM-4.2";
14 compatible = "xen,xenvm-4.2", "xen,xenvm";
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
25 #address-cells = <1>;
26 #size-cells = <0>;
[all …]
/linux/arch/arm/boot/dts/sunplus/
H A Dsunplus-sp7021-achip.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include "sunplus-sp7021.dtsi"
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "sunplus,sp7021-achip", "sunplus,sp7021";
14 #address-cells = <1>;
15 #size-cells = <1>;
16 interrupt-parent = <&gic>;
19 #address-cells = <1>;
20 #size-cells = <0>;
23 compatible = "arm,cortex-a7";
[all …]
/linux/arch/arm/boot/dts/mediatek/
H A Dmt8127.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
15 interrupt-parent = <&sysirq>;
18 #address-cells = <1>;
19 #size-cells = <0>;
20 enable-method = "mediatek,mt81xx-tz-smp";
24 compatible = "arm,cortex-a7";
[all …]
H A Dmt8135.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/mt8135-clk.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/mt8135-resets.h>
12 #include <dt-bindings/pinctrl/mt8135-pinfunc.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
18 interrupt-parent = <&sysirq>;
20 cpu-map {
[all …]
/linux/arch/arm64/boot/dts/arm/
H A Dcorstone1000.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 interrupt-parent = <&gic>;
12 #address-cells = <1>;
13 #size-cells = <1>;
21 stdout-path = "serial0:115200n8";
25 #address-cells = <1>;
26 #size-cells = <0>;
30 compatible = "arm,cortex-a35";
32 next-level-cache = <&L2_0>;
[all …]
/linux/drivers/clocksource/
H A Darm_arch_timer.c1 // SPDX-License-Identifier: GPL-2.0-only
29 #include <linux/arm-smccc.h>
77 [ARCH_TIMER_PHYS_SECURE_PPI] = "sec-phys",
80 [ARCH_TIMER_HYP_PPI] = "hyp-phys",
81 [ARCH_TIMER_HYP_VIRT_PPI] = "hyp-virt",
106 * Makes an educated guess at a valid counter width based on the Generic Timer
109 * 2) a roll-over time of not less than 40 years
118 return clamp_val(ilog2(min_cycles - 1) + 1, 56, 64); in arch_counter_get_width()
122 * Architected system timer support.
130 struct arch_timer *timer = to_arch_timer(clk); in arch_timer_reg_write() local
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/linux/arch/arm/mach-shmobile/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
7 obj-y := timer.o
10 obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o
11 obj-$(CONFIG_ARCH_R8A73A4) += setup-r8a73a4.o
12 obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o
13 obj-$(CONFIG_ARCH_R8A7778) += setup-r8a7778.o
14 obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o
15 obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o
16 obj-$(CONFIG_ARCH_R7S72100) += setup-r7s72100.o
17 obj-$(CONFIG_ARCH_R7S9210) += setup-r7s9210.o
[all …]
/linux/arch/arm/boot/dts/intel/axm/
H A Daxm55xx.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/lsi,axm5516-clks.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
14 interrupt-parent = <&gic>;
21 timer = &timer0;
25 compatible = "simple-bus";
26 #address-cells = <2>;
27 #size-cells = <2>;
[all …]
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm6846.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
14 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-a7";
24 next-level-cache = <&L2_0>;
[all …]
H A Dbcm63148.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
14 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "brcm,brahma-b15";
24 next-level-cache = <&L2_0>;
[all …]
H A Dbcm6878.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
14 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-a7";
24 next-level-cache = <&L2_0>;
[all …]
H A Dbcm6855.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
14 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-a7";
24 next-level-cache = <&L2_0>;
[all …]
H A Dbcm63178.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
14 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-a7";
24 next-level-cache = <&L2_0>;
[all …]
H A Dbcm6756.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
14 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-a7";
24 next-level-cache = <&L2_0>;
[all …]
H A Dbcm47622.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
14 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-a7";
24 next-level-cache = <&L2_0>;
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Dexynos54xx.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
28 arm_a7_pmu: arm-a7-pmu {
29 compatible = "arm,cortex-a7-pmu";
30 interrupt-parent = <&gic>;
38 arm_a15_pmu: arm-a15-pmu {
39 compatible = "arm,cortex-a15-pmu";
40 interrupt-parent = <&combiner>;
48 timer: timer { label
49 compatible = "arm,armv7-timer";
[all …]
/linux/arch/arm/boot/dts/amazon/
H A Dalpine.dtsi27 #include <dt-bindings/interrupt-controller/arm-gic.h>
30 #address-cells = <2>;
31 #size-cells = <2>;
42 #address-cells = <1>;
43 #size-cells = <0>;
44 enable-method = "al,alpine-smp";
47 compatible = "arm,cortex-a15";
50 clock-frequency = <1700000000>;
54 compatible = "arm,cortex-a15";
57 clock-frequency = <1700000000>;
[all …]
/linux/arch/arm/mach-sunxi/
H A Dheadsmp.S1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018 Chen-Yu Tsai
6 * Chen-Yu Tsai <wens@csie.org>
18 .arch armv7-a
20 * Enable cluster-level coherency, in preparation for turning on the MMU.
23 * Cortex-A15. These settings are from the vendor kernel.
34 /* The following is Cortex-A15 specific */
43 /* Enable L2, GIC, and Timer regional clock gates */
55 /* End of Cortex-A15 specific setup */
69 first: .word sunxi_mc_smp_first_comer - .

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