Home
last modified time | relevance | path

Searched +full:armv7 +full:- +full:timer (Results 1 – 25 of 69) sorted by relevance

123

/linux/Documentation/devicetree/bindings/timer/
H A Darm,arch_timer_mmio.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/timer/arm,arch_timer_mmio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM memory mapped architected timer
10 - Marc Zyngier <marc.zyngier@arm.com>
11 - Mark Rutland <mark.rutland@arm.com>
14 ARM cores may have a memory mapped architected timer, which provides up to 8
15 frames with a physical and optional virtual timer per frame.
17 The memory mapped timer is attached to a GIC to deliver its interrupts via SPIs.
[all …]
H A Darm,armv7m-systick.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/arm,armv7m-systick.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARMv7M System Timer
10 - Alexandre Torgue <alexandre.torgue@foss.st.com>
11 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
13 description: ARMv7-M includes a system timer, known as SysTick.
17 const: arm,armv7m-systick
25 clock-frequency: true
[all …]
/linux/arch/arm/boot/dts/socionext/
H A Dmilbeaut-m10v.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/interrupt-controller/irq.h>
3 #include <dt-bindings/input/input.h>
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 interrupt-parent = <&gic>;
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
[all …]
/linux/arch/arm/boot/dts/calxeda/
H A Decx-2000.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2011-2012 Calxeda, Inc.
6 /dts-v1/;
12 model = "Calxeda ECX-2000";
13 compatible = "calxeda,ecx-2000";
14 #address-cells = <2>;
15 #size-cells = <2>;
18 #address-cells = <1>;
19 #size-cells = <0>;
22 compatible = "arm,cortex-a15";
[all …]
/linux/arch/arm/boot/dts/xen/
H A Dxenvm-4.2.dts1 // SPDX-License-Identifier: GPL-2.0
6 * Cortex-A15 MPCore (V2P-CA15)
10 /dts-v1/;
13 model = "XENVM-4.2";
14 compatible = "xen,xenvm-4.2", "xen,xenvm";
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
25 #address-cells = <1>;
26 #size-cells = <0>;
[all …]
/linux/arch/arm/boot/dts/sunplus/
H A Dsunplus-sp7021-achip.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include "sunplus-sp7021.dtsi"
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "sunplus,sp7021-achip", "sunplus,sp7021";
14 #address-cells = <1>;
15 #size-cells = <1>;
16 interrupt-parent = <&gic>;
19 #address-cells = <1>;
20 #size-cells = <0>;
23 compatible = "arm,cortex-a7";
[all …]
/linux/arch/arm/mach-shmobile/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
7 obj-y := timer.o
10 obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o
11 obj-$(CONFIG_ARCH_R8A73A4) += setup-r8a73a4.o
12 obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o
13 obj-$(CONFIG_ARCH_R8A7778) += setup-r8a7778.o
14 obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o
15 obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o
16 obj-$(CONFIG_ARCH_R7S72100) += setup-r7s72100.o
17 obj-$(CONFIG_ARCH_R7S9210) += setup-r7s9210.o
[all …]
/linux/arch/arm/boot/dts/intel/axm/
H A Daxm55xx.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/lsi,axm5516-clks.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
14 interrupt-parent = <&gic>;
21 timer = &timer0;
25 compatible = "simple-bus";
26 #address-cells = <2>;
27 #size-cells = <2>;
[all …]
/linux/arch/arm/mach-sunxi/
H A Dheadsmp.S1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018 Chen-Yu Tsai
6 * Chen-Yu Tsai <wens@csie.org>
18 .arch armv7-a
20 * Enable cluster-level coherency, in preparation for turning on the MMU.
23 * Cortex-A15. These settings are from the vendor kernel.
34 /* The following is Cortex-A15 specific */
43 /* Enable L2, GIC, and Timer regional clock gates */
55 /* End of Cortex-A15 specific setup */
69 first: .word sunxi_mc_smp_first_comer - .
/linux/arch/arm/boot/dts/amazon/
H A Dalpine.dtsi27 #include <dt-bindings/interrupt-controller/arm-gic.h>
30 #address-cells = <2>;
31 #size-cells = <2>;
42 #address-cells = <1>;
43 #size-cells = <0>;
44 enable-method = "al,alpine-smp";
47 compatible = "arm,cortex-a15";
50 clock-frequency = <1700000000>;
54 compatible = "arm,cortex-a15";
57 clock-frequency = <1700000000>;
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Dexynos54xx.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
28 arm_a7_pmu: arm-a7-pmu {
29 compatible = "arm,cortex-a7-pmu";
30 interrupt-parent = <&gic>;
38 arm_a15_pmu: arm-a15-pmu {
39 compatible = "arm,cortex-a15-pmu";
40 interrupt-parent = <&combiner>;
48 timer: timer { label
49 compatible = "arm,armv7-timer";
[all …]
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm6756.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
14 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-a7";
24 next-level-cache = <&L2_0>;
[all …]
H A Dbcm47622.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
14 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-a7";
24 next-level-cache = <&L2_0>;
[all …]
H A Dbcm2837.dtsi2 #include "bcm2835-common.dtsi"
10 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
12 local_intc: interrupt-controller@40000000 {
13 compatible = "brcm,bcm2836-l1-intc";
15 interrupt-controller;
16 #interrupt-cells = <2>;
17 interrupt-parent = <&local_intc>;
21 arm-pmu {
22 compatible = "arm,cortex-a53-pmu";
23 interrupt-parent = <&local_intc>;
[all …]
H A Dbcm2836.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include "bcm2835-common.dtsi"
11 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
13 local_intc: interrupt-controller@40000000 {
14 compatible = "brcm,bcm2836-l1-intc";
16 interrupt-controller;
17 #interrupt-cells = <2>;
18 interrupt-parent = <&local_intc>;
22 arm-pmu {
23 compatible = "arm,cortex-a7-pmu";
[all …]
H A Dbcm53573.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
14 interrupt-parent = <&gic>;
21 stdout-path = "serial0:115200n8";
25 #address-cells = <1>;
[all …]
H A Dbcm63178.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
14 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-a7";
24 next-level-cache = <&L2_0>;
[all …]
/linux/arch/arm/boot/dts/arm/
H A Dmps2.dtsi6 * This file is dual-licensed: you can use it either under the terms
45 #include "../armv7-m.dtsi"
48 #address-cells = <1>;
49 #size-cells = <1>;
51 oscclk0: clock-50000000 {
52 compatible = "fixed-clock";
53 #clock-cells = <0>;
54 clock-frequency = <50000000>;
57 oscclk1: clock-24576000 {
58 compatible = "fixed-clock";
[all …]
H A Dvexpress-v2p-ca15-tc1.dts1 // SPDX-License-Identifier: GPL-2.0
6 * Cortex-A15 MPCore (V2P-CA15)
8 * HBI-0237A
11 /dts-v1/;
12 #include "vexpress-v2m-rs1.dtsi"
15 model = "V2P-CA15";
18 compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
[all …]
/linux/arch/arm/kernel/
H A Dvdso.c1 // SPDX-License-Identifier: GPL-2.0-only
40 current->mm->context.vdso = new_vma->vm_start; in vdso_mremap()
57 /* Boot-time check for whether the arch timer exists, and if so,
72 np = of_find_compatible_node(NULL, NULL, "arm,armv7-timer"); in cntvct_functional()
74 np = of_find_compatible_node(NULL, NULL, "arm,armv8-timer"); in cntvct_functional()
78 if (of_property_read_bool(np, "arm,cpu-registers-not-fw-configured")) in cntvct_functional()
97 sechdrs = (void *)ehdr + ehdr->e_shoff; in find_section()
98 secnames = (void *)ehdr + sechdrs[ehdr->e_shstrndx].sh_offset; in find_section()
101 for (i = 1; i < ehdr->e_shnum; i++) { in find_section()
118 for (i = 0; i < (lib->dynsymsize / sizeof(Elf32_Sym)); i++) { in find_symbol()
[all …]
/linux/arch/arm/boot/dts/realtek/
H A Drtd1195.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
3 * Copyright (c) 2017-2019 Andreas Färber
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/realtek,rtd1195.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <1>;
17 #size-cells = <1>;
20 #address-cells = <1>;
21 #size-cells = <0>;
25 compatible = "arm,cortex-a7";
[all …]
/linux/arch/arm/boot/dts/sigmastar/
H A Dmstar-v7.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/mstar-msc313-mpll.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
14 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-a7";
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimxrt1050.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "../../armv7-m.dtsi"
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/imxrt1050-clock.h>
10 #include <dt-bindings/gpio/gpio.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
18 compatible = "fixed-clock";
19 #clock-cells = <0>;
20 clock-frequency = <24000000>;
[all …]
/linux/arch/arm/boot/dts/ti/keystone/
H A Dkeystone.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/gpio/gpio.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
14 interrupt-parent = <&gic>;
30 gic: interrupt-controller@2561000 {
31 compatible = "arm,gic-400", "arm,cortex-a15-gic";
32 #interrupt-cells = <3>;
[all …]
/linux/arch/arm/boot/dts/qcom/
H A Dqcom-sdx65.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
9 #include <dt-bindings/clock/qcom,gcc-sdx65.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
15 #include <dt-bindings/interconnect/qcom,sdx65.h>
18 #address-cells = <1>;
19 #size-cells = <1>;
[all …]

123