Lines Matching +full:armv7 +full:- +full:timer
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
14 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-a7";
24 next-level-cache = <&L2_0>;
25 enable-method = "psci";
30 compatible = "arm,cortex-a7";
32 next-level-cache = <&L2_0>;
33 enable-method = "psci";
38 compatible = "arm,cortex-a7";
40 next-level-cache = <&L2_0>;
41 enable-method = "psci";
46 compatible = "arm,cortex-a7";
48 next-level-cache = <&L2_0>;
49 enable-method = "psci";
52 L2_0: l2-cache0 {
54 cache-level = <2>;
55 cache-unified;
59 timer {
60 compatible = "arm,armv7-timer";
65 arm,cpu-registers-not-fw-configured;
69 compatible = "arm,cortex-a7-pmu";
74 interrupt-affinity = <&CA7_0>, <&CA7_1>,
79 periph_clk: periph-clk {
80 compatible = "fixed-clock";
81 #clock-cells = <0>;
82 clock-frequency = <200000000>;
85 uart_clk: uart-clk {
86 compatible = "fixed-factor-clock";
87 #clock-cells = <0>;
89 clock-div = <4>;
90 clock-mult = <1>;
93 hsspi_pll: hsspi-pll {
94 compatible = "fixed-clock";
95 #clock-cells = <0>;
96 clock-frequency = <200000000>;
101 compatible = "arm,psci-0.2";
106 compatible = "simple-bus";
107 #address-cells = <1>;
108 #size-cells = <1>;
111 gic: interrupt-controller@1000 {
112 compatible = "arm,cortex-a7-gic";
113 #interrupt-cells = <3>;
114 interrupt-controller;
124 compatible = "simple-bus";
125 #address-cells = <1>;
126 #size-cells = <1>;
130 #address-cells = <1>;
131 #size-cells = <0>;
132 compatible = "brcm,bcm47622-hsspi", "brcm,bcmbca-hsspi-v1.0";
136 clock-names = "hsspi", "pll";
137 num-cs = <8>;
141 nand_controller: nand-controller@1800 {
142 #address-cells = <1>;
143 #size-cells = <0>;
144 compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";
146 reg-names = "nand", "nand-int-base";
160 clock-names = "uartclk", "apb_pclk";