Lines Matching +full:armv7 +full:- +full:timer
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
14 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-a7";
24 next-level-cache = <&L2_0>;
25 enable-method = "psci";
30 compatible = "arm,cortex-a7";
32 next-level-cache = <&L2_0>;
33 enable-method = "psci";
38 compatible = "arm,cortex-a7";
40 next-level-cache = <&L2_0>;
41 enable-method = "psci";
44 L2_0: l2-cache0 {
46 cache-level = <2>;
47 cache-unified;
51 timer {
52 compatible = "arm,armv7-timer";
57 arm,cpu-registers-not-fw-configured;
61 compatible = "arm,cortex-a7-pmu";
65 interrupt-affinity = <&CA7_0>, <&CA7_1>,
70 periph_clk: periph-clk {
71 compatible = "fixed-clock";
72 #clock-cells = <0>;
73 clock-frequency = <200000000>;
76 uart_clk: uart-clk {
77 compatible = "fixed-factor-clock";
78 #clock-cells = <0>;
80 clock-div = <4>;
81 clock-mult = <1>;
84 hsspi_pll: hsspi-pll {
85 compatible = "fixed-clock";
86 #clock-cells = <0>;
87 clock-frequency = <200000000>;
92 compatible = "arm,psci-0.2";
97 compatible = "simple-bus";
98 #address-cells = <1>;
99 #size-cells = <1>;
102 gic: interrupt-controller@1000 {
103 compatible = "arm,cortex-a7-gic";
104 #interrupt-cells = <3>;
105 interrupt-controller;
115 compatible = "simple-bus";
116 #address-cells = <1>;
117 #size-cells = <1>;
121 #address-cells = <1>;
122 #size-cells = <0>;
123 compatible = "brcm,bcm63178-hsspi", "brcm,bcmbca-hsspi-v1.0";
127 clock-names = "hsspi", "pll";
128 num-cs = <8>;
132 nand_controller: nand-controller@1800 {
133 #address-cells = <1>;
134 #size-cells = <0>;
135 compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";
137 reg-names = "nand", "nand-int-base";
151 clock-names = "uartclk", "apb_pclk";