Lines Matching +full:armv7 +full:- +full:timer

1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/timer/arm,arch_timer_mmio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM memory mapped architected timer
10   - Marc Zyngier <marc.zyngier@arm.com>
11   - Mark Rutland <mark.rutland@arm.com>
14   ARM cores may have a memory mapped architected timer, which provides up to 8
15   frames with a physical and optional virtual timer per frame.
17   The memory mapped timer is attached to a GIC to deliver its interrupts via SPIs.
22       - enum:
23           - arm,armv7-timer-mem
29   '#address-cells':
32   '#size-cells':
37   clock-frequency:
43   always-on:
45     description: If present, the timer is powered through an always-on power
48   arm,cpu-registers-not-fw-configured:
50     description: Firmware does not initialize any of the generic timer CPU
51       registers, which contain their architecturally-defined reset values. Only
52       supported for 32-bit systems which follow the ARMv7 architected reset
55   arm,no-tick-in-suspend:
58       low-power system suspend on some SoCs. This behavior does not match the
60       be implemented in an always-on power domain."
63   '^frame@[0-9a-f]+$':
66     description: A timer node has up to 8 frame sub-nodes, each with the following properties.
68       frame-number:
76           - description: physical timer irq
77           - description: virtual timer irq
82           - description: 1st view base address
83           - description: 2nd optional view base address
86       - frame-number
87       - interrupts
88       - reg
91   - compatible
92   - reg
93   - '#address-cells'
94   - '#size-cells'
99   - |
100     timer@f0000000 {
101       compatible = "arm,armv7-timer-mem";
102       #address-cells = <1>;
103       #size-cells = <1>;
106       clock-frequency = <50000000>;
109         frame-number = <0>;
117         frame-number = <1>;