Lines Matching +full:armv7 +full:- +full:timer
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
14 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-a7";
24 next-level-cache = <&L2_0>;
25 enable-method = "psci";
30 compatible = "arm,cortex-a7";
32 next-level-cache = <&L2_0>;
33 enable-method = "psci";
38 compatible = "arm,cortex-a7";
40 next-level-cache = <&L2_0>;
41 enable-method = "psci";
44 L2_0: l2-cache0 {
46 cache-level = <2>;
47 cache-unified;
51 timer {
52 compatible = "arm,armv7-timer";
57 arm,cpu-registers-not-fw-configured;
61 compatible = "arm,cortex-a7-pmu";
65 interrupt-affinity = <&CA7_0>, <&CA7_1>, <&CA7_2>;
69 periph_clk: periph-clk {
70 compatible = "fixed-clock";
71 #clock-cells = <0>;
72 clock-frequency = <200000000>;
75 uart_clk: uart-clk {
76 compatible = "fixed-factor-clock";
77 #clock-cells = <0>;
79 clock-div = <4>;
80 clock-mult = <1>;
83 hsspi_pll: hsspi-pll {
84 compatible = "fixed-clock";
85 #clock-cells = <0>;
86 clock-frequency = <200000000>;
91 compatible = "arm,psci-0.2";
96 compatible = "simple-bus";
97 #address-cells = <1>;
98 #size-cells = <1>;
101 gic: interrupt-controller@1000 {
102 compatible = "arm,cortex-a7-gic";
103 #interrupt-cells = <3>;
104 interrupt-controller;
114 compatible = "simple-bus";
115 #address-cells = <1>;
116 #size-cells = <1>;
120 #address-cells = <1>;
121 #size-cells = <0>;
122 compatible = "brcm,bcm6855-hsspi", "brcm,bcmbca-hsspi-v1.1";
124 reg-names = "hsspi", "spim-ctrl";
127 clock-names = "hsspi", "pll";
128 num-cs = <8>;
132 nand_controller: nand-controller@1800 {
133 #address-cells = <1>;
134 #size-cells = <0>;
135 compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";
137 reg-names = "nand", "nand-int-base";
151 clock-names = "uartclk", "apb_pclk";