| /linux/arch/arm/boot/dts/marvell/ |
| H A D | armada-xp.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Marvell Armada XP family SoC
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 * Contains definitions specific to the Armada XP SoC that are not
13 * common to all Armada SoCs.
16 #include "armada-370-xp.dtsi"
19 #address-cells = <2>;
20 #size-cells = <2>;
22 model = "Marvell Armada XP family SoC";
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| H A D | armada-xp-98dx3236.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * common to all Armada XP SoCs.
11 #include "armada-370-xp.dtsi"
14 #address-cells = <2>;
15 #size-cells = <2>;
18 compatible = "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
27 #address-cells = <1>;
28 #size-cells = <0>;
29 enable-method = "marvell,98dx3236-smp";
31 cpu@0 {
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| H A D | armada-xp-mv78230.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Marvell Armada XP family SoC
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Contains definitions specific to the Armada XP MV78230 SoC that are not
10 * common to all Armada XP SoCs.
13 #include "armada-xp.dtsi"
16 model = "Marvell Armada XP MV78230 SoC";
17 compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
25 #address-cells = <1>;
26 #size-cells = <0>;
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| H A D | armada-xp-98dx3336.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * common to all Armada XP SoCs.
11 #include "armada-xp-98dx3236.dtsi"
15 compatible = "marvell,armadaxp-98dx3336", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
18 cpu@1 {
19 device_type = "cpu";
20 compatible = "marvell,sheeva-v7";
23 clock-latency = <1000000>;
28 internal-regs {
30 compatible = "marvell,98dx3336-resume-ctrl";
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| H A D | armada-xp-mv78460.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Marvell Armada XP family SoC
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Contains definitions specific to the Armada XP MV78460 SoC that are not
10 * common to all Armada XP SoCs.
13 #include "armada-xp.dtsi"
16 model = "Marvell Armada XP MV78460 SoC";
17 compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
27 #address-cells = <1>;
28 #size-cells = <0>;
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| H A D | armada-xp-98dx4251.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * common to all Armada XP SoCs.
11 #include "armada-xp-98dx3236.dtsi"
15 compatible = "marvell,armadaxp-98dx4251", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
18 cpu@1 {
19 device_type = "cpu";
20 compatible = "marvell,sheeva-v7";
23 clock-latency = <1000000>;
28 internal-regs {
30 compatible = "marvell,98dx3336-resume-ctrl";
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| H A D | armada-370-xp.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Marvell Armada 370 and Armada XP SoC
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 * This file contains the definitions that are common to the Armada
13 * 370 and Armada XP SoC.
19 model = "Marvell Armada 370 and XP SoC";
20 compatible = "marvell,armada-370-xp";
28 #address-cells = <1>;
29 #size-cells = <0>;
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| H A D | armada-xp-mv78260.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Marvell Armada XP family SoC
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Contains definitions specific to the Armada XP MV78260 SoC that are not
10 * common to all Armada XP SoCs.
13 #include "armada-xp.dtsi"
16 model = "Marvell Armada XP MV78260 SoC";
17 compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
26 #address-cells = <1>;
27 #size-cells = <0>;
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| H A D | armada-370.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Marvell Armada 370 family SoC
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
11 * Contains definitions specific to the Armada 370 SoC that are not
12 * common to all Armada SoCs.
15 #include "armada-370-xp.dtsi"
18 #address-cells = <1>;
19 #size-cells = <1>;
21 model = "Marvell Armada 370 family SoC";
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| H A D | armada-39x.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Marvell Armada 39x family of SoCs.
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
16 #address-cells = <1>;
17 #size-cells = <1>;
18 model = "Marvell Armada 39x family SoC";
31 #address-cells = <1>;
32 #size-cells = <0>;
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| H A D | armada-38x.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Marvell Armada 38x family of SoCs.
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
18 #address-cells = <1>;
19 #size-cells = <1>;
21 model = "Marvell Armada 38x family SoC";
32 compatible = "arm,cortex-a9-pmu";
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| H A D | armada-370-db.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for Marvell Armada 370 evaluation board
4 * (DB-88F6710-BP-DDR3)
9 * Gregory CLEMENT <gregory.clement@free-electrons.com>
10 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
15 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
22 /dts-v1/;
23 #include "armada-370.dtsi"
26 model = "Marvell Armada 370 Evaluation Board";
27 compatible = "marvell,a370-db", "marvell,armada370", "marvell,armada-370-xp";
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| H A D | armada-370-c200-v2.dts | 1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Device Tree file for Ctera C200-V2
8 /dts-v1/;
10 #include "armada-370.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/leds/common.h>
18 compatible = "ctera,c200-v2", "marvell,armada370", "marvell,armada-370-xp";
22 stdout-path = "serial0:115200n8";
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| /linux/drivers/clk/mvebu/ |
| H A D | armada-375.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Marvell Armada 375 SoC clocks
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
14 #include <linux/clk-provider.h>
24 * For the Armada 375 SoCs, the CPU, DDR and L2 clocks frequencies are
25 * all modified at the same time, and not separately as for the Armada
26 * 370 or the Armada XP SoCs.
28 * SAR1[21:17] : CPU frequency DDR frequency L2 frequency
78 pr_err("Selected CPU frequency (%d) unsupported\n", in armada_375_get_cpu_freq()
144 CLK_OF_DECLARE(armada_375_core_clk, "marvell,armada-375-core-clock",
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| H A D | common.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Marvell EBU SoC common clock handling
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
16 #include <linux/clk-provider.h>
38 * This function can be used by the Kirkwood, the Armada 370, the
39 * Armada XP and the Armada 375 SoC. The name of the function was
67 if ((high_bound - low_bound) <= 0) in kirkwood_fix_sscg_deviation()
72 * Spread percentage = 1/96 * (H - L) / H in kirkwood_fix_sscg_deviation()
83 freq_swing_half = (((u64)high_bound - (u64)low_bound) in kirkwood_fix_sscg_deviation()
89 system_clk -= freq_swing_half; in kirkwood_fix_sscg_deviation()
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| H A D | clk-cpu.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Marvell MVEBU CPU clock handling.
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
13 #include <linux/clk-provider.h>
18 #include <linux/mvebu-pmsu.h>
35 int cpu; member
54 reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET); in clk_cpu_recalc_rate()
55 div = (reg >> (cpuclk->cpu * 8)) & SYS_CTRL_CLK_DIVIDER_MASK; in clk_cpu_recalc_rate()
83 reg = (readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET) in clk_cpu_off_set_rate()
84 & (~(SYS_CTRL_CLK_DIVIDER_MASK << (cpuclk->cpu * 8)))) in clk_cpu_off_set_rate()
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| /linux/drivers/gpio/ |
| H A D | gpio-mvebu.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 * Kirkwood, Discovery, Armada 370/XP). The only complexity of this
15 * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP
16 * platforms (MV78200 from the Discovery family and the Armada
17 * XP). Therefore, this driver handles three variants of the GPIO
19 * - the basic variant, called "orion-gpio", with the simplest
20 * register set. Used on Orion, Dove, Kirkwoord, Armada 370 and
21 * non-SMP Discovery systems
22 * - the mv78200 variant for MV78200 Discovery systems. This variant
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| /linux/drivers/clocksource/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
2 menu "Clock Source drivers"
60 bool "OMAP dual-mode timer driver" if ARCH_K3 || COMPILE_TEST
64 Enables the support for the TI dual-mode timer driver.
82 Support for CPU timer found on EcoNet MIPS based SoCs.
111 bool "Armada 370 and XP timer driver" if COMPILE_TEST
116 Enables the support for the Armada 370 and XP timer driver.
198 Enable 24-bit TIMER0 and TIMER1 counters in the NPCM7xx architecture,
221 32-bit free running decrementing counters.
256 bool "Integrator-AP timer driver" if COMPILE_TEST
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| /linux/Documentation/devicetree/bindings/arm/ |
| H A D | cpus.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
14 "cpus" node, which in turn contains a number of subnodes (ie "cpu") defining
15 properties for every cpu.
17 Bindings for CPU nodes follow the Devicetree Specification, available from:
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
34 cpus and cpu node bindings definition
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| /linux/drivers/bus/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
37 Driver for the Broadcom Set Top Box System-on-a-chip internal bus
42 bool "Baikal-T1 APB-bus driver"
46 Baikal-T1 AXI-APB bridge is used to access the SoC subsystem CSRs.
53 errors counter. The counter and the APB-bus operations timeout can be
57 bool "Baikal-T1 AXI-bus driver"
61 AXI3-bus is the main communication bus connecting all high-speed
62 peripheral IP-cores with RAM controller and with MIPS P5600 cores on
63 Baikal-T1 SoC. Traffic arbitration is done by means of DW AMBA 3 AXI
120 cores. This bus is for per-CPU tightly coupled devices such as the
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| /linux/drivers/pci/controller/ |
| H A D | pci-mvebu.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe driver for Marvell Armada 370 and Armada XP SoCs
5 * Author: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
27 #include "../pci-bridge-emul.h"
40 #define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
130 writel(val, port->base + reg); in mvebu_writel()
135 return readl(port->base + reg); in mvebu_readl()
140 return port->io_target != -1 && port->io_attr != -1; in mvebu_has_ioport()
199 * BAR[0] -> internal registers (needed for MSI)
200 * BAR[1] -> covers all DRAM banks
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| /linux/drivers/net/ethernet/marvell/ |
| H A D | mvneta.c | 2 * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs.
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
15 #include <linux/cpu.h>
114 /* Only exists on Armada XP and Armada 370 */
131 #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2)) argument
141 * registers. For a given CPU if the bit associated to a queue is not
142 * set, then for the register a read from this CPU will always return
156 #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0)
158 #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8)
270 * to cover all rate-limit values from 10Kbps up to 5Gbps
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| /linux/ |
| H A D | MAINTAINERS | 5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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| H A D | CREDITS | 1 This is at least a partial credits-file of people that have
4 scripts. The fields are: name (N), email (E), web-address
6 snail-mail address (S).
10 ----------
51 D: in-kernel DRM Maintainer
59 D: Intel IA32 CPU microcode update support
76 E: tim_alpaerts@toyota-motor-europe.com
80 S: B-2610 Wilrijk-Antwerpen
85 W: http://www-stu.christs.cam.ac.uk/~aia21/
106 D: Maintainer of ide-cd and Uniform CD-ROM driver,
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