1 // SPDX-License-Identifier: GPL-2.0
3  * Marvell MVEBU CPU clock handling.
7  * Gregory CLEMENT <gregory.clement@free-electrons.com>
13 #include <linux/clk-provider.h>
18 #include <linux/mvebu-pmsu.h>
35 	int cpu;  member
54 	reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET);  in clk_cpu_recalc_rate()
55 	div = (reg >> (cpuclk->cpu * 8)) & SYS_CTRL_CLK_DIVIDER_MASK;  in clk_cpu_recalc_rate()
83 	reg = (readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET)  in clk_cpu_off_set_rate()
84 		& (~(SYS_CTRL_CLK_DIVIDER_MASK << (cpuclk->cpu * 8))))  in clk_cpu_off_set_rate()
85 		| (div << (cpuclk->cpu * 8));  in clk_cpu_off_set_rate()
86 	writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET);  in clk_cpu_off_set_rate()
87 	/* Set clock divider reload smooth bit mask */  in clk_cpu_off_set_rate()
88 	reload_mask = 1 << (20 + cpuclk->cpu);  in clk_cpu_off_set_rate()
90 	reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET)  in clk_cpu_off_set_rate()
92 	writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET);  in clk_cpu_off_set_rate()
94 	/* Now trigger the clock update */  in clk_cpu_off_set_rate()
95 	reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET)  in clk_cpu_off_set_rate()
97 	writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET);  in clk_cpu_off_set_rate()
102 	writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET);  in clk_cpu_off_set_rate()
119 	if (!cpuclk->pmu_dfs)  in clk_cpu_on_set_rate()
120 		return -ENODEV;  in clk_cpu_on_set_rate()
124 	reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL2_OFFSET);  in clk_cpu_on_set_rate()
138 	reg = readl(cpuclk->pmu_dfs);  in clk_cpu_on_set_rate()
141 	writel(reg, cpuclk->pmu_dfs);  in clk_cpu_on_set_rate()
143 	reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET);  in clk_cpu_on_set_rate()
146 	writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET);  in clk_cpu_on_set_rate()
148 	return mvebu_pmsu_dfs_request(cpuclk->cpu);  in clk_cpu_on_set_rate()
154 	if (__clk_is_enabled(hwclk->clk))  in clk_cpu_set_rate()
172 	int cpu;  in of_cpu_clk_setup()  local
175 		pr_err("%s: clock-complex base register not set\n",  in of_cpu_clk_setup()
181 		pr_warn("%s: pmu-dfs base register not set, dynamic frequency scaling not available\n",  in of_cpu_clk_setup()
192 	for_each_possible_cpu(cpu) {  in of_cpu_clk_setup()
200 		sprintf(clk_name, "cpu%d", cpu);  in of_cpu_clk_setup()
202 		cpuclk[cpu].parent_name = of_clk_get_parent_name(node, 0);  in of_cpu_clk_setup()
203 		cpuclk[cpu].clk_name = clk_name;  in of_cpu_clk_setup()
204 		cpuclk[cpu].cpu = cpu;  in of_cpu_clk_setup()
205 		cpuclk[cpu].reg_base = clock_complex_base;  in of_cpu_clk_setup()
207 			cpuclk[cpu].pmu_dfs = pmu_dfs_base + 4 * cpu;  in of_cpu_clk_setup()
208 		cpuclk[cpu].hw.init = &init;  in of_cpu_clk_setup()
210 		init.name = cpuclk[cpu].clk_name;  in of_cpu_clk_setup()
213 		init.parent_names = &cpuclk[cpu].parent_name;  in of_cpu_clk_setup()
216 		clk = clk_register(NULL, &cpuclk[cpu].hw);  in of_cpu_clk_setup()
219 		clks[cpu] = clk;  in of_cpu_clk_setup()
228 	while(ncpus--)  in of_cpu_clk_setup()
236 CLK_OF_DECLARE(armada_xp_cpu_clock, "marvell,armada-xp-cpu-clock",
244 CLK_OF_DECLARE(mv98dx3236_cpu_clock, "marvell,mv98dx3236-cpu-clock",