1 // SPDX-License-Identifier: GPL-2.0
3  * Marvell EBU SoC common clock handling
7  * Gregory CLEMENT <gregory.clement@free-electrons.com>
16 #include <linux/clk-provider.h>
38  * This function can be used by the Kirkwood, the Armada 370, the
39  * Armada XP and the Armada 375 SoC. The name of the function was
67 	if ((high_bound - low_bound) <= 0)  in kirkwood_fix_sscg_deviation()
72 	 * Spread percentage = 1/96 * (H - L) / H  in kirkwood_fix_sscg_deviation()
83 	freq_swing_half = (((u64)high_bound - (u64)low_bound)  in kirkwood_fix_sscg_deviation()
89 		system_clk -= freq_swing_half;  in kirkwood_fix_sscg_deviation()
120 	/* Allocate struct for TCLK, cpu clk, and core ratio clocks */  in mvebu_coreclk_setup()
121 	clk_data.clk_num = 2 + desc->num_ratios;  in mvebu_coreclk_setup()
123 	/* One more clock for the optional refclk */  in mvebu_coreclk_setup()
124 	if (desc->get_refclk_freq)  in mvebu_coreclk_setup()
135 	of_property_read_string_index(np, "clock-output-names", 0,  in mvebu_coreclk_setup()
137 	rate = desc->get_tclk_freq(base);  in mvebu_coreclk_setup()
142 	/* Register CPU clock */  in mvebu_coreclk_setup()
143 	of_property_read_string_index(np, "clock-output-names", 1,  in mvebu_coreclk_setup()
145 	rate = desc->get_cpu_freq(base);  in mvebu_coreclk_setup()
147 	if (desc->is_sscg_enabled && desc->fix_sscg_deviation  in mvebu_coreclk_setup()
148 		&& desc->is_sscg_enabled(base))  in mvebu_coreclk_setup()
149 		rate = desc->fix_sscg_deviation(rate);  in mvebu_coreclk_setup()
155 	/* Register fixed-factor clocks derived from CPU clock */  in mvebu_coreclk_setup()
156 	for (n = 0; n < desc->num_ratios; n++) {  in mvebu_coreclk_setup()
157 		const char *rclk_name = desc->ratios[n].name;  in mvebu_coreclk_setup()
160 		of_property_read_string_index(np, "clock-output-names",  in mvebu_coreclk_setup()
162 		desc->get_clk_ratio(base, desc->ratios[n].id, &mult, &div);  in mvebu_coreclk_setup()
169 	if (desc->get_refclk_freq) {  in mvebu_coreclk_setup()
171 		of_property_read_string_index(np, "clock-output-names",  in mvebu_coreclk_setup()
172 					      2 + desc->num_ratios, &name);  in mvebu_coreclk_setup()
173 		rate = desc->get_refclk_freq(base);  in mvebu_coreclk_setup()
174 		clk_data.clks[2 + desc->num_ratios] =  in mvebu_coreclk_setup()
176 		WARN_ON(IS_ERR(clk_data.clks[2 + desc->num_ratios]));  in mvebu_coreclk_setup()
186  * Clock Gating Control
206 	if (clkspec->args_count < 1)  in clk_gating_get_src()
207 		return ERR_PTR(-EINVAL);  in clk_gating_get_src()
209 	for (n = 0; n < ctrl->num_gates; n++) {  in clk_gating_get_src()
211 			to_clk_gate(__clk_get_hw(ctrl->gates[n]));  in clk_gating_get_src()
212 		if (clkspec->args[0] == gate->bit_idx)  in clk_gating_get_src()
213 			return ctrl->gates[n];  in clk_gating_get_src()
215 	return ERR_PTR(-ENODEV);  in clk_gating_get_src()
220 	ctrl->saved_reg = readl(ctrl->base);  in mvebu_clk_gating_suspend()
226 	writel(ctrl->saved_reg, ctrl->base);  in mvebu_clk_gating_resume()
243 		pr_err("mvebu-clk-gating: cannot instantiate more than one gateable clock device\n");  in mvebu_clk_gating_setup()
262 	ctrl->lock = &ctrl_gating_lock;  in mvebu_clk_gating_setup()
264 	ctrl->base = base;  in mvebu_clk_gating_setup()
266 	/* Count, allocate, and register clock gates */  in mvebu_clk_gating_setup()
270 	ctrl->num_gates = n;  in mvebu_clk_gating_setup()
271 	ctrl->gates = kcalloc(ctrl->num_gates, sizeof(*ctrl->gates),  in mvebu_clk_gating_setup()
273 	if (WARN_ON(!ctrl->gates))  in mvebu_clk_gating_setup()
276 	for (n = 0; n < ctrl->num_gates; n++) {  in mvebu_clk_gating_setup()
279 		ctrl->gates[n] = clk_register_gate(NULL, desc[n].name, parent,  in mvebu_clk_gating_setup()
281 					0, ctrl->lock);  in mvebu_clk_gating_setup()
282 		WARN_ON(IS_ERR(ctrl->gates[n]));  in mvebu_clk_gating_setup()