Lines Matching +full:armada +full:- +full:xp +full:- +full:cpu +full:- +full:clock
1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe driver for Marvell Armada 370 and Armada XP SoCs
5 * Author: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
27 #include "../pci-bridge-emul.h"
40 #define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
130 writel(val, port->base + reg); in mvebu_writel()
135 return readl(port->base + reg); in mvebu_readl()
140 return port->io_target != -1 && port->io_attr != -1; in mvebu_has_ioport()
199 * BAR[0] -> internal registers (needed for MSI)
200 * BAR[1] -> covers all DRAM banks
201 * BAR[2] -> Disabled
202 * WIN[0-3] -> DRAM bank[0-3]
217 for (i = 0; i < dram->num_cs; i++) { in mvebu_pcie_setup_wins()
218 const struct mbus_dram_window *cs = dram->cs + i; in mvebu_pcie_setup_wins()
220 mvebu_writel(port, cs->base & 0xffff0000, in mvebu_pcie_setup_wins()
224 ((cs->size - 1) & 0xffff0000) | in mvebu_pcie_setup_wins()
225 (cs->mbus_attr << 8) | in mvebu_pcie_setup_wins()
226 (dram->mbus_dram_target_id << 4) | 1, in mvebu_pcie_setup_wins()
229 size += cs->size; in mvebu_pcie_setup_wins()
233 if ((size & (size - 1)) != 0) in mvebu_pcie_setup_wins()
237 mvebu_writel(port, dram->cs[0].base, PCIE_BAR_LO_OFF(1)); in mvebu_pcie_setup_wins()
239 mvebu_writel(port, ((size - 1) & 0xffff0000) | 1, in mvebu_pcie_setup_wins()
245 mvebu_writel(port, round_down(port->regs.start, SZ_1M), PCIE_BAR_LO_OFF(0)); in mvebu_pcie_setup_wins()
261 * as read-only but this mvebu controller has it as read-write and must in mvebu_pcie_setup_hw()
267 lnkcap |= FIELD_PREP(PCI_EXP_LNKCAP_MLW, port->is_x4 ? 4 : 1); in mvebu_pcie_setup_hw()
283 * Moreover Type 0 BAR registers (ranges 0x10 - 0x28 and 0x30 - 0x34) in mvebu_pcie_setup_hw()
311 if (port->slot_power_limit_value) { in mvebu_pcie_setup_hw()
312 sspl |= port->slot_power_limit_value << PCIE_SSPL_VALUE_SHIFT; in mvebu_pcie_setup_hw()
313 sspl |= port->slot_power_limit_scale << PCIE_SSPL_SCALE_SHIFT; in mvebu_pcie_setup_hw()
325 if (port->intx_irq > 0) in mvebu_pcie_setup_hw()
351 struct mvebu_pcie *pcie = bus->sysdata; in mvebu_pcie_child_rd_conf()
362 conf_data = port->base + PCIE_CONF_DATA_OFF; in mvebu_pcie_child_rd_conf()
364 mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where), in mvebu_pcie_child_rd_conf()
387 struct mvebu_pcie *pcie = bus->sysdata; in mvebu_pcie_child_wr_conf()
398 conf_data = port->base + PCIE_CONF_DATA_OFF; in mvebu_pcie_child_wr_conf()
400 mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where), in mvebu_pcie_child_wr_conf()
433 size_t sz = 1 << (fls(size) - 1); in mvebu_pcie_del_windows()
437 size -= sz; in mvebu_pcie_del_windows()
455 size_t sz = 1 << (fls(size) - 1); in mvebu_pcie_add_windows()
461 phys_addr_t end = base + sz - 1; in mvebu_pcie_add_windows()
463 dev_err(&port->pcie->pdev->dev, in mvebu_pcie_add_windows()
464 "Could not create MBus window at [mem %pa-%pa]: %d\n", in mvebu_pcie_add_windows()
466 mvebu_pcie_del_windows(port, base - size_mapped, in mvebu_pcie_add_windows()
471 size -= sz; in mvebu_pcie_add_windows()
488 if (desired->base == cur->base && desired->remap == cur->remap && in mvebu_pcie_set_window()
489 desired->size == cur->size) in mvebu_pcie_set_window()
492 if (cur->size != 0) { in mvebu_pcie_set_window()
493 mvebu_pcie_del_windows(port, cur->base, cur->size); in mvebu_pcie_set_window()
494 cur->size = 0; in mvebu_pcie_set_window()
495 cur->base = 0; in mvebu_pcie_set_window()
504 if (desired->size == 0) in mvebu_pcie_set_window()
507 ret = mvebu_pcie_add_windows(port, target, attribute, desired->base, in mvebu_pcie_set_window()
508 desired->size, desired->remap); in mvebu_pcie_set_window()
510 cur->size = 0; in mvebu_pcie_set_window()
511 cur->base = 0; in mvebu_pcie_set_window()
522 struct pci_bridge_emul_conf *conf = &port->bridge.conf; in mvebu_pcie_handle_iobase_change()
525 if (conf->iolimit < conf->iobase || in mvebu_pcie_handle_iobase_change()
526 le16_to_cpu(conf->iolimitupper) < le16_to_cpu(conf->iobaseupper)) in mvebu_pcie_handle_iobase_change()
527 return mvebu_pcie_set_window(port, port->io_target, port->io_attr, in mvebu_pcie_handle_iobase_change()
528 &desired, &port->iowin); in mvebu_pcie_handle_iobase_change()
531 * We read the PCI-to-PCI bridge emulated registers, and in mvebu_pcie_handle_iobase_change()
533 * window to setup, according to the PCI-to-PCI bridge in mvebu_pcie_handle_iobase_change()
534 * specifications. iobase is the bus address, port->iowin_base in mvebu_pcie_handle_iobase_change()
535 * is the CPU address. in mvebu_pcie_handle_iobase_change()
537 desired.remap = ((conf->iobase & 0xF0) << 8) | in mvebu_pcie_handle_iobase_change()
538 (le16_to_cpu(conf->iobaseupper) << 16); in mvebu_pcie_handle_iobase_change()
539 desired.base = port->pcie->io.start + desired.remap; in mvebu_pcie_handle_iobase_change()
540 desired.size = ((0xFFF | ((conf->iolimit & 0xF0) << 8) | in mvebu_pcie_handle_iobase_change()
541 (le16_to_cpu(conf->iolimitupper) << 16)) - in mvebu_pcie_handle_iobase_change()
545 return mvebu_pcie_set_window(port, port->io_target, port->io_attr, &desired, in mvebu_pcie_handle_iobase_change()
546 &port->iowin); in mvebu_pcie_handle_iobase_change()
552 struct pci_bridge_emul_conf *conf = &port->bridge.conf; in mvebu_pcie_handle_membase_change()
555 if (le16_to_cpu(conf->memlimit) < le16_to_cpu(conf->membase)) in mvebu_pcie_handle_membase_change()
556 return mvebu_pcie_set_window(port, port->mem_target, port->mem_attr, in mvebu_pcie_handle_membase_change()
557 &desired, &port->memwin); in mvebu_pcie_handle_membase_change()
560 * We read the PCI-to-PCI bridge emulated registers, and in mvebu_pcie_handle_membase_change()
562 * window to setup, according to the PCI-to-PCI bridge in mvebu_pcie_handle_membase_change()
565 desired.base = ((le16_to_cpu(conf->membase) & 0xFFF0) << 16); in mvebu_pcie_handle_membase_change()
566 desired.size = (((le16_to_cpu(conf->memlimit) & 0xFFF0) << 16) | 0xFFFFF) - in mvebu_pcie_handle_membase_change()
569 return mvebu_pcie_set_window(port, port->mem_target, port->mem_attr, &desired, in mvebu_pcie_handle_membase_change()
570 &port->memwin); in mvebu_pcie_handle_membase_change()
577 struct mvebu_pcie_port *port = bridge->data; in mvebu_pci_bridge_emul_base_conf_read()
590 __le32 *cfgspace = (__le32 *)&bridge->conf; in mvebu_pci_bridge_emul_base_conf_read()
604 __le32 *cfgspace = (__le32 *)&bridge->conf; in mvebu_pci_bridge_emul_base_conf_read()
625 struct mvebu_pcie_port *port = bridge->data; in mvebu_pci_bridge_emul_pcie_conf_read()
638 * PCIe requires that the Clock Power Management capability bit in mvebu_pci_bridge_emul_pcie_conf_read()
639 * is hard-wired to zero for downstream ports but HW returns 1. in mvebu_pci_bridge_emul_pcie_conf_read()
655 u16 slotctl = le16_to_cpu(bridge->pcie_conf.slotctl); in mvebu_pci_bridge_emul_pcie_conf_read()
656 u16 slotsta = le16_to_cpu(bridge->pcie_conf.slotsta); in mvebu_pci_bridge_emul_pcie_conf_read()
663 if (!port->slot_power_limit_value) in mvebu_pci_bridge_emul_pcie_conf_read()
667 /* This callback is 32-bit and in high bits is slot status. */ in mvebu_pci_bridge_emul_pcie_conf_read()
700 struct mvebu_pcie_port *port = bridge->data; in mvebu_pci_bridge_emul_ext_conf_read()
731 struct mvebu_pcie_port *port = bridge->data; in mvebu_pci_bridge_emul_base_conf_write()
732 struct pci_bridge_emul_conf *conf = &bridge->conf; in mvebu_pci_bridge_emul_base_conf_write()
743 conf->iobase &= ~0xf0; in mvebu_pci_bridge_emul_base_conf_write()
744 conf->iolimit &= ~0xf0; in mvebu_pci_bridge_emul_base_conf_write()
745 conf->iobase |= 0xf0; in mvebu_pci_bridge_emul_base_conf_write()
746 conf->iobaseupper = cpu_to_le16(0x0000); in mvebu_pci_bridge_emul_base_conf_write()
747 conf->iolimitupper = cpu_to_le16(0x0000); in mvebu_pci_bridge_emul_base_conf_write()
754 conf->membase = cpu_to_le16(le16_to_cpu(conf->membase) & ~0xfff0); in mvebu_pci_bridge_emul_base_conf_write()
755 conf->memlimit = cpu_to_le16(le16_to_cpu(conf->memlimit) & ~0xfff0); in mvebu_pci_bridge_emul_base_conf_write()
756 conf->membase = cpu_to_le16(le16_to_cpu(conf->membase) | 0xfff0); in mvebu_pci_bridge_emul_base_conf_write()
764 conf->iobase &= ~0xf0; in mvebu_pci_bridge_emul_base_conf_write()
765 conf->iolimit &= ~0xf0; in mvebu_pci_bridge_emul_base_conf_write()
766 conf->iobase |= 0xf0; in mvebu_pci_bridge_emul_base_conf_write()
767 conf->iobaseupper = cpu_to_le16(0x0000); in mvebu_pci_bridge_emul_base_conf_write()
768 conf->iolimitupper = cpu_to_le16(0x0000); in mvebu_pci_bridge_emul_base_conf_write()
774 mvebu_pcie_set_local_bus_nr(port, conf->secondary_bus); in mvebu_pci_bridge_emul_base_conf_write()
797 struct mvebu_pcie_port *port = bridge->data; in mvebu_pci_bridge_emul_pcie_conf_write()
806 * PCIe requires that the Enable Clock Power Management bit in mvebu_pci_bridge_emul_pcie_conf_write()
807 * is hard-wired to zero for downstream ports but HW allows in mvebu_pci_bridge_emul_pcie_conf_write()
821 port->slot_power_limit_value) { in mvebu_pci_bridge_emul_pcie_conf_write()
834 * is read-only and can be cleared only by writing 0b to the in mvebu_pci_bridge_emul_pcie_conf_write()
859 struct mvebu_pcie_port *port = bridge->data; in mvebu_pci_bridge_emul_ext_conf_write()
897 * Initialize the configuration space of the PCI-to-PCI bridge
903 struct pci_bridge_emul *bridge = &port->bridge; in mvebu_pci_bridge_emul_init()
910 bridge->conf.vendor = cpu_to_le16(dev_id & 0xffff); in mvebu_pci_bridge_emul_init()
911 bridge->conf.device = cpu_to_le16(dev_id >> 16); in mvebu_pci_bridge_emul_init()
912 bridge->conf.class_revision = cpu_to_le32(dev_rev & 0xff); in mvebu_pci_bridge_emul_init()
916 bridge->conf.iobase = PCI_IO_RANGE_TYPE_32; in mvebu_pci_bridge_emul_init()
917 bridge->conf.iolimit = PCI_IO_RANGE_TYPE_32; in mvebu_pci_bridge_emul_init()
927 bridge->pcie_conf.cap = cpu_to_le16(pcie_cap_ver | PCI_EXP_FLAGS_SLOT); in mvebu_pci_bridge_emul_init()
940 bridge->pcie_conf.slotcap = cpu_to_le32( in mvebu_pci_bridge_emul_init()
941 FIELD_PREP(PCI_EXP_SLTCAP_SPLV, port->slot_power_limit_value) | in mvebu_pci_bridge_emul_init()
942 FIELD_PREP(PCI_EXP_SLTCAP_SPLS, port->slot_power_limit_scale) | in mvebu_pci_bridge_emul_init()
943 FIELD_PREP(PCI_EXP_SLTCAP_PSN, port->port+1)); in mvebu_pci_bridge_emul_init()
944 bridge->pcie_conf.slotsta = cpu_to_le16(PCI_EXP_SLTSTA_PDS); in mvebu_pci_bridge_emul_init()
946 bridge->subsystem_vendor_id = ssdev_id & 0xffff; in mvebu_pci_bridge_emul_init()
947 bridge->subsystem_id = ssdev_id >> 16; in mvebu_pci_bridge_emul_init()
948 bridge->has_pcie = true; in mvebu_pci_bridge_emul_init()
949 bridge->pcie_start = PCIE_CAP_PCIEXP; in mvebu_pci_bridge_emul_init()
950 bridge->data = port; in mvebu_pci_bridge_emul_init()
951 bridge->ops = &mvebu_pci_bridge_emul_ops; in mvebu_pci_bridge_emul_init()
958 return sys->private_data; in sys_to_pcie()
967 for (i = 0; i < pcie->nports; i++) { in mvebu_pcie_find_port()
968 struct mvebu_pcie_port *port = &pcie->ports[i]; in mvebu_pcie_find_port()
970 if (!port->base) in mvebu_pcie_find_port()
973 if (bus->number == 0 && port->devfn == devfn) in mvebu_pcie_find_port()
975 if (bus->number != 0 && in mvebu_pcie_find_port()
976 bus->number >= port->bridge.conf.secondary_bus && in mvebu_pcie_find_port()
977 bus->number <= port->bridge.conf.subordinate_bus) in mvebu_pcie_find_port()
988 struct mvebu_pcie *pcie = bus->sysdata; in mvebu_pcie_wr_conf()
995 return pci_bridge_emul_conf_write(&port->bridge, where, size, val); in mvebu_pcie_wr_conf()
1002 struct mvebu_pcie *pcie = bus->sysdata; in mvebu_pcie_rd_conf()
1009 return pci_bridge_emul_conf_read(&port->bridge, where, size, val); in mvebu_pcie_rd_conf()
1019 struct mvebu_pcie_port *port = d->domain->host_data; in mvebu_pcie_intx_irq_mask()
1024 raw_spin_lock_irqsave(&port->irq_lock, flags); in mvebu_pcie_intx_irq_mask()
1028 raw_spin_unlock_irqrestore(&port->irq_lock, flags); in mvebu_pcie_intx_irq_mask()
1033 struct mvebu_pcie_port *port = d->domain->host_data; in mvebu_pcie_intx_irq_unmask()
1038 raw_spin_lock_irqsave(&port->irq_lock, flags); in mvebu_pcie_intx_irq_unmask()
1042 raw_spin_unlock_irqrestore(&port->irq_lock, flags); in mvebu_pcie_intx_irq_unmask()
1046 .name = "mvebu-INTx",
1054 struct mvebu_pcie_port *port = h->host_data; in mvebu_pcie_intx_irq_map()
1070 struct device *dev = &port->pcie->pdev->dev; in mvebu_pcie_init_irq_domain()
1073 raw_spin_lock_init(&port->irq_lock); in mvebu_pcie_init_irq_domain()
1075 pcie_intc_node = of_get_next_child(port->dn, NULL); in mvebu_pcie_init_irq_domain()
1077 dev_err(dev, "No PCIe Intc node found for %s\n", port->name); in mvebu_pcie_init_irq_domain()
1078 return -ENODEV; in mvebu_pcie_init_irq_domain()
1081 port->intx_irq_domain = irq_domain_create_linear(of_fwnode_handle(pcie_intc_node), in mvebu_pcie_init_irq_domain()
1085 if (!port->intx_irq_domain) { in mvebu_pcie_init_irq_domain()
1086 dev_err(dev, "Failed to get INTx IRQ domain for %s\n", port->name); in mvebu_pcie_init_irq_domain()
1087 return -ENOMEM; in mvebu_pcie_init_irq_domain()
1097 struct device *dev = &port->pcie->pdev->dev; in mvebu_pcie_irq_handler()
1112 if (generic_handle_domain_irq(port->intx_irq_domain, i) == -EINVAL) in mvebu_pcie_irq_handler()
1122 if (dev->bus->number == 0) in mvebu_pcie_map_irq()
1134 if (dev->bus->number != 0) in mvebu_pcie_align_resource()
1138 * On the PCI-to-PCI bridge side, the I/O windows must have at in mvebu_pcie_align_resource()
1148 if (res->flags & IORESOURCE_IO) in mvebu_pcie_align_resource()
1151 else if (res->flags & IORESOURCE_MEM) in mvebu_pcie_align_resource()
1164 ret = of_address_to_resource(np, 0, &port->regs); in mvebu_pcie_map_registers()
1168 return devm_ioremap_resource(&pdev->dev, &port->regs); in mvebu_pcie_map_registers()
1185 *tgt = -1; in mvebu_get_tgt_attr()
1186 *attr = -1; in mvebu_get_tgt_attr()
1189 return -EINVAL; in mvebu_get_tgt_attr()
1209 return -ENOENT; in mvebu_get_tgt_attr()
1218 for (i = 0; i < pcie->nports; i++) { in mvebu_pcie_suspend()
1219 struct mvebu_pcie_port *port = pcie->ports + i; in mvebu_pcie_suspend()
1220 if (!port->base) in mvebu_pcie_suspend()
1222 port->saved_pcie_stat = mvebu_readl(port, PCIE_STAT_OFF); in mvebu_pcie_suspend()
1234 for (i = 0; i < pcie->nports; i++) { in mvebu_pcie_resume()
1235 struct mvebu_pcie_port *port = pcie->ports + i; in mvebu_pcie_resume()
1236 if (!port->base) in mvebu_pcie_resume()
1238 mvebu_writel(port, port->saved_pcie_stat, PCIE_STAT_OFF); in mvebu_pcie_resume()
1249 clk_put(port->clk); in mvebu_pcie_port_clk_put()
1255 struct device *dev = &pcie->pdev->dev; in mvebu_pcie_parse_port()
1260 port->pcie = pcie; in mvebu_pcie_parse_port()
1262 if (of_property_read_u32(child, "marvell,pcie-port", &port->port)) { in mvebu_pcie_parse_port()
1263 dev_warn(dev, "ignoring %pOF, missing pcie-port property\n", in mvebu_pcie_parse_port()
1268 if (of_property_read_u32(child, "marvell,pcie-lane", &port->lane)) in mvebu_pcie_parse_port()
1269 port->lane = 0; in mvebu_pcie_parse_port()
1271 if (!of_property_read_u32(child, "num-lanes", &num_lanes) && num_lanes == 4) in mvebu_pcie_parse_port()
1272 port->is_x4 = true; in mvebu_pcie_parse_port()
1274 port->name = devm_kasprintf(dev, GFP_KERNEL, "pcie%d.%d", port->port, in mvebu_pcie_parse_port()
1275 port->lane); in mvebu_pcie_parse_port()
1276 if (!port->name) { in mvebu_pcie_parse_port()
1277 ret = -ENOMEM; in mvebu_pcie_parse_port()
1281 port->devfn = of_pci_get_devfn(child); in mvebu_pcie_parse_port()
1282 if (port->devfn < 0) in mvebu_pcie_parse_port()
1284 if (PCI_FUNC(port->devfn) != 0) { in mvebu_pcie_parse_port()
1286 port->name); in mvebu_pcie_parse_port()
1290 ret = mvebu_get_tgt_attr(dev->of_node, port->devfn, IORESOURCE_MEM, in mvebu_pcie_parse_port()
1291 &port->mem_target, &port->mem_attr); in mvebu_pcie_parse_port()
1294 port->name); in mvebu_pcie_parse_port()
1298 if (resource_size(&pcie->io) != 0) { in mvebu_pcie_parse_port()
1299 mvebu_get_tgt_attr(dev->of_node, port->devfn, IORESOURCE_IO, in mvebu_pcie_parse_port()
1300 &port->io_target, &port->io_attr); in mvebu_pcie_parse_port()
1302 port->io_target = -1; in mvebu_pcie_parse_port()
1303 port->io_attr = -1; in mvebu_pcie_parse_port()
1310 port->intx_irq = of_irq_get_byname(child, "intx"); in mvebu_pcie_parse_port()
1311 if (port->intx_irq == -EPROBE_DEFER) { in mvebu_pcie_parse_port()
1312 ret = port->intx_irq; in mvebu_pcie_parse_port()
1315 if (port->intx_irq <= 0) { in mvebu_pcie_parse_port()
1318 port->name, child); in mvebu_pcie_parse_port()
1321 port->reset_name = devm_kasprintf(dev, GFP_KERNEL, "%s-reset", in mvebu_pcie_parse_port()
1322 port->name); in mvebu_pcie_parse_port()
1323 if (!port->reset_name) { in mvebu_pcie_parse_port()
1324 ret = -ENOMEM; in mvebu_pcie_parse_port()
1328 port->reset_gpio = devm_fwnode_gpiod_get(dev, of_fwnode_handle(child), in mvebu_pcie_parse_port()
1330 port->name); in mvebu_pcie_parse_port()
1331 ret = PTR_ERR_OR_ZERO(port->reset_gpio); in mvebu_pcie_parse_port()
1333 if (ret != -ENOENT) in mvebu_pcie_parse_port()
1336 port->reset_gpio = NULL; in mvebu_pcie_parse_port()
1337 devm_kfree(dev, port->reset_name); in mvebu_pcie_parse_port()
1338 port->reset_name = NULL; in mvebu_pcie_parse_port()
1342 &port->slot_power_limit_value, in mvebu_pcie_parse_port()
1343 &port->slot_power_limit_scale); in mvebu_pcie_parse_port()
1346 port->name, in mvebu_pcie_parse_port()
1350 port->clk = of_clk_get_by_name(child, NULL); in mvebu_pcie_parse_port()
1351 if (IS_ERR(port->clk)) { in mvebu_pcie_parse_port()
1352 dev_err(dev, "%s: cannot get clock\n", port->name); in mvebu_pcie_parse_port()
1366 devm_kfree(dev, port->reset_name); in mvebu_pcie_parse_port()
1367 port->reset_name = NULL; in mvebu_pcie_parse_port()
1368 devm_kfree(dev, port->name); in mvebu_pcie_parse_port()
1369 port->name = NULL; in mvebu_pcie_parse_port()
1377 * prior to releasing PERST. See table 2-4 in section 2.6.2 AC Specifications
1384 ret = clk_prepare_enable(port->clk); in mvebu_pcie_powerup()
1388 if (port->reset_gpio) { in mvebu_pcie_powerup()
1391 of_property_read_u32(port->dn, "reset-delay-us", in mvebu_pcie_powerup()
1396 gpiod_set_value_cansleep(port->reset_gpio, 0); in mvebu_pcie_powerup()
1409 gpiod_set_value_cansleep(port->reset_gpio, 1); in mvebu_pcie_powerdown()
1411 clk_disable_unprepare(port->clk); in mvebu_pcie_powerdown()
1421 struct device *dev = &pcie->pdev->dev; in mvebu_pcie_parse_request_resources()
1426 mvebu_mbus_get_pcie_mem_aperture(&pcie->mem); in mvebu_pcie_parse_request_resources()
1427 if (resource_size(&pcie->mem) == 0) { in mvebu_pcie_parse_request_resources()
1429 return -EINVAL; in mvebu_pcie_parse_request_resources()
1432 pcie->mem.name = "PCI MEM"; in mvebu_pcie_parse_request_resources()
1433 pci_add_resource(&bridge->windows, &pcie->mem); in mvebu_pcie_parse_request_resources()
1434 ret = devm_request_resource(dev, &iomem_resource, &pcie->mem); in mvebu_pcie_parse_request_resources()
1439 mvebu_mbus_get_pcie_io_aperture(&pcie->io); in mvebu_pcie_parse_request_resources()
1441 if (resource_size(&pcie->io) != 0) { in mvebu_pcie_parse_request_resources()
1442 pcie->realio.flags = pcie->io.flags; in mvebu_pcie_parse_request_resources()
1443 pcie->realio.start = PCIBIOS_MIN_IO; in mvebu_pcie_parse_request_resources()
1444 pcie->realio.end = min_t(resource_size_t, in mvebu_pcie_parse_request_resources()
1445 IO_SPACE_LIMIT - SZ_64K, in mvebu_pcie_parse_request_resources()
1446 resource_size(&pcie->io) - 1); in mvebu_pcie_parse_request_resources()
1447 pcie->realio.name = "PCI I/O"; in mvebu_pcie_parse_request_resources()
1449 ret = devm_pci_remap_iospace(dev, &pcie->realio, pcie->io.start); in mvebu_pcie_parse_request_resources()
1453 pci_add_resource(&bridge->windows, &pcie->realio); in mvebu_pcie_parse_request_resources()
1454 ret = devm_request_resource(dev, &ioport_resource, &pcie->realio); in mvebu_pcie_parse_request_resources()
1464 struct device *dev = &pdev->dev; in mvebu_pcie_probe()
1467 struct device_node *np = dev->of_node; in mvebu_pcie_probe()
1473 return -ENOMEM; in mvebu_pcie_probe()
1476 pcie->pdev = pdev; in mvebu_pcie_probe()
1485 pcie->ports = devm_kcalloc(dev, num, sizeof(*pcie->ports), GFP_KERNEL); in mvebu_pcie_probe()
1486 if (!pcie->ports) in mvebu_pcie_probe()
1487 return -ENOMEM; in mvebu_pcie_probe()
1491 struct mvebu_pcie_port *port = &pcie->ports[i]; in mvebu_pcie_probe()
1501 port->dn = child; in mvebu_pcie_probe()
1504 pcie->nports = i; in mvebu_pcie_probe()
1506 for (i = 0; i < pcie->nports; i++) { in mvebu_pcie_probe()
1507 struct mvebu_pcie_port *port = &pcie->ports[i]; in mvebu_pcie_probe()
1508 int irq = port->intx_irq; in mvebu_pcie_probe()
1510 child = port->dn; in mvebu_pcie_probe()
1518 port->base = mvebu_pcie_map_registers(pdev, child, port); in mvebu_pcie_probe()
1519 if (IS_ERR(port->base)) { in mvebu_pcie_probe()
1520 dev_err(dev, "%s: cannot map registers\n", port->name); in mvebu_pcie_probe()
1521 port->base = NULL; in mvebu_pcie_probe()
1529 port->name); in mvebu_pcie_probe()
1530 devm_iounmap(dev, port->base); in mvebu_pcie_probe()
1531 port->base = NULL; in mvebu_pcie_probe()
1540 port->name); in mvebu_pcie_probe()
1541 pci_bridge_emul_cleanup(&port->bridge); in mvebu_pcie_probe()
1542 devm_iounmap(dev, port->base); in mvebu_pcie_probe()
1543 port->base = NULL; in mvebu_pcie_probe()
1560 * peer-to-peer support between PCIe devices behind different in mvebu_pcie_probe()
1569 * host bridges into one bus zero, like in classic multi-port in mvebu_pcie_probe()
1572 * This means that pci-mvebu.c driver provides "virtual" bus 0 in mvebu_pcie_probe()
1589 * available (applies for pre-XP PCIe controllers) then Type 0 in mvebu_pcie_probe()
1609 * option 2. is not available on pre-XP PCIe controllers. Hence in mvebu_pcie_probe()
1632 bridge->sysdata = pcie; in mvebu_pcie_probe()
1633 bridge->ops = &mvebu_pcie_ops; in mvebu_pcie_probe()
1634 bridge->child_ops = &mvebu_pcie_child_ops; in mvebu_pcie_probe()
1635 bridge->align_resource = mvebu_pcie_align_resource; in mvebu_pcie_probe()
1636 bridge->map_irq = mvebu_pcie_map_irq; in mvebu_pcie_probe()
1650 pci_stop_root_bus(bridge->bus); in mvebu_pcie_remove()
1651 pci_remove_root_bus(bridge->bus); in mvebu_pcie_remove()
1654 for (i = 0; i < pcie->nports; i++) { in mvebu_pcie_remove()
1655 struct mvebu_pcie_port *port = &pcie->ports[i]; in mvebu_pcie_remove()
1656 int irq = port->intx_irq; in mvebu_pcie_remove()
1658 if (!port->base) in mvebu_pcie_remove()
1676 if (port->intx_irq_domain) in mvebu_pcie_remove()
1677 irq_domain_remove(port->intx_irq_domain); in mvebu_pcie_remove()
1680 pci_bridge_emul_cleanup(&port->bridge); in mvebu_pcie_remove()
1691 if (port->iowin.size) in mvebu_pcie_remove()
1692 mvebu_pcie_del_windows(port, port->iowin.base, port->iowin.size); in mvebu_pcie_remove()
1693 if (port->memwin.size) in mvebu_pcie_remove()
1694 mvebu_pcie_del_windows(port, port->memwin.base, port->memwin.size); in mvebu_pcie_remove()
1702 { .compatible = "marvell,armada-xp-pcie", },
1703 { .compatible = "marvell,armada-370-pcie", },
1704 { .compatible = "marvell,dove-pcie", },
1705 { .compatible = "marvell,kirkwood-pcie", },
1716 .name = "mvebu-pcie",