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/linux/drivers/gpu/drm/msm/registers/adreno/
H A Da2xx.xml11 <value name="DITHER_PIXEL" value="0"/>
12 <value name="DITHER_SUBPIXEL" value="1"/>
16 <value name="COLORX_4_4_4_4" value="0"/>
17 <value name="COLORX_1_5_5_5" value="1"/>
18 <value name="COLORX_5_6_5" value="2"/>
19 <value name="COLORX_8" value="3"/>
20 <value name="COLORX_8_8" value="4"/>
21 <value name="COLORX_8_8_8_8" value="5"/>
22 <value name="COLORX_S8_8_8_8" value="6"/>
23 <value name="COLORX_16_FLOAT" value="7"/>
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H A Da6xx.xml25 <value name="TILE6_LINEAR" value="0"/>
26 <value name="TILE6_2" value="2"/>
27 <value name="TILE6_3" value="3"/>
31 <value value="0x02" name="FMT6_A8_UNORM"/>
32 <value value="0x03" name="FMT6_8_UNORM"/>
33 <value value="0x04" name="FMT6_8_SNORM"/>
34 <value value="0x05" name="FMT6_8_UINT"/>
35 <value value="0x06" name="FMT6_8_SINT"/>
37 <value value="0x08" name="FMT6_4_4_4_4_UNORM"/>
38 <value value="0x0a" name="FMT6_5_5_5_1_UNORM"/>
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H A Da4xx.xml10 <value name="RB4_A8_UNORM" value="0x01"/>
11 <value name="RB4_R8_UNORM" value="0x02"/>
12 <value name="RB4_R8_SNORM" value="0x03"/>
13 <value name="RB4_R8_UINT" value="0x04"/>
14 <value name="RB4_R8_SINT" value="0x05"/>
16 <value name="RB4_R4G4B4A4_UNORM" value="0x08"/>
17 <value name="RB4_R5G5B5A1_UNORM" value="0x0a"/>
18 <value name="RB4_R5G6B5_UNORM" value="0x0e"/>
19 <value name="RB4_R8G8_UNORM" value="0x0f"/>
20 <value name="RB4_R8G8_SNORM" value="0x10"/>
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H A Dadreno_common.xml8 <value name="A2XX" value="2"/>
9 <value name="A3XX" value="3"/>
10 <value name="A4XX" value="4"/>
11 <value name="A5XX" value="5"/>
12 <value name="A6XX" value="6"/>
13 <value name="A7XX" value="7"/>
17 <value name="PC_DRAW_POINTS" value="0"/>
18 <value name="PC_DRAW_LINES" value="1"/>
19 <value name="PC_DRAW_TRIANGLES" value="2"/>
23 <value name="FUNC_NEVER" value="0"/>
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H A Da3xx.xml10 <value name="LINEAR" value="0"/>
11 <value name="TILE_4X4" value="1"/> <!-- "normal" case for textures -->
12 <value name="TILE_32X32" value="2"/> <!-- only used in GMEM -->
13 <value name="TILE_4X2" value="3"/> <!-- only used for CrCb -->
17 <value name="HLSQ_BLOCK_ID_TP_TEX" value="2"/>
18 <value name="HLSQ_BLOCK_ID_TP_MIPMAP" value="3"/>
19 <value name="HLSQ_BLOCK_ID_SP_VS" value="4"/>
20 <value name="HLSQ_BLOCK_ID_SP_FS" value="6"/>
24 <value name="INVALIDATE" value="1"/>
28 <value name="VFMT_32_FLOAT" value="0x0"/>
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H A Da5xx.xml10 <value value="0x02" name="RB5_A8_UNORM"/>
11 <value value="0x03" name="RB5_R8_UNORM"/>
12 <value value="0x04" name="RB5_R8_SNORM"/>
13 <value value="0x05" name="RB5_R8_UINT"/>
14 <value value="0x06" name="RB5_R8_SINT"/>
15 <value value="0x08" name="RB5_R4G4B4A4_UNORM"/>
16 <value value="0x0a" name="RB5_R5G5B5A1_UNORM"/>
17 <value value="0x0e" name="RB5_R5G6B5_UNORM"/>
18 <value value="0x0f" name="RB5_R8G8_UNORM"/>
19 <value value="0x10" name="RB5_R8G8_SNORM"/>
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/linux/tools/testing/selftests/kvm/include/x86_64/
H A Devmcs.h
/linux/drivers/gpu/drm/msm/registers/display/
H A Dmdp_common.xml11 <value name="CHROMA_FULL" value="0"/>
12 <value name="CHROMA_H2V1" value="1"/>
13 <value name="CHROMA_H1V2" value="2"/>
14 <value name="CHROMA_420" value="3"/>
18 <value name="MDP_PLANE_INTERLEAVED" value="0"/>
19 <value name="MDP_PLANE_PLANAR" value="1"/>
20 <value name="MDP_PLANE_PSEUDO_PLANAR" value="2"/>
24 <value name="STAGE_UNUSED" value="0"/>
25 <value name="STAGE_BASE" value="1"/>
26 <value name="STAGE0" value="2"/> <!-- zorder 0 -->
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/linux/drivers/video/fbdev/riva/
H A Dnvreg.h34 #define SetBF(mask,value) ((value) << (0?mask)) argument
37 #define MaskAndSetBF(var,mask,value) (var)=(((var)&(~MASKEXPAND(mask)) \ argument
38 | SetBF(mask,value)))
47 #define DEVICE_WRITE(device,reg,value) DEVICE_ACCESS(device,reg)=(value) argument
51 #define DEVICE_DEF(device,mask,value) \ argument
52 SetBF(NV_##device##_##mask,NV_##device##_##mask##_##value)
53 #define DEVICE_VALUE(device,mask,value) SetBF(NV_##device##_##mask,value) argument
56 #define PDAC_Write(reg,value) DEVICE_WRITE(PDAC,reg,value) argument
59 #define PDAC_Def(mask,value) DEVICE_DEF(PDAC,mask,value) argument
60 #define PDAC_Val(mask,value) DEVICE_VALUE(PDAC,mask,value) argument
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/linux/drivers/phy/tegra/
H A Dxusb-tegra210.c468 u32 value; in tegra210_pex_uphy_enable() local
486 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
487 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_MASK << in tegra210_pex_uphy_enable()
489 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_VAL << in tegra210_pex_uphy_enable()
491 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
493 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL5); in tegra210_pex_uphy_enable()
494 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_MASK << in tegra210_pex_uphy_enable()
496 value |= XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_VAL << in tegra210_pex_uphy_enable()
498 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL5); in tegra210_pex_uphy_enable()
500 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
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H A Dxusb-tegra186.c278 static inline void ao_writel(struct tegra186_xusb_padctl *priv, u32 value, unsigned int offset) in ao_writel() argument
280 writel(value, priv->ao_regs + offset); in ao_writel()
334 u32 value; in tegra186_utmi_enable_phy_sleepwalk() local
339 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); in tegra186_utmi_enable_phy_sleepwalk()
340 value &= ~MASTER_ENABLE; in tegra186_utmi_enable_phy_sleepwalk()
341 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); in tegra186_utmi_enable_phy_sleepwalk()
344 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); in tegra186_utmi_enable_phy_sleepwalk()
345 value |= MASTER_CFG_SEL; in tegra186_utmi_enable_phy_sleepwalk()
346 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); in tegra186_utmi_enable_phy_sleepwalk()
349 value = ao_readl(priv, XUSB_AO_USB_DEBOUNCE_DEL); in tegra186_utmi_enable_phy_sleepwalk()
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H A Dxusb-tegra124.c227 u32 value; in tegra124_xusb_padctl_enable() local
234 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); in tegra124_xusb_padctl_enable()
235 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN; in tegra124_xusb_padctl_enable()
236 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); in tegra124_xusb_padctl_enable()
240 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); in tegra124_xusb_padctl_enable()
241 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY; in tegra124_xusb_padctl_enable()
242 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); in tegra124_xusb_padctl_enable()
246 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); in tegra124_xusb_padctl_enable()
247 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN; in tegra124_xusb_padctl_enable()
248 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); in tegra124_xusb_padctl_enable()
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/linux/drivers/gpu/drm/amd/display/dc/dce110/
H A Ddce110_mem_input_v.c43 uint32_t value = 0; in set_flip_control() local
45 value = dm_read_reg( in set_flip_control()
49 set_reg_field_value(value, 1, in set_flip_control()
56 value); in set_flip_control()
64 uint32_t value = 0; in program_pri_addr_c() local
70 set_reg_field_value(value, temp, in program_pri_addr_c()
77 value); in program_pri_addr_c()
79 value = 0; in program_pri_addr_c()
83 set_reg_field_value(value, temp, in program_pri_addr_c()
90 value); in program_pri_addr_c()
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H A Ddce110_opp_regamma_v.c37 uint32_t value = dm_read_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL); in power_on_lut() local
43 value, in power_on_lut()
49 value, in power_on_lut()
56 value, in power_on_lut()
62 value, in power_on_lut()
68 dm_write_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL, value); in power_on_lut()
71 value = dm_read_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL); in power_on_lut()
72 if (get_reg_field_value(value, in power_on_lut()
75 get_reg_field_value(value, in power_on_lut()
86 uint32_t value; in set_bypass_input_gamma() local
[all …]
H A Ddce110_opp_csc_v.c52 * value = UNDERLAY_SATURATION_MAX /UNDERLAY_SATURATION_DIVIDER
127 uint32_t value = 0; in program_color_matrix_v() local
131 value, in program_color_matrix_v()
137 value, in program_color_matrix_v()
142 dm_write_reg(ctx, addr, value); in program_color_matrix_v()
145 uint32_t value = 0; in program_color_matrix_v() local
149 value, in program_color_matrix_v()
155 value, in program_color_matrix_v()
160 dm_write_reg(ctx, addr, value); in program_color_matrix_v()
163 uint32_t value = 0; in program_color_matrix_v() local
[all …]
H A Ddce110_timing_generator.c95 uint32_t value = 0; in dce110_timing_generator_is_in_vertical_blank() local
100 value = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_is_in_vertical_blank()
101 field = get_reg_field_value(value, CRTC_STATUS, CRTC_V_BLANK); in dce110_timing_generator_is_in_vertical_blank()
128 uint32_t value = 0; in dce110_timing_generator_enable_crtc() local
135 value, in dce110_timing_generator_enable_crtc()
140 dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_MASTER_UPDATE_MODE), value); in dce110_timing_generator_enable_crtc()
143 value = 0; in dce110_timing_generator_enable_crtc()
144 dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_MASTER_UPDATE_LOCK), value); in dce110_timing_generator_enable_crtc()
157 uint32_t value = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_program_blank_color() local
160 value, in dce110_timing_generator_program_blank_color()
[all …]
/linux/tools/power/x86/intel-speed-select/
H A Disst-display.c85 char *value) in format_and_print_txt() argument
102 if (header && value) { in format_and_print_txt()
104 fprintf(outf, "%s:%s\n", header, value); in format_and_print_txt()
112 static void format_and_print(FILE *outf, int level, char *header, char *value) in format_and_print() argument
119 format_and_print_txt(outf, level, header, value); in format_and_print()
139 if (value) { in format_and_print()
144 fprintf(outf, "\"%s\"", value); in format_and_print()
215 static char value[1024]; in _isst_pbf_display_information() local
221 snprintf(value, sizeof(value), "%d", in _isst_pbf_display_information()
223 format_and_print(outf, disp_level + 1, header, value); in _isst_pbf_display_information()
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/linux/drivers/media/pci/cx25821/
H A Dcx25821-medusa-video.c24 u32 value = 0; in medusa_enable_bluefield_output() local
63 value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl, &tmp); in medusa_enable_bluefield_output()
64 value &= 0xFFFFFF7F; /* clear BLUE_FIELD_EN */ in medusa_enable_bluefield_output()
66 value |= 0x00000080; /* set BLUE_FIELD_EN */ in medusa_enable_bluefield_output()
67 cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl, value); in medusa_enable_bluefield_output()
69 value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl_ns, &tmp); in medusa_enable_bluefield_output()
70 value &= 0xFFFFFF7F; in medusa_enable_bluefield_output()
72 value |= 0x00000080; /* set BLUE_FIELD_EN */ in medusa_enable_bluefield_output()
73 cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl_ns, value); in medusa_enable_bluefield_output()
80 u32 value = 0; in medusa_initialize_ntsc() local
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/linux/arch/mips/include/asm/octeon/
H A Dcvmx-fau.h57 * bit will be set. Otherwise the value of the register before
62 int64_t value:63; member
67 * bit will be set. Otherwise the value of the register before
72 int32_t value:31; member
77 * bit will be set. Otherwise the value of the register before
82 int16_t value:15; member
87 * bit will be set. Otherwise the value of the register before
92 int8_t value:7; member
97 * the error bit will be set. Otherwise the value of the
121 * @noadd: 0 = Store value is atomically added to the current value
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/linux/drivers/net/wwan/t7xx/
H A Dt7xx_dpmaif.c37 u32 value, ul_intr_enable, dl_intr_enable; in t7xx_dpmaif_init_intr() local
50 value, (value & ul_intr_enable) != ul_intr_enable, 0, in t7xx_dpmaif_init_intr()
65 value, (value & ul_intr_enable) != ul_intr_enable, 0, in t7xx_dpmaif_init_intr()
74 value = ioread32(hw_info->pcie_base + DPMAIF_AO_UL_AP_L1TIMR0); in t7xx_dpmaif_init_intr()
75 value |= DPMAIF_DL_INT_Q2APTOP | DPMAIF_DL_INT_Q2TOQ1; in t7xx_dpmaif_init_intr()
76 iowrite32(value, hw_info->pcie_base + DPMAIF_AO_UL_AP_L1TIMR0); in t7xx_dpmaif_init_intr()
85 u32 value, ul_int_que_done; in t7xx_dpmaif_mask_ulq_intr() local
94 value, (value & ul_int_que_done) == ul_int_que_done, 0, in t7xx_dpmaif_mask_ulq_intr()
99 value); in t7xx_dpmaif_mask_ulq_intr()
105 u32 value, ul_int_que_done; in t7xx_dpmaif_unmask_ulq_intr() local
[all …]
/linux/drivers/gpu/drm/bridge/
H A Dsil-sii8620.h15 /* Vendor ID Low byte, default value: 0x01 */
18 /* Vendor ID High byte, default value: 0x00 */
21 /* Device ID Low byte, default value: 0x60 */
24 /* Device ID High byte, default value: 0x86 */
27 /* Device Revision, default value: 0x10 */
30 /* OTP DBYTE510, default value: 0x00 */
33 /* System Control #1, default value: 0x00 */
44 /* System Control DPD, default value: 0x90 */
54 /* Dual link Control, default value: 0x00 */
65 /* PWD Software Reset, default value: 0x20 */
[all …]
/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwxgmac2_dma.c13 u32 value = readl(ioaddr + XGMAC_DMA_MODE); in dwxgmac2_dma_reset() local
16 writel(value | XGMAC_SWR, ioaddr + XGMAC_DMA_MODE); in dwxgmac2_dma_reset()
18 return readl_poll_timeout(ioaddr + XGMAC_DMA_MODE, value, in dwxgmac2_dma_reset()
19 !(value & XGMAC_SWR), 0, 100000); in dwxgmac2_dma_reset()
25 u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE); in dwxgmac2_dma_init() local
28 value |= XGMAC_AAL; in dwxgmac2_dma_init()
31 value |= XGMAC_EAME; in dwxgmac2_dma_init()
33 writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE); in dwxgmac2_dma_init()
40 u32 value = readl(ioaddr + XGMAC_DMA_CH_CONTROL(chan)); in dwxgmac2_dma_init_chan() local
43 value |= XGMAC_PBLx8; in dwxgmac2_dma_init_chan()
[all …]
/linux/tools/testing/selftests/bpf/test_kmods/
H A Dbpf_testmod.h27 /* BPF iter that returns *value* *n* times in a row */
29 s64 value; member
51 int (*tramp_1)(int value);
52 int (*tramp_2)(int value);
53 int (*tramp_3)(int value);
54 int (*tramp_4)(int value);
55 int (*tramp_5)(int value);
56 int (*tramp_6)(int value);
57 int (*tramp_7)(int value);
58 int (*tramp_8)(int value);
[all …]
/linux/drivers/infiniband/hw/bnxt_re/
H A Dhw_counters.c150 stats->value[BNXT_RE_TX_ATOMIC_REQ] = s->tx_atomic_req; in bnxt_re_copy_ext_stats()
151 stats->value[BNXT_RE_TX_READ_REQ] = s->tx_read_req; in bnxt_re_copy_ext_stats()
152 stats->value[BNXT_RE_TX_READ_RES] = s->tx_read_res; in bnxt_re_copy_ext_stats()
153 stats->value[BNXT_RE_TX_WRITE_REQ] = s->tx_write_req; in bnxt_re_copy_ext_stats()
154 stats->value[BNXT_RE_TX_SEND_REQ] = s->tx_send_req; in bnxt_re_copy_ext_stats()
155 stats->value[BNXT_RE_TX_ROCE_PKTS] = s->tx_roce_pkts; in bnxt_re_copy_ext_stats()
156 stats->value[BNXT_RE_TX_ROCE_BYTES] = s->tx_roce_bytes; in bnxt_re_copy_ext_stats()
157 stats->value[BNXT_RE_RX_ATOMIC_REQ] = s->rx_atomic_req; in bnxt_re_copy_ext_stats()
158 stats->value[BNXT_RE_RX_READ_REQ] = s->rx_read_req; in bnxt_re_copy_ext_stats()
159 stats->value[BNXT_RE_RX_READ_RESP] = s->rx_read_res; in bnxt_re_copy_ext_stats()
[all …]
/linux/drivers/gpu/drm/i915/
H A Di915_getparam.c23 int value = 0; in i915_getparam_ioctl() local
33 value = pdev->device; in i915_getparam_ioctl()
36 value = pdev->revision; in i915_getparam_ioctl()
39 value = to_gt(i915)->ggtt->num_fences; in i915_getparam_ioctl()
42 value = intel_overlay_available(display); in i915_getparam_ioctl()
45 value = !!intel_engine_lookup_user(i915, in i915_getparam_ioctl()
49 value = !!intel_engine_lookup_user(i915, in i915_getparam_ioctl()
53 value = !!intel_engine_lookup_user(i915, in i915_getparam_ioctl()
57 value = !!intel_engine_lookup_user(i915, in i915_getparam_ioctl()
61 value = HAS_LLC(i915); in i915_getparam_ioctl()
[all …]

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