Lines Matching full:value

10 	<value value="0x02" name="RB5_A8_UNORM"/>
11 <value value="0x03" name="RB5_R8_UNORM"/>
12 <value value="0x04" name="RB5_R8_SNORM"/>
13 <value value="0x05" name="RB5_R8_UINT"/>
14 <value value="0x06" name="RB5_R8_SINT"/>
15 <value value="0x08" name="RB5_R4G4B4A4_UNORM"/>
16 <value value="0x0a" name="RB5_R5G5B5A1_UNORM"/>
17 <value value="0x0e" name="RB5_R5G6B5_UNORM"/>
18 <value value="0x0f" name="RB5_R8G8_UNORM"/>
19 <value value="0x10" name="RB5_R8G8_SNORM"/>
20 <value value="0x11" name="RB5_R8G8_UINT"/>
21 <value value="0x12" name="RB5_R8G8_SINT"/>
22 <value value="0x15" name="RB5_R16_UNORM"/>
23 <value value="0x16" name="RB5_R16_SNORM"/>
24 <value value="0x17" name="RB5_R16_FLOAT"/>
25 <value value="0x18" name="RB5_R16_UINT"/>
26 <value value="0x19" name="RB5_R16_SINT"/>
27 <value value="0x30" name="RB5_R8G8B8A8_UNORM"/>
28 <value value="0x31" name="RB5_R8G8B8_UNORM"/>
29 <value value="0x32" name="RB5_R8G8B8A8_SNORM"/>
30 <value value="0x33" name="RB5_R8G8B8A8_UINT"/>
31 <value value="0x34" name="RB5_R8G8B8A8_SINT"/>
32 <value value="0x37" name="RB5_R10G10B10A2_UNORM"/> <!-- GL_RGB10_A2 -->
33 <value value="0x3a" name="RB5_R10G10B10A2_UINT"/> <!-- GL_RGB10_A2UI -->
34 <value value="0x42" name="RB5_R11G11B10_FLOAT"/> <!-- GL_R11F_G11F_B10F -->
35 <value value="0x43" name="RB5_R16G16_UNORM"/>
36 <value value="0x44" name="RB5_R16G16_SNORM"/>
37 <value value="0x45" name="RB5_R16G16_FLOAT"/>
38 <value value="0x46" name="RB5_R16G16_UINT"/>
39 <value value="0x47" name="RB5_R16G16_SINT"/>
40 <value value="0x4a" name="RB5_R32_FLOAT"/>
41 <value value="0x4b" name="RB5_R32_UINT"/>
42 <value value="0x4c" name="RB5_R32_SINT"/>
43 <value value="0x60" name="RB5_R16G16B16A16_UNORM"/>
44 <value value="0x61" name="RB5_R16G16B16A16_SNORM"/>
45 <value value="0x62" name="RB5_R16G16B16A16_FLOAT"/>
46 <value value="0x63" name="RB5_R16G16B16A16_UINT"/>
47 <value value="0x64" name="RB5_R16G16B16A16_SINT"/>
48 <value value="0x67" name="RB5_R32G32_FLOAT"/>
49 <value value="0x68" name="RB5_R32G32_UINT"/>
50 <value value="0x69" name="RB5_R32G32_SINT"/>
51 <value value="0x82" name="RB5_R32G32B32A32_FLOAT"/>
52 <value value="0x83" name="RB5_R32G32B32A32_UINT"/>
53 <value value="0x84" name="RB5_R32G32B32A32_SINT"/>
55 <value value="0xff" name="RB5_NONE"/>
59 <value name="TILE5_LINEAR" value="0"/>
60 <value name="TILE5_2" value="2"/>
61 <value name="TILE5_3" value="3"/>
65 <value value="0x03" name="VFMT5_8_UNORM"/>
66 <value value="0x04" name="VFMT5_8_SNORM"/>
67 <value value="0x05" name="VFMT5_8_UINT"/>
68 <value value="0x06" name="VFMT5_8_SINT"/>
70 <value value="0x0f" name="VFMT5_8_8_UNORM"/>
71 <value value="0x10" name="VFMT5_8_8_SNORM"/>
72 <value value="0x11" name="VFMT5_8_8_UINT"/>
73 <value value="0x12" name="VFMT5_8_8_SINT"/>
75 <value value="0x15" name="VFMT5_16_UNORM"/>
76 <value value="0x16" name="VFMT5_16_SNORM"/>
77 <value value="0x17" name="VFMT5_16_FLOAT"/>
78 <value value="0x18" name="VFMT5_16_UINT"/>
79 <value value="0x19" name="VFMT5_16_SINT"/>
81 <value value="0x21" name="VFMT5_8_8_8_UNORM"/>
82 <value value="0x22" name="VFMT5_8_8_8_SNORM"/>
83 <value value="0x23" name="VFMT5_8_8_8_UINT"/>
84 <value value="0x24" name="VFMT5_8_8_8_SINT"/>
86 <value value="0x30" name="VFMT5_8_8_8_8_UNORM"/>
87 <value value="0x32" name="VFMT5_8_8_8_8_SNORM"/>
88 <value value="0x33" name="VFMT5_8_8_8_8_UINT"/>
89 <value value="0x34" name="VFMT5_8_8_8_8_SINT"/>
91 <value value="0x36" name="VFMT5_10_10_10_2_UNORM"/>
92 <value value="0x39" name="VFMT5_10_10_10_2_SNORM"/>
93 <value value="0x3a" name="VFMT5_10_10_10_2_UINT"/>
94 <value value="0x3b" name="VFMT5_10_10_10_2_SINT"/>
96 <value value="0x42" name="VFMT5_11_11_10_FLOAT"/>
98 <value value="0x43" name="VFMT5_16_16_UNORM"/>
99 <value value="0x44" name="VFMT5_16_16_SNORM"/>
100 <value value="0x45" name="VFMT5_16_16_FLOAT"/>
101 <value value="0x46" name="VFMT5_16_16_UINT"/>
102 <value value="0x47" name="VFMT5_16_16_SINT"/>
104 <value value="0x48" name="VFMT5_32_UNORM"/>
105 <value value="0x49" name="VFMT5_32_SNORM"/>
106 <value value="0x4a" name="VFMT5_32_FLOAT"/>
107 <value value="0x4b" name="VFMT5_32_UINT"/>
108 <value value="0x4c" name="VFMT5_32_SINT"/>
109 <value value="0x4d" name="VFMT5_32_FIXED"/>
111 <value value="0x58" name="VFMT5_16_16_16_UNORM"/>
112 <value value="0x59" name="VFMT5_16_16_16_SNORM"/>
113 <value value="0x5a" name="VFMT5_16_16_16_FLOAT"/>
114 <value value="0x5b" name="VFMT5_16_16_16_UINT"/>
115 <value value="0x5c" name="VFMT5_16_16_16_SINT"/>
117 <value value="0x60" name="VFMT5_16_16_16_16_UNORM"/>
118 <value value="0x61" name="VFMT5_16_16_16_16_SNORM"/>
119 <value value="0x62" name="VFMT5_16_16_16_16_FLOAT"/>
120 <value value="0x63" name="VFMT5_16_16_16_16_UINT"/>
121 <value value="0x64" name="VFMT5_16_16_16_16_SINT"/>
123 <value value="0x65" name="VFMT5_32_32_UNORM"/>
124 <value value="0x66" name="VFMT5_32_32_SNORM"/>
125 <value value="0x67" name="VFMT5_32_32_FLOAT"/>
126 <value value="0x68" name="VFMT5_32_32_UINT"/>
127 <value value="0x69" name="VFMT5_32_32_SINT"/>
128 <value value="0x6a" name="VFMT5_32_32_FIXED"/>
130 <value value="0x70" name="VFMT5_32_32_32_UNORM"/>
131 <value value="0x71" name="VFMT5_32_32_32_SNORM"/>
132 <value value="0x72" name="VFMT5_32_32_32_UINT"/>
133 <value value="0x73" name="VFMT5_32_32_32_SINT"/>
134 <value value="0x74" name="VFMT5_32_32_32_FLOAT"/>
135 <value value="0x75" name="VFMT5_32_32_32_FIXED"/>
137 <value value="0x80" name="VFMT5_32_32_32_32_UNORM"/>
138 <value value="0x81" name="VFMT5_32_32_32_32_SNORM"/>
139 <value value="0x82" name="VFMT5_32_32_32_32_FLOAT"/>
140 <value value="0x83" name="VFMT5_32_32_32_32_UINT"/>
141 <value value="0x84" name="VFMT5_32_32_32_32_SINT"/>
142 <value value="0x85" name="VFMT5_32_32_32_32_FIXED"/>
144 <value value="0xff" name="VFMT5_NONE"/>
148 <value value="0x02" name="TFMT5_A8_UNORM"/>
149 <value value="0x03" name="TFMT5_8_UNORM"/>
150 <value value="0x04" name="TFMT5_8_SNORM"/>
151 <value value="0x05" name="TFMT5_8_UINT"/>
152 <value value="0x06" name="TFMT5_8_SINT"/>
153 <value value="0x08" name="TFMT5_4_4_4_4_UNORM"/>
154 <value value="0x0a" name="TFMT5_5_5_5_1_UNORM"/>
155 <value value="0x0e" name="TFMT5_5_6_5_UNORM"/>
156 <value value="0x0f" name="TFMT5_8_8_UNORM"/>
157 <value value="0x10" name="TFMT5_8_8_SNORM"/>
158 <value value="0x11" name="TFMT5_8_8_UINT"/>
159 <value value="0x12" name="TFMT5_8_8_SINT"/>
160 <value value="0x13" name="TFMT5_L8_A8_UNORM"/>
161 <value value="0x15" name="TFMT5_16_UNORM"/>
162 <value value="0x16" name="TFMT5_16_SNORM"/>
163 <value value="0x17" name="TFMT5_16_FLOAT"/>
164 <value value="0x18" name="TFMT5_16_UINT"/>
165 <value value="0x19" name="TFMT5_16_SINT"/>
166 <value value="0x30" name="TFMT5_8_8_8_8_UNORM"/>
167 <value value="0x31" name="TFMT5_8_8_8_UNORM"/>
168 <value value="0x32" name="TFMT5_8_8_8_8_SNORM"/>
169 <value value="0x33" name="TFMT5_8_8_8_8_UINT"/>
170 <value value="0x34" name="TFMT5_8_8_8_8_SINT"/>
171 <value value="0x35" name="TFMT5_9_9_9_E5_FLOAT"/>
172 <value value="0x36" name="TFMT5_10_10_10_2_UNORM"/>
173 <value value="0x3a" name="TFMT5_10_10_10_2_UINT"/>
174 <value value="0x42" name="TFMT5_11_11_10_FLOAT"/>
175 <value value="0x43" name="TFMT5_16_16_UNORM"/>
176 <value value="0x44" name="TFMT5_16_16_SNORM"/>
177 <value value="0x45" name="TFMT5_16_16_FLOAT"/>
178 <value value="0x46" name="TFMT5_16_16_UINT"/>
179 <value value="0x47" name="TFMT5_16_16_SINT"/>
180 <value value="0x4a" name="TFMT5_32_FLOAT"/>
181 <value value="0x4b" name="TFMT5_32_UINT"/>
182 <value value="0x4c" name="TFMT5_32_SINT"/>
183 <value value="0x60" name="TFMT5_16_16_16_16_UNORM"/>
184 <value value="0x61" name="TFMT5_16_16_16_16_SNORM"/>
185 <value value="0x62" name="TFMT5_16_16_16_16_FLOAT"/>
186 <value value="0x63" name="TFMT5_16_16_16_16_UINT"/>
187 <value value="0x64" name="TFMT5_16_16_16_16_SINT"/>
188 <value value="0x67" name="TFMT5_32_32_FLOAT"/>
189 <value value="0x68" name="TFMT5_32_32_UINT"/>
190 <value value="0x69" name="TFMT5_32_32_SINT"/>
191 <value value="0x72" name="TFMT5_32_32_32_UINT"/>
192 <value value="0x73" name="TFMT5_32_32_32_SINT"/>
193 <value value="0x74" name="TFMT5_32_32_32_FLOAT"/>
194 <value value="0x82" name="TFMT5_32_32_32_32_FLOAT"/>
195 <value value="0x83" name="TFMT5_32_32_32_32_UINT"/>
196 <value value="0x84" name="TFMT5_32_32_32_32_SINT"/>
197 <value value="0xa0" name="TFMT5_X8Z24_UNORM"/>
199 <value value="0xab" name="TFMT5_ETC2_RG11_UNORM"/>
200 <value value="0xac" name="TFMT5_ETC2_RG11_SNORM"/>
201 <value value="0xad" name="TFMT5_ETC2_R11_UNORM"/>
202 <value value="0xae" name="TFMT5_ETC2_R11_SNORM"/>
203 <value value="0xaf" name="TFMT5_ETC1"/>
204 <value value="0xb0" name="TFMT5_ETC2_RGB8"/>
205 <value value="0xb1" name="TFMT5_ETC2_RGBA8"/>
206 <value value="0xb2" name="TFMT5_ETC2_RGB8A1"/>
207 <value value="0xb3" name="TFMT5_DXT1"/>
208 <value value="0xb4" name="TFMT5_DXT3"/>
209 <value value="0xb5" name="TFMT5_DXT5"/>
210 <value value="0xb7" name="TFMT5_RGTC1_UNORM"/>
211 <value value="0xb8" name="TFMT5_RGTC1_SNORM"/>
212 <value value="0xbb" name="TFMT5_RGTC2_UNORM"/>
213 <value value="0xbc" name="TFMT5_RGTC2_SNORM"/>
214 <value value="0xbe" name="TFMT5_BPTC_UFLOAT"/>
215 <value value="0xbf" name="TFMT5_BPTC_FLOAT"/>
216 <value value="0xc0" name="TFMT5_BPTC"/>
217 <value value="0xc1" name="TFMT5_ASTC_4x4"/>
218 <value value="0xc2" name="TFMT5_ASTC_5x4"/>
219 <value value="0xc3" name="TFMT5_ASTC_5x5"/>
220 <value value="0xc4" name="TFMT5_ASTC_6x5"/>
221 <value value="0xc5" name="TFMT5_ASTC_6x6"/>
222 <value value="0xc6" name="TFMT5_ASTC_8x5"/>
223 <value value="0xc7" name="TFMT5_ASTC_8x6"/>
224 <value value="0xc8" name="TFMT5_ASTC_8x8"/>
225 <value value="0xc9" name="TFMT5_ASTC_10x5"/>
226 <value value="0xca" name="TFMT5_ASTC_10x6"/>
227 <value value="0xcb" name="TFMT5_ASTC_10x8"/>
228 <value value="0xcc" name="TFMT5_ASTC_10x10"/>
229 <value value="0xcd" name="TFMT5_ASTC_12x10"/>
230 <value value="0xce" name="TFMT5_ASTC_12x12"/>
232 <value value="0xff" name="TFMT5_NONE"/>
236 <value name="DEPTH5_NONE" value="0"/>
237 <value name="DEPTH5_16" value="1"/>
238 <value name="DEPTH5_24_8" value="2"/>
239 <value name="DEPTH5_32" value="4"/>
243 <value value="0" name="BLIT_MRT0"/>
244 <value value="1" name="BLIT_MRT1"/>
245 <value value="2" name="BLIT_MRT2"/>
246 <value value="3" name="BLIT_MRT3"/>
247 <value value="4" name="BLIT_MRT4"/>
248 <value value="5" name="BLIT_MRT5"/>
249 <value value="6" name="BLIT_MRT6"/>
250 <value value="7" name="BLIT_MRT7"/>
251 <value value="8" name="BLIT_ZS"/> <!-- depth or combined depth+stencil -->
252 <value value="9" name="BLIT_S"/> <!-- separate stencil -->
257 <value value="0" name="PERF_CP_ALWAYS_COUNT"/>
258 <value value="1" name="PERF_CP_BUSY_GFX_CORE_IDLE"/>
259 <value value="2" name="PERF_CP_BUSY_CYCLES"/>
260 <value value="3" name="PERF_CP_PFP_IDLE"/>
261 <value value="4" name="PERF_CP_PFP_BUSY_WORKING"/>
262 <value value="5" name="PERF_CP_PFP_STALL_CYCLES_ANY"/>
263 <value value="6" name="PERF_CP_PFP_STARVE_CYCLES_ANY"/>
264 <value value="7" name="PERF_CP_PFP_ICACHE_MISS"/>
265 <value value="8" name="PERF_CP_PFP_ICACHE_HIT"/>
266 <value value="9" name="PERF_CP_PFP_MATCH_PM4_PKT_PROFILE"/>
267 <value value="10" name="PERF_CP_ME_BUSY_WORKING"/>
268 <value value="11" name="PERF_CP_ME_IDLE"/>
269 <value value="12" name="PERF_CP_ME_STARVE_CYCLES_ANY"/>
270 <value value="13" name="PERF_CP_ME_FIFO_EMPTY_PFP_IDLE"/>
271 <value value="14" name="PERF_CP_ME_FIFO_EMPTY_PFP_BUSY"/>
272 <value value="15" name="PERF_CP_ME_FIFO_FULL_ME_BUSY"/>
273 <value value="16" name="PERF_CP_ME_FIFO_FULL_ME_NON_WORKING"/>
274 <value value="17" name="PERF_CP_ME_STALL_CYCLES_ANY"/>
275 <value value="18" name="PERF_CP_ME_ICACHE_MISS"/>
276 <value value="19" name="PERF_CP_ME_ICACHE_HIT"/>
277 <value value="20" name="PERF_CP_NUM_PREEMPTIONS"/>
278 <value value="21" name="PERF_CP_PREEMPTION_REACTION_DELAY"/>
279 <value value="22" name="PERF_CP_PREEMPTION_SWITCH_OUT_TIME"/>
280 <value value="23" name="PERF_CP_PREEMPTION_SWITCH_IN_TIME"/>
281 <value value="24" name="PERF_CP_DEAD_DRAWS_IN_BIN_RENDER"/>
282 <value value="25" name="PERF_CP_PREDICATED_DRAWS_KILLED"/>
283 <value value="26" name="PERF_CP_MODE_SWITCH"/>
284 <value value="27" name="PERF_CP_ZPASS_DONE"/>
285 <value value="28" name="PERF_CP_CONTEXT_DONE"/>
286 <value value="29" name="PERF_CP_CACHE_FLUSH"/>
287 <value value="30" name="PERF_CP_LONG_PREEMPTIONS"/>
291 <value value="0" name="PERF_RBBM_ALWAYS_COUNT"/>
292 <value value="1" name="PERF_RBBM_ALWAYS_ON"/>
293 <value value="2" name="PERF_RBBM_TSE_BUSY"/>
294 <value value="3" name="PERF_RBBM_RAS_BUSY"/>
295 <value value="4" name="PERF_RBBM_PC_DCALL_BUSY"/>
296 <value value="5" name="PERF_RBBM_PC_VSD_BUSY"/>
297 <value value="6" name="PERF_RBBM_STATUS_MASKED"/>
298 <value value="7" name="PERF_RBBM_COM_BUSY"/>
299 <value value="8" name="PERF_RBBM_DCOM_BUSY"/>
300 <value value="9" name="PERF_RBBM_VBIF_BUSY"/>
301 <value value="10" name="PERF_RBBM_VSC_BUSY"/>
302 <value value="11" name="PERF_RBBM_TESS_BUSY"/>
303 <value value="12" name="PERF_RBBM_UCHE_BUSY"/>
304 <value value="13" name="PERF_RBBM_HLSQ_BUSY"/>
308 <value value="0" name="PERF_PC_BUSY_CYCLES"/>
309 <value value="1" name="PERF_PC_WORKING_CYCLES"/>
310 <value value="2" name="PERF_PC_STALL_CYCLES_VFD"/>
311 <value value="3" name="PERF_PC_STALL_CYCLES_TSE"/>
312 <value value="4" name="PERF_PC_STALL_CYCLES_VPC"/>
313 <value value="5" name="PERF_PC_STALL_CYCLES_UCHE"/>
314 <value value="6" name="PERF_PC_STALL_CYCLES_TESS"/>
315 <value value="7" name="PERF_PC_STALL_CYCLES_TSE_ONLY"/>
316 <value value="8" name="PERF_PC_STALL_CYCLES_VPC_ONLY"/>
317 <value value="9" name="PERF_PC_PASS1_TF_STALL_CYCLES"/>
318 <value value="10" name="PERF_PC_STARVE_CYCLES_FOR_INDEX"/>
319 <value value="11" name="PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR"/>
320 <value value="12" name="PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM"/>
321 <value value="13" name="PERF_PC_STARVE_CYCLES_FOR_POSITION"/>
322 <value value="14" name="PERF_PC_STARVE_CYCLES_DI"/>
323 <value value="15" name="PERF_PC_VIS_STREAMS_LOADED"/>
324 <value value="16" name="PERF_PC_INSTANCES"/>
325 <value value="17" name="PERF_PC_VPC_PRIMITIVES"/>
326 <value value="18" name="PERF_PC_DEAD_PRIM"/>
327 <value value="19" name="PERF_PC_LIVE_PRIM"/>
328 <value value="20" name="PERF_PC_VERTEX_HITS"/>
329 <value value="21" name="PERF_PC_IA_VERTICES"/>
330 <value value="22" name="PERF_PC_IA_PRIMITIVES"/>
331 <value value="23" name="PERF_PC_GS_PRIMITIVES"/>
332 <value value="24" name="PERF_PC_HS_INVOCATIONS"/>
333 <value value="25" name="PERF_PC_DS_INVOCATIONS"/>
334 <value value="26" name="PERF_PC_VS_INVOCATIONS"/>
335 <value value="27" name="PERF_PC_GS_INVOCATIONS"/>
336 <value value="28" name="PERF_PC_DS_PRIMITIVES"/>
337 <value value="29" name="PERF_PC_VPC_POS_DATA_TRANSACTION"/>
338 <value value="30" name="PERF_PC_3D_DRAWCALLS"/>
339 <value value="31" name="PERF_PC_2D_DRAWCALLS"/>
340 <value value="32" name="PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS"/>
341 <value value="33" name="PERF_TESS_BUSY_CYCLES"/>
342 <value value="34" name="PERF_TESS_WORKING_CYCLES"/>
343 <value value="35" name="PERF_TESS_STALL_CYCLES_PC"/>
344 <value value="36" name="PERF_TESS_STARVE_CYCLES_PC"/>
348 <value value="0" name="PERF_VFD_BUSY_CYCLES"/>
349 <value value="1" name="PERF_VFD_STALL_CYCLES_UCHE"/>
350 <value value="2" name="PERF_VFD_STALL_CYCLES_VPC_ALLOC"/>
351 <value value="3" name="PERF_VFD_STALL_CYCLES_MISS_VB"/>
352 <value value="4" name="PERF_VFD_STALL_CYCLES_MISS_Q"/>
353 <value value="5" name="PERF_VFD_STALL_CYCLES_SP_INFO"/>
354 <value value="6" name="PERF_VFD_STALL_CYCLES_SP_ATTR"/>
355 <value value="7" name="PERF_VFD_STALL_CYCLES_VFDP_VB"/>
356 <value value="8" name="PERF_VFD_STALL_CYCLES_VFDP_Q"/>
357 <value value="9" name="PERF_VFD_DECODER_PACKER_STALL"/>
358 <value value="10" name="PERF_VFD_STARVE_CYCLES_UCHE"/>
359 <value value="11" name="PERF_VFD_RBUFFER_FULL"/>
360 <value value="12" name="PERF_VFD_ATTR_INFO_FIFO_FULL"/>
361 <value value="13" name="PERF_VFD_DECODED_ATTRIBUTE_BYTES"/>
362 <value value="14" name="PERF_VFD_NUM_ATTRIBUTES"/>
363 <value value="15" name="PERF_VFD_INSTRUCTIONS"/>
364 <value value="16" name="PERF_VFD_UPPER_SHADER_FIBERS"/>
365 <value value="17" name="PERF_VFD_LOWER_SHADER_FIBERS"/>
366 <value value="18" name="PERF_VFD_MODE_0_FIBERS"/>
367 <value value="19" name="PERF_VFD_MODE_1_FIBERS"/>
368 <value value="20" name="PERF_VFD_MODE_2_FIBERS"/>
369 <value value="21" name="PERF_VFD_MODE_3_FIBERS"/>
370 <value value="22" name="PERF_VFD_MODE_4_FIBERS"/>
371 <value value="23" name="PERF_VFD_TOTAL_VERTICES"/>
372 <value value="24" name="PERF_VFD_NUM_ATTR_MISS"/>
373 <value value="25" name="PERF_VFD_1_BURST_REQ"/>
374 <value value="26" name="PERF_VFDP_STALL_CYCLES_VFD"/>
375 <value value="27" name="PERF_VFDP_STALL_CYCLES_VFD_INDEX"/>
376 <value value="28" name="PERF_VFDP_STALL_CYCLES_VFD_PROG"/>
377 <value value="29" name="PERF_VFDP_STARVE_CYCLES_PC"/>
378 <value value="30" name="PERF_VFDP_VS_STAGE_32_WAVES"/>
382 <value value="0" name="PERF_HLSQ_BUSY_CYCLES"/>
383 <value value="1" name="PERF_HLSQ_STALL_CYCLES_UCHE"/>
384 <value value="2" name="PERF_HLSQ_STALL_CYCLES_SP_STATE"/>
385 <value value="3" name="PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE"/>
386 <value value="4" name="PERF_HLSQ_UCHE_LATENCY_CYCLES"/>
387 <value value="5" name="PERF_HLSQ_UCHE_LATENCY_COUNT"/>
388 <value value="6" name="PERF_HLSQ_FS_STAGE_32_WAVES"/>
389 <value value="7" name="PERF_HLSQ_FS_STAGE_64_WAVES"/>
390 <value value="8" name="PERF_HLSQ_QUADS"/>
391 <value value="9" name="PERF_HLSQ_SP_STATE_COPY_TRANS_FS_STAGE"/>
392 <value value="10" name="PERF_HLSQ_SP_STATE_COPY_TRANS_VS_STAGE"/>
393 <value value="11" name="PERF_HLSQ_TP_STATE_COPY_TRANS_FS_STAGE"/>
394 <value value="12" name="PERF_HLSQ_TP_STATE_COPY_TRANS_VS_STAGE"/>
395 <value value="13" name="PERF_HLSQ_CS_INVOCATIONS"/>
396 <value value="14" name="PERF_HLSQ_COMPUTE_DRAWCALLS"/>
400 <value value="0" name="PERF_VPC_BUSY_CYCLES"/>
401 <value value="1" name="PERF_VPC_WORKING_CYCLES"/>
402 <value value="2" name="PERF_VPC_STALL_CYCLES_UCHE"/>
403 <value value="3" name="PERF_VPC_STALL_CYCLES_VFD_WACK"/>
404 <value value="4" name="PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC"/>
405 <value value="5" name="PERF_VPC_STALL_CYCLES_PC"/>
406 <value value="6" name="PERF_VPC_STALL_CYCLES_SP_LM"/>
407 <value value="7" name="PERF_VPC_POS_EXPORT_STALL_CYCLES"/>
408 <value value="8" name="PERF_VPC_STARVE_CYCLES_SP"/>
409 <value value="9" name="PERF_VPC_STARVE_CYCLES_LRZ"/>
410 <value value="10" name="PERF_VPC_PC_PRIMITIVES"/>
411 <value value="11" name="PERF_VPC_SP_COMPONENTS"/>
412 <value value="12" name="PERF_VPC_SP_LM_PRIMITIVES"/>
413 <value value="13" name="PERF_VPC_SP_LM_COMPONENTS"/>
414 <value value="14" name="PERF_VPC_SP_LM_DWORDS"/>
415 <value value="15" name="PERF_VPC_STREAMOUT_COMPONENTS"/>
416 <value value="16" name="PERF_VPC_GRANT_PHASES"/>
420 <value value="0" name="PERF_TSE_BUSY_CYCLES"/>
421 <value value="1" name="PERF_TSE_CLIPPING_CYCLES"/>
422 <value value="2" name="PERF_TSE_STALL_CYCLES_RAS"/>
423 <value value="3" name="PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE"/>
424 <value value="4" name="PERF_TSE_STALL_CYCLES_LRZ_ZPLANE"/>
425 <value value="5" name="PERF_TSE_STARVE_CYCLES_PC"/>
426 <value value="6" name="PERF_TSE_INPUT_PRIM"/>
427 <value value="7" name="PERF_TSE_INPUT_NULL_PRIM"/>
428 <value value="8" name="PERF_TSE_TRIVAL_REJ_PRIM"/>
429 <value value="9" name="PERF_TSE_CLIPPED_PRIM"/>
430 <value value="10" name="PERF_TSE_ZERO_AREA_PRIM"/>
431 <value value="11" name="PERF_TSE_FACENESS_CULLED_PRIM"/>
432 <value value="12" name="PERF_TSE_ZERO_PIXEL_PRIM"/>
433 <value value="13" name="PERF_TSE_OUTPUT_NULL_PRIM"/>
434 <value value="14" name="PERF_TSE_OUTPUT_VISIBLE_PRIM"/>
435 <value value="15" name="PERF_TSE_CINVOCATION"/>
436 <value value="16" name="PERF_TSE_CPRIMITIVES"/>
437 <value value="17" name="PERF_TSE_2D_INPUT_PRIM"/>
438 <value value="18" name="PERF_TSE_2D_ALIVE_CLCLES"/>
442 <value value="0" name="PERF_RAS_BUSY_CYCLES"/>
443 <value value="1" name="PERF_RAS_SUPERTILE_ACTIVE_CYCLES"/>
444 <value value="2" name="PERF_RAS_STALL_CYCLES_LRZ"/>
445 <value value="3" name="PERF_RAS_STARVE_CYCLES_TSE"/>
446 <value value="4" name="PERF_RAS_SUPER_TILES"/>
447 <value value="5" name="PERF_RAS_8X4_TILES"/>
448 <value value="6" name="PERF_RAS_MASKGEN_ACTIVE"/>
449 <value value="7" name="PERF_RAS_FULLY_COVERED_SUPER_TILES"/>
450 <value value="8" name="PERF_RAS_FULLY_COVERED_8X4_TILES"/>
451 <value value="9" name="PERF_RAS_PRIM_KILLED_INVISILBE"/>
455 <value value="0" name="PERF_LRZ_BUSY_CYCLES"/>
456 <value value="1" name="PERF_LRZ_STARVE_CYCLES_RAS"/>
457 <value value="2" name="PERF_LRZ_STALL_CYCLES_RB"/>
458 <value value="3" name="PERF_LRZ_STALL_CYCLES_VSC"/>
459 <value value="4" name="PERF_LRZ_STALL_CYCLES_VPC"/>
460 <value value="5" name="PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH"/>
461 <value value="6" name="PERF_LRZ_STALL_CYCLES_UCHE"/>
462 <value value="7" name="PERF_LRZ_LRZ_READ"/>
463 <value value="8" name="PERF_LRZ_LRZ_WRITE"/>
464 <value value="9" name="PERF_LRZ_READ_LATENCY"/>
465 <value value="10" name="PERF_LRZ_MERGE_CACHE_UPDATING"/>
466 <value value="11" name="PERF_LRZ_PRIM_KILLED_BY_MASKGEN"/>
467 <value value="12" name="PERF_LRZ_PRIM_KILLED_BY_LRZ"/>
468 <value value="13" name="PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ"/>
469 <value value="14" name="PERF_LRZ_FULL_8X8_TILES"/>
470 <value value="15" name="PERF_LRZ_PARTIAL_8X8_TILES"/>
471 <value value="16" name="PERF_LRZ_TILE_KILLED"/>
472 <value value="17" name="PERF_LRZ_TOTAL_PIXEL"/>
473 <value value="18" name="PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ"/>
477 <value value="0" name="PERF_UCHE_BUSY_CYCLES"/>
478 <value value="1" name="PERF_UCHE_STALL_CYCLES_VBIF"/>
479 <value value="2" name="PERF_UCHE_VBIF_LATENCY_CYCLES"/>
480 <value value="3" name="PERF_UCHE_VBIF_LATENCY_SAMPLES"/>
481 <value value="4" name="PERF_UCHE_VBIF_READ_BEATS_TP"/>
482 <value value="5" name="PERF_UCHE_VBIF_READ_BEATS_VFD"/>
483 <value value="6" name="PERF_UCHE_VBIF_READ_BEATS_HLSQ"/>
484 <value value="7" name="PERF_UCHE_VBIF_READ_BEATS_LRZ"/>
485 <value value="8" name="PERF_UCHE_VBIF_READ_BEATS_SP"/>
486 <value value="9" name="PERF_UCHE_READ_REQUESTS_TP"/>
487 <value value="10" name="PERF_UCHE_READ_REQUESTS_VFD"/>
488 <value value="11" name="PERF_UCHE_READ_REQUESTS_HLSQ"/>
489 <value value="12" name="PERF_UCHE_READ_REQUESTS_LRZ"/>
490 <value value="13" name="PERF_UCHE_READ_REQUESTS_SP"/>
491 <value value="14" name="PERF_UCHE_WRITE_REQUESTS_LRZ"/>
492 <value value="15" name="PERF_UCHE_WRITE_REQUESTS_SP"/>
493 <value value="16" name="PERF_UCHE_WRITE_REQUESTS_VPC"/>
494 <value value="17" name="PERF_UCHE_WRITE_REQUESTS_VSC"/>
495 <value value="18" name="PERF_UCHE_EVICTS"/>
496 <value value="19" name="PERF_UCHE_BANK_REQ0"/>
497 <value value="20" name="PERF_UCHE_BANK_REQ1"/>
498 <value value="21" name="PERF_UCHE_BANK_REQ2"/>
499 <value value="22" name="PERF_UCHE_BANK_REQ3"/>
500 <value value="23" name="PERF_UCHE_BANK_REQ4"/>
501 <value value="24" name="PERF_UCHE_BANK_REQ5"/>
502 <value value="25" name="PERF_UCHE_BANK_REQ6"/>
503 <value value="26" name="PERF_UCHE_BANK_REQ7"/>
504 <value value="27" name="PERF_UCHE_VBIF_READ_BEATS_CH0"/>
505 <value value="28" name="PERF_UCHE_VBIF_READ_BEATS_CH1"/>
506 <value value="29" name="PERF_UCHE_GMEM_READ_BEATS"/>
507 <value value="30" name="PERF_UCHE_FLAG_COUNT"/>
511 <value value="0" name="PERF_TP_BUSY_CYCLES"/>
512 <value value="1" name="PERF_TP_STALL_CYCLES_UCHE"/>
513 <value value="2" name="PERF_TP_LATENCY_CYCLES"/>
514 <value value="3" name="PERF_TP_LATENCY_TRANS"/>
515 <value value="4" name="PERF_TP_FLAG_CACHE_REQUEST_SAMPLES"/>
516 <value value="5" name="PERF_TP_FLAG_CACHE_REQUEST_LATENCY"/>
517 <value value="6" name="PERF_TP_L1_CACHELINE_REQUESTS"/>
518 <value value="7" name="PERF_TP_L1_CACHELINE_MISSES"/>
519 <value value="8" name="PERF_TP_SP_TP_TRANS"/>
520 <value value="9" name="PERF_TP_TP_SP_TRANS"/>
521 <value value="10" name="PERF_TP_OUTPUT_PIXELS"/>
522 <value value="11" name="PERF_TP_FILTER_WORKLOAD_16BIT"/>
523 <value value="12" name="PERF_TP_FILTER_WORKLOAD_32BIT"/>
524 <value value="13" name="PERF_TP_QUADS_RECEIVED"/>
525 <value value="14" name="PERF_TP_QUADS_OFFSET"/>
526 <value value="15" name="PERF_TP_QUADS_SHADOW"/>
527 <value value="16" name="PERF_TP_QUADS_ARRAY"/>
528 <value value="17" name="PERF_TP_QUADS_GRADIENT"/>
529 <value value="18" name="PERF_TP_QUADS_1D"/>
530 <value value="19" name="PERF_TP_QUADS_2D"/>
531 <value value="20" name="PERF_TP_QUADS_BUFFER"/>
532 <value value="21" name="PERF_TP_QUADS_3D"/>
533 <value value="22" name="PERF_TP_QUADS_CUBE"/>
534 <value value="23" name="PERF_TP_STATE_CACHE_REQUESTS"/>
535 <value value="24" name="PERF_TP_STATE_CACHE_MISSES"/>
536 <value value="25" name="PERF_TP_DIVERGENT_QUADS_RECEIVED"/>
537 <value value="26" name="PERF_TP_BINDLESS_STATE_CACHE_REQUESTS"/>
538 <value value="27" name="PERF_TP_BINDLESS_STATE_CACHE_MISSES"/>
539 <value value="28" name="PERF_TP_PRT_NON_RESIDENT_EVENTS"/>
540 <value value="29" name="PERF_TP_OUTPUT_PIXELS_POINT"/>
541 <value value="30" name="PERF_TP_OUTPUT_PIXELS_BILINEAR"/>
542 <value value="31" name="PERF_TP_OUTPUT_PIXELS_MIP"/>
543 <value value="32" name="PERF_TP_OUTPUT_PIXELS_ANISO"/>
544 <value value="33" name="PERF_TP_OUTPUT_PIXELS_ZERO_LOD"/>
545 <value value="34" name="PERF_TP_FLAG_CACHE_REQUESTS"/>
546 <value value="35" name="PERF_TP_FLAG_CACHE_MISSES"/>
547 <value value="36" name="PERF_TP_L1_5_L2_REQUESTS"/>
548 <value value="37" name="PERF_TP_2D_OUTPUT_PIXELS"/>
549 <value value="38" name="PERF_TP_2D_OUTPUT_PIXELS_POINT"/>
550 <value value="39" name="PERF_TP_2D_OUTPUT_PIXELS_BILINEAR"/>
551 <value value="40" name="PERF_TP_2D_FILTER_WORKLOAD_16BIT"/>
552 <value value="41" name="PERF_TP_2D_FILTER_WORKLOAD_32BIT"/>
556 <value value="0" name="PERF_SP_BUSY_CYCLES"/>
557 <value value="1" name="PERF_SP_ALU_WORKING_CYCLES"/>
558 <value value="2" name="PERF_SP_EFU_WORKING_CYCLES"/>
559 <value value="3" name="PERF_SP_STALL_CYCLES_VPC"/>
560 <value value="4" name="PERF_SP_STALL_CYCLES_TP"/>
561 <value value="5" name="PERF_SP_STALL_CYCLES_UCHE"/>
562 <value value="6" name="PERF_SP_STALL_CYCLES_RB"/>
563 <value value="7" name="PERF_SP_SCHEDULER_NON_WORKING"/>
564 <value value="8" name="PERF_SP_WAVE_CONTEXTS"/>
565 <value value="9" name="PERF_SP_WAVE_CONTEXT_CYCLES"/>
566 <value value="10" name="PERF_SP_FS_STAGE_WAVE_CYCLES"/>
567 <value value="11" name="PERF_SP_FS_STAGE_WAVE_SAMPLES"/>
568 <value value="12" name="PERF_SP_VS_STAGE_WAVE_CYCLES"/>
569 <value value="13" name="PERF_SP_VS_STAGE_WAVE_SAMPLES"/>
570 <value value="14" name="PERF_SP_FS_STAGE_DURATION_CYCLES"/>
571 <value value="15" name="PERF_SP_VS_STAGE_DURATION_CYCLES"/>
572 <value value="16" name="PERF_SP_WAVE_CTRL_CYCLES"/>
573 <value value="17" name="PERF_SP_WAVE_LOAD_CYCLES"/>
574 <value value="18" name="PERF_SP_WAVE_EMIT_CYCLES"/>
575 <value value="19" name="PERF_SP_WAVE_NOP_CYCLES"/>
576 <value value="20" name="PERF_SP_WAVE_WAIT_CYCLES"/>
577 <value value="21" name="PERF_SP_WAVE_FETCH_CYCLES"/>
578 <value value="22" name="PERF_SP_WAVE_IDLE_CYCLES"/>
579 <value value="23" name="PERF_SP_WAVE_END_CYCLES"/>
580 <value value="24" name="PERF_SP_WAVE_LONG_SYNC_CYCLES"/>
581 <value value="25" name="PERF_SP_WAVE_SHORT_SYNC_CYCLES"/>
582 <value value="26" name="PERF_SP_WAVE_JOIN_CYCLES"/>
583 <value value="27" name="PERF_SP_LM_LOAD_INSTRUCTIONS"/>
584 <value value="28" name="PERF_SP_LM_STORE_INSTRUCTIONS"/>
585 <value value="29" name="PERF_SP_LM_ATOMICS"/>
586 <value value="30" name="PERF_SP_GM_LOAD_INSTRUCTIONS"/>
587 <value value="31" name="PERF_SP_GM_STORE_INSTRUCTIONS"/>
588 <value value="32" name="PERF_SP_GM_ATOMICS"/>
589 <value value="33" name="PERF_SP_VS_STAGE_TEX_INSTRUCTIONS"/>
590 <value value="34" name="PERF_SP_VS_STAGE_CFLOW_INSTRUCTIONS"/>
591 <value value="35" name="PERF_SP_VS_STAGE_EFU_INSTRUCTIONS"/>
592 <value value="36" name="PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS"/>
593 <value value="37" name="PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS"/>
594 <value value="38" name="PERF_SP_FS_STAGE_TEX_INSTRUCTIONS"/>
595 <value value="39" name="PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS"/>
596 <value value="40" name="PERF_SP_FS_STAGE_EFU_INSTRUCTIONS"/>
597 <value value="41" name="PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS"/>
598 <value value="42" name="PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS"/>
599 <value value="43" name="PERF_SP_FS_STAGE_BARY_INSTRUCTIONS"/>
600 <value value="44" name="PERF_SP_VS_INSTRUCTIONS"/>
601 <value value="45" name="PERF_SP_FS_INSTRUCTIONS"/>
602 <value value="46" name="PERF_SP_ADDR_LOCK_COUNT"/>
603 <value value="47" name="PERF_SP_UCHE_READ_TRANS"/>
604 <value value="48" name="PERF_SP_UCHE_WRITE_TRANS"/>
605 <value value="49" name="PERF_SP_EXPORT_VPC_TRANS"/>
606 <value value="50" name="PERF_SP_EXPORT_RB_TRANS"/>
607 <value value="51" name="PERF_SP_PIXELS_KILLED"/>
608 <value value="52" name="PERF_SP_ICL1_REQUESTS"/>
609 <value value="53" name="PERF_SP_ICL1_MISSES"/>
610 <value value="54" name="PERF_SP_ICL0_REQUESTS"/>
611 <value value="55" name="PERF_SP_ICL0_MISSES"/>
612 <value value="56" name="PERF_SP_HS_INSTRUCTIONS"/>
613 <value value="57" name="PERF_SP_DS_INSTRUCTIONS"/>
614 <value value="58" name="PERF_SP_GS_INSTRUCTIONS"/>
615 <value value="59" name="PERF_SP_CS_INSTRUCTIONS"/>
616 <value value="60" name="PERF_SP_GPR_READ"/>
617 <value value="61" name="PERF_SP_GPR_WRITE"/>
618 <value value="62" name="PERF_SP_LM_CH0_REQUESTS"/>
619 <value value="63" name="PERF_SP_LM_CH1_REQUESTS"/>
620 <value value="64" name="PERF_SP_LM_BANK_CONFLICTS"/>
624 <value value="0" name="PERF_RB_BUSY_CYCLES"/>
625 <value value="1" name="PERF_RB_STALL_CYCLES_CCU"/>
626 <value value="2" name="PERF_RB_STALL_CYCLES_HLSQ"/>
627 <value value="3" name="PERF_RB_STALL_CYCLES_FIFO0_FULL"/>
628 <value value="4" name="PERF_RB_STALL_CYCLES_FIFO1_FULL"/>
629 <value value="5" name="PERF_RB_STALL_CYCLES_FIFO2_FULL"/>
630 <value value="6" name="PERF_RB_STARVE_CYCLES_SP"/>
631 <value value="7" name="PERF_RB_STARVE_CYCLES_LRZ_TILE"/>
632 <value value="8" name="PERF_RB_STARVE_CYCLES_CCU"/>
633 <value value="9" name="PERF_RB_STARVE_CYCLES_Z_PLANE"/>
634 <value value="10" name="PERF_RB_STARVE_CYCLES_BARY_PLANE"/>
635 <value value="11" name="PERF_RB_Z_WORKLOAD"/>
636 <value value="12" name="PERF_RB_HLSQ_ACTIVE"/>
637 <value value="13" name="PERF_RB_Z_READ"/>
638 <value value="14" name="PERF_RB_Z_WRITE"/>
639 <value value="15" name="PERF_RB_C_READ"/>
640 <value value="16" name="PERF_RB_C_WRITE"/>
641 <value value="17" name="PERF_RB_TOTAL_PASS"/>
642 <value value="18" name="PERF_RB_Z_PASS"/>
643 <value value="19" name="PERF_RB_Z_FAIL"/>
644 <value value="20" name="PERF_RB_S_FAIL"/>
645 <value value="21" name="PERF_RB_BLENDED_FXP_COMPONENTS"/>
646 <value value="22" name="PERF_RB_BLENDED_FP16_COMPONENTS"/>
647 <value value="23" name="RB_RESERVED"/>
648 <value value="24" name="PERF_RB_2D_ALIVE_CYCLES"/>
649 <value value="25" name="PERF_RB_2D_STALL_CYCLES_A2D"/>
650 <value value="26" name="PERF_RB_2D_STARVE_CYCLES_SRC"/>
651 <value value="27" name="PERF_RB_2D_STARVE_CYCLES_SP"/>
652 <value value="28" name="PERF_RB_2D_STARVE_CYCLES_DST"/>
653 <value value="29" name="PERF_RB_2D_VALID_PIXELS"/>
657 <value value="0" name="TOTAL_SAMPLES"/>
658 <value value="1" name="ZPASS_SAMPLES"/>
659 <value value="2" name="ZFAIL_SAMPLES"/>
660 <value value="3" name="SFAIL_SAMPLES"/>
664 <value value="0" name="PERF_VSC_BUSY_CYCLES"/>
665 <value value="1" name="PERF_VSC_WORKING_CYCLES"/>
666 <value value="2" name="PERF_VSC_STALL_CYCLES_UCHE"/>
667 <value value="3" name="PERF_VSC_EOT_NUM"/>
671 <value value="0" name="PERF_CCU_BUSY_CYCLES"/>
672 <value value="1" name="PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN"/>
673 <value value="2" name="PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN"/>
674 <value value="3" name="PERF_CCU_STARVE_CYCLES_FLAG_RETURN"/>
675 <value value="4" name="PERF_CCU_DEPTH_BLOCKS"/>
676 <value value="5" name="PERF_CCU_COLOR_BLOCKS"/>
677 <value value="6" name="PERF_CCU_DEPTH_BLOCK_HIT"/>
678 <value value="7" name="PERF_CCU_COLOR_BLOCK_HIT"/>
679 <value value="8" name="PERF_CCU_PARTIAL_BLOCK_READ"/>
680 <value value="9" name="PERF_CCU_GMEM_READ"/>
681 <value value="10" name="PERF_CCU_GMEM_WRITE"/>
682 <value value="11" name="PERF_CCU_DEPTH_READ_FLAG0_COUNT"/>
683 <value value="12" name="PERF_CCU_DEPTH_READ_FLAG1_COUNT"/>
684 <value value="13" name="PERF_CCU_DEPTH_READ_FLAG2_COUNT"/>
685 <value value="14" name="PERF_CCU_DEPTH_READ_FLAG3_COUNT"/>
686 <value value="15" name="PERF_CCU_DEPTH_READ_FLAG4_COUNT"/>
687 <value value="16" name="PERF_CCU_COLOR_READ_FLAG0_COUNT"/>
688 <value value="17" name="PERF_CCU_COLOR_READ_FLAG1_COUNT"/>
689 <value value="18" name="PERF_CCU_COLOR_READ_FLAG2_COUNT"/>
690 <value value="19" name="PERF_CCU_COLOR_READ_FLAG3_COUNT"/>
691 <value value="20" name="PERF_CCU_COLOR_READ_FLAG4_COUNT"/>
692 <value value="21" name="PERF_CCU_2D_BUSY_CYCLES"/>
693 <value value="22" name="PERF_CCU_2D_RD_REQ"/>
694 <value value="23" name="PERF_CCU_2D_WR_REQ"/>
695 <value value="24" name="PERF_CCU_2D_REORDER_STARVE_CYCLES"/>
696 <value value="25" name="PERF_CCU_2D_PIXELS"/>
700 <value value="0" name="PERF_CMPDECMP_STALL_CYCLES_VBIF"/>
701 <value value="1" name="PERF_CMPDECMP_VBIF_LATENCY_CYCLES"/>
702 <value value="2" name="PERF_CMPDECMP_VBIF_LATENCY_SAMPLES"/>
703 <value value="3" name="PERF_CMPDECMP_VBIF_READ_DATA_CCU"/>
704 <value value="4" name="PERF_CMPDECMP_VBIF_WRITE_DATA_CCU"/>
705 <value value="5" name="PERF_CMPDECMP_VBIF_READ_REQUEST"/>
706 <value value="6" name="PERF_CMPDECMP_VBIF_WRITE_REQUEST"/>
707 <value value="7" name="PERF_CMPDECMP_VBIF_READ_DATA"/>
708 <value value="8" name="PERF_CMPDECMP_VBIF_WRITE_DATA"/>
709 <value value="9" name="PERF_CMPDECMP_FLAG_FETCH_CYCLES"/>
710 <value value="10" name="PERF_CMPDECMP_FLAG_FETCH_SAMPLES"/>
711 <value value="11" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT"/>
712 <value value="12" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT"/>
713 <value value="13" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT"/>
714 <value value="14" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT"/>
715 <value value="15" name="PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT"/>
716 <value value="16" name="PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT"/>
717 <value value="17" name="PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT"/>
718 <value value="18" name="PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT"/>
719 <value value="19" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ"/>
720 <value value="20" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR"/>
721 <value value="21" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN"/>
722 <value value="22" name="PERF_CMPDECMP_2D_RD_DATA"/>
723 <value value="23" name="PERF_CMPDECMP_2D_WR_DATA"/>
727 <value value="0" name="AXI_READ_REQUESTS_ID_0"/>
728 <value value="1" name="AXI_READ_REQUESTS_ID_1"/>
729 <value value="2" name="AXI_READ_REQUESTS_ID_2"/>
730 <value value="3" name="AXI_READ_REQUESTS_ID_3"/>
731 <value value="4" name="AXI_READ_REQUESTS_ID_4"/>
732 <value value="5" name="AXI_READ_REQUESTS_ID_5"/>
733 <value value="6" name="AXI_READ_REQUESTS_ID_6"/>
734 <value value="7" name="AXI_READ_REQUESTS_ID_7"/>
735 <value value="8" name="AXI_READ_REQUESTS_ID_8"/>
736 <value value="9" name="AXI_READ_REQUESTS_ID_9"/>
737 <value value="10" name="AXI_READ_REQUESTS_ID_10"/>
738 <value value="11" name="AXI_READ_REQUESTS_ID_11"/>
739 <value value="12" name="AXI_READ_REQUESTS_ID_12"/>
740 <value value="13" name="AXI_READ_REQUESTS_ID_13"/>
741 <value value="14" name="AXI_READ_REQUESTS_ID_14"/>
742 <value value="15" name="AXI_READ_REQUESTS_ID_15"/>
743 <value value="16" name="AXI0_READ_REQUESTS_TOTAL"/>
744 <value value="17" name="AXI1_READ_REQUESTS_TOTAL"/>
745 <value value="18" name="AXI2_READ_REQUESTS_TOTAL"/>
746 <value value="19" name="AXI3_READ_REQUESTS_TOTAL"/>
747 <value value="20" name="AXI_READ_REQUESTS_TOTAL"/>
748 <value value="21" name="AXI_WRITE_REQUESTS_ID_0"/>
749 <value value="22" name="AXI_WRITE_REQUESTS_ID_1"/>
750 <value value="23" name="AXI_WRITE_REQUESTS_ID_2"/>
751 <value value="24" name="AXI_WRITE_REQUESTS_ID_3"/>
752 <value value="25" name="AXI_WRITE_REQUESTS_ID_4"/>
753 <value value="26" name="AXI_WRITE_REQUESTS_ID_5"/>
754 <value value="27" name="AXI_WRITE_REQUESTS_ID_6"/>
755 <value value="28" name="AXI_WRITE_REQUESTS_ID_7"/>
756 <value value="29" name="AXI_WRITE_REQUESTS_ID_8"/>
757 <value value="30" name="AXI_WRITE_REQUESTS_ID_9"/>
758 <value value="31" name="AXI_WRITE_REQUESTS_ID_10"/>
759 <value value="32" name="AXI_WRITE_REQUESTS_ID_11"/>
760 <value value="33" name="AXI_WRITE_REQUESTS_ID_12"/>
761 <value value="34" name="AXI_WRITE_REQUESTS_ID_13"/>
762 <value value="35" name="AXI_WRITE_REQUESTS_ID_14"/>
763 <value value="36" name="AXI_WRITE_REQUESTS_ID_15"/>
764 <value value="37" name="AXI0_WRITE_REQUESTS_TOTAL"/>
765 <value value="38" name="AXI1_WRITE_REQUESTS_TOTAL"/>
766 <value value="39" name="AXI2_WRITE_REQUESTS_TOTAL"/>
767 <value value="40" name="AXI3_WRITE_REQUESTS_TOTAL"/>
768 <value value="41" name="AXI_WRITE_REQUESTS_TOTAL"/>
769 <value value="42" name="AXI_TOTAL_REQUESTS"/>
770 <value value="43" name="AXI_READ_DATA_BEATS_ID_0"/>
771 <value value="44" name="AXI_READ_DATA_BEATS_ID_1"/>
772 <value value="45" name="AXI_READ_DATA_BEATS_ID_2"/>
773 <value value="46" name="AXI_READ_DATA_BEATS_ID_3"/>
774 <value value="47" name="AXI_READ_DATA_BEATS_ID_4"/>
775 <value value="48" name="AXI_READ_DATA_BEATS_ID_5"/>
776 <value value="49" name="AXI_READ_DATA_BEATS_ID_6"/>
777 <value value="50" name="AXI_READ_DATA_BEATS_ID_7"/>
778 <value value="51" name="AXI_READ_DATA_BEATS_ID_8"/>
779 <value value="52" name="AXI_READ_DATA_BEATS_ID_9"/>
780 <value value="53" name="AXI_READ_DATA_BEATS_ID_10"/>
781 <value value="54" name="AXI_READ_DATA_BEATS_ID_11"/>
782 <value value="55" name="AXI_READ_DATA_BEATS_ID_12"/>
783 <value value="56" name="AXI_READ_DATA_BEATS_ID_13"/>
784 <value value="57" name="AXI_READ_DATA_BEATS_ID_14"/>
785 <value value="58" name="AXI_READ_DATA_BEATS_ID_15"/>
786 <value value="59" name="AXI0_READ_DATA_BEATS_TOTAL"/>
787 <value value="60" name="AXI1_READ_DATA_BEATS_TOTAL"/>
788 <value value="61" name="AXI2_READ_DATA_BEATS_TOTAL"/>
789 <value value="62" name="AXI3_READ_DATA_BEATS_TOTAL"/>
790 <value value="63" name="AXI_READ_DATA_BEATS_TOTAL"/>
791 <value value="64" name="AXI_WRITE_DATA_BEATS_ID_0"/>
792 <value value="65" name="AXI_WRITE_DATA_BEATS_ID_1"/>
793 <value value="66" name="AXI_WRITE_DATA_BEATS_ID_2"/>
794 <value value="67" name="AXI_WRITE_DATA_BEATS_ID_3"/>
795 <value value="68" name="AXI_WRITE_DATA_BEATS_ID_4"/>
796 <value value="69" name="AXI_WRITE_DATA_BEATS_ID_5"/>
797 <value value="70" name="AXI_WRITE_DATA_BEATS_ID_6"/>
798 <value value="71" name="AXI_WRITE_DATA_BEATS_ID_7"/>
799 <value value="72" name="AXI_WRITE_DATA_BEATS_ID_8"/>
800 <value value="73" name="AXI_WRITE_DATA_BEATS_ID_9"/>
801 <value value="74" name="AXI_WRITE_DATA_BEATS_ID_10"/>
802 <value value="75" name="AXI_WRITE_DATA_BEATS_ID_11"/>
803 <value value="76" name="AXI_WRITE_DATA_BEATS_ID_12"/>
804 <value value="77" name="AXI_WRITE_DATA_BEATS_ID_13"/>
805 <value value="78" name="AXI_WRITE_DATA_BEATS_ID_14"/>
806 <value value="79" name="AXI_WRITE_DATA_BEATS_ID_15"/>
807 <value value="80" name="AXI0_WRITE_DATA_BEATS_TOTAL"/>
808 <value value="81" name="AXI1_WRITE_DATA_BEATS_TOTAL"/>
809 <value value="82" name="AXI2_WRITE_DATA_BEATS_TOTAL"/>
810 <value value="83" name="AXI3_WRITE_DATA_BEATS_TOTAL"/>
811 <value value="84" name="AXI_WRITE_DATA_BEATS_TOTAL"/>
812 <value value="85" name="AXI_DATA_BEATS_TOTAL"/>
1910 since the occluded primitive can still contribute to final color value
1919 <doc>update MAX instead of MIN value, ie. GL_GREATER/GL_GEQUAL</doc>
2574 texture using varying value directly before shader thread starts? I
2715 <!-- localsize is value minus one: -->
2849 <value name="A5XX_TEX_NEAREST" value="0"/>
2850 <value name="A5XX_TEX_LINEAR" value="1"/>
2851 <value name="A5XX_TEX_ANISO" value="2"/>
2854 <value name="A5XX_TEX_REPEAT" value="0"/>
2855 <value name="A5XX_TEX_CLAMP_TO_EDGE" value="1"/>
2856 <value name="A5XX_TEX_MIRROR_REPEAT" value="2"/>
2857 <value name="A5XX_TEX_CLAMP_TO_BORDER" value="3"/>
2858 <value name="A5XX_TEX_MIRROR_CLAMP" value="4"/>
2861 <value name="A5XX_TEX_ANISO_1" value="0"/>
2862 <value name="A5XX_TEX_ANISO_2" value="1"/>
2863 <value name="A5XX_TEX_ANISO_4" value="2"/>
2864 <value name="A5XX_TEX_ANISO_8" value="3"/>
2865 <value name="A5XX_TEX_ANISO_16" value="4"/>
2909 <value name="A5XX_TEX_X" value="0"/>
2910 <value name="A5XX_TEX_Y" value="1"/>
2911 <value name="A5XX_TEX_Z" value="2"/>
2912 <value name="A5XX_TEX_W" value="3"/>
2913 <value name="A5XX_TEX_ZERO" value="4"/>
2914 <value name="A5XX_TEX_ONE" value="5"/>
2917 <value name="A5XX_TEX_1D" value="0"/>
2918 <value name="A5XX_TEX_2D" value="1"/>
2919 <value name="A5XX_TEX_CUBE" value="2"/>
2920 <value name="A5XX_TEX_3D" value="3"/>
2921 <value name="A5XX_TEX_BUFFER" value="4"/>