/linux/drivers/net/phy/ |
H A D | linkmode.c | 1 // SPDX-License-Identifier: GPL-2.0+ 5 * linkmode_resolve_pause - resolve the allowable pause modes 19 * 0 1 1 1 TX 21 * 1 X 1 X TX+RX 47 * linkmode_set_pause - set the pause mode advertisement 49 * @tx: boolean from ethtool struct ethtool_pauseparam tx_pause member 53 * capabilities of provided in @tx and @rx. 56 * tx rx Pause AsymDir 62 * Note: this translation from ethtool tx/rx notation to the advertisement 65 * For tx=0 rx=1, meaning transmit is unsupported, receive is supported: [all …]
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/linux/Documentation/devicetree/bindings/sound/ |
H A D | rockchip,i2s-tdm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/sound/rockchip,i2s-tdm.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 15 - Nicolas Frattaroli <frattaroli.nicolas@gmail.com> 18 - $ref: dai-common.yaml# 23 - rockchip,px30-i2s-tdm 24 - rockchip,rk1808-i2s-tdm 25 - rockchip,rk3308-i2s-tdm 26 - rockchip,rk3568-i2s-tdm [all …]
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/linux/drivers/firmware/tegra/ |
H A D | ivc.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. 47 * This structure is divided into two-cache aligned parts, the first is only 48 * written through the tx.channel pointer, while the second is only written 50 * lines, which is critical to performance and necessary in non-cache coherent 62 } tx; member 79 if (!ivc->peer) in tegra_ivc_invalidate() 82 dma_sync_single_for_cpu(ivc->peer, phys, TEGRA_IVC_ALIGN, in tegra_ivc_invalidate() 88 if (!ivc->peer) in tegra_ivc_flush() 91 dma_sync_single_for_device(ivc->peer, phys, TEGRA_IVC_ALIGN, in tegra_ivc_flush() [all …]
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/linux/Documentation/userspace-api/media/cec/ |
H A D | cec-pin-error-inj.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later 8 The CEC Pin Framework is a core CEC framework for CEC hardware that only 9 has low-level support for the CEC bus. Most hardware today will have 10 high-level CEC support where the hardware deals with driving the CEC bus, 19 Currently only the cec-gpio driver (when the CEC line is directly 20 connected to a pull-up GPIO line) and the AllWinner A10/A20 drm driver 25 now an ``error-inj`` file. 32 With ``cat error-inj`` you can see both the possible commands and the current 35 $ cat /sys/kernel/debug/cec/cec0/error-inj 37 # clear clear all rx and tx error injections [all …]
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/linux/drivers/spi/ |
H A D | spi-loopback-test.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 3 * linux/drivers/spi/spi-loopback-test.c 23 #include "spi-test.h" 25 /* flag to only simulate transfers */ 37 /* the device is jumpered for loopback - enabling some rx_buf tests */ 56 /* run tests only for a specific length */ 57 static int run_only_iter_len = -1; 60 "only run tests for a length of this number in iterate_len list"); 62 /* run only a specific test */ 63 static int run_only_test = -1; [all …]
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H A D | spi-bcm2835.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 10 * spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org> 11 * spi-atmel.c, Copyright (C) 2006 Atmel Corporation 19 #include <linux/dma-mapping.h> 76 #define DRV_NAME "spi-bcm2835" 85 * struct bcm2835_spi - BCM2835 SPI controller 88 * @cs_gpio: chip-select GPIO descriptor 90 * @irq: interrupt, signals TX FIFO empty or RX FIFO ¾ full 97 * @tx_prologue: bytes transmitted without DMA if first TX sglist entry's 101 * @tx_spillover: whether @tx_prologue spills over to second TX sglist entry [all …]
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/linux/drivers/net/wan/ |
H A D | hd64572.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 3 * hd64572.h Description of the Hitachi HD64572 (SCA-II), valid for 8 * Copyright: (c) 2000-2001 Cyclades Corp. 15 * PC300 initial CVS version (3.4.0-pre1) 48 #define DTX_REG(reg, chan) (reg + 0x20*(2*chan + 1)) /* DMA Tx */ 50 #define TTX_REG(reg, chan) (reg + 0x10*(2*chan + 1)) /* Timer Tx */ 53 #define IR0_DTX(val, chan) ((val)<<(4*(2*chan + 1))) /* Int DMA Tx */ 66 #define TXS 0x13d /* TX clock source */ 68 #define TMCT 0x144 /* Time constant (Tx) */ 85 #define TRBL 0x100 /* TX/RX buffer reg L */ [all …]
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/linux/drivers/media/i2c/adv748x/ |
H A D | adv748x-csi2.c | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Driver for Analog Devices ADV748X CSI-2 Transmitter 10 #include <media/v4l2-ctrls.h> 11 #include <media/v4l2-device.h> 12 #include <media/v4l2-ioctl.h> 25 int adv748x_csi2_set_virtual_channel(struct adv748x_csi2 *tx, unsigned int vc) in adv748x_csi2_set_virtual_channel() argument 27 return tx_write(tx, ADV748X_CSI_VC_REF, vc << ADV748X_CSI_VC_REF_SHIFT); in adv748x_csi2_set_virtual_channel() 33 * @tx: CSI2 private entity 36 * @src_pad: Pad number of source to link to this @tx 42 static int adv748x_csi2_register_link(struct adv748x_csi2 *tx, in adv748x_csi2_register_link() argument [all …]
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/linux/Documentation/networking/device_drivers/ethernet/mellanox/mlx5/ |
H A D | counters.rst | 1 .. SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 13 - `Overview`_ 14 - `Groups`_ 15 - `Types`_ 16 - `Descriptions`_ 27 ---------------------------------------- 29 ---------------------------------------- ---------------------------------------- | 32 | ------------------- --------------- | | ------------------- --------------- | | 34 | ------------------- --------------- | | ------------------- --------------- | | 36 | ------------------- | | ------------------- | | [all …]
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/linux/drivers/net/ethernet/marvell/ |
H A D | skge.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 133 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */ 134 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */ 135 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */ 136 CS_VAUX_AVAIL = 1<<10,/* VAUX available (YUKON only) */ 153 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */ 173 IS_I2C_READY = 1<<25, /* IRQ on end of I2C Tx */ 175 IS_EXT_REG = 1<<23, /* IRQ from LM80 or PHY (GENESIS only) */ 176 /* IRQ from PHY (YUKON only) */ 217 IS_IRQ_TIST_OV = 1<<13, /* Time Stamp Timer Overflow (YUKON only) */ [all …]
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H A D | sky2.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 30 /* Yukon-2 */ 32 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */ 33 PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */ 34 PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */ 35 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */ 36 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */ 37 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */ 38 PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */ 60 /* PCI_OUR_REG_3 32 bit Our Register 3 (Yukon-ECU only) */ [all …]
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/linux/Documentation/networking/devlink/ |
H A D | mlx5.rst | 1 .. SPDX-License-Identifier: GPL-2.0 13 .. list-table:: Generic parameters implemented 15 * - Name 16 - Mode 17 - Validation 18 * - ``enable_roce`` 19 - driverinit 20 - Type: Boolean 24 driver stack. When RoCE is disabled at the driver level, only raw 26 * - ``io_eq_size`` [all …]
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/linux/drivers/net/wireless/ralink/rt2x00/ |
H A D | rt2x00queue.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 3 Copyright (C) 2004 - 2010 Ivo van Doorn <IvDoorn@gmail.com> 42 * @QID_OTHER: None of the above (don't use, only present for completeness) 63 * @SKBDESC_DMA_MAPPED_TX: &skb_dma field has been mapped for TX 87 * @tx_rate_idx: the index of the TX rate, used for TX status reporting 88 * @tx_rate_flags: the TX rate flags, used for TX status reporting 91 * of the scope of the skb->data pointer. 93 * @skb_dma: (PCI-only) the DMA address associated with the sk buffer. 112 * get_skb_frame_desc - Obtain the rt2x00 frame descriptor from a sk_buff. 119 return (struct skb_frame_desc *)&IEEE80211_SKB_CB(skb)->driver_data; in get_skb_frame_desc() [all …]
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/linux/drivers/net/wireless/intel/iwlwifi/fw/api/ |
H A D | power.h | 1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 3 * Copyright (C) 2012-2014, 2018-2024 Intel Corporation 4 * Copyright (C) 2013-2014 Intel Mobile Communications GmbH 5 * Copyright (C) 2015-2017 Intel Deutschland GmbH 13 * enum iwl_ltr_config_flags - masks for LTR config command flags 39 * struct iwl_ltr_config_cmd_v1 - configures the LTR 53 * struct iwl_ltr_config_cmd - configures the LTR 58 * TX, RX, Short Idle, Long Idle. Used only if %LTR_CFG_FLAG_UPDATE_VALUES 60 * @ltr_short_idle_timeout: LTR Short Idle timeout (in usec). Used only if 77 * enum iwl_power_flags - masks for power table command flags [all …]
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H A D | tx.h | 1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 3 * Copyright (C) 2012-2014, 2018-2024 Intel Corporation 4 * Copyright (C) 2016-2017 Intel Deutschland GmbH 11 * enum iwl_tx_flags - bitmasks for tx_flags in TX command 12 * @TX_CMD_FLG_PROT_REQUIRE: use RTS or CTS-to-self to protect the frame 13 * @TX_CMD_FLG_WRITE_TX_POWER: update current tx power value in the mgmt frame 15 * @TX_CMD_FLG_STA_RATE: use RS table with initial index from the TX command. 16 * Otherwise, use rate_n_flags from the TX command 22 * @TX_CMD_FLG_CSI_FDBK2HOST: mark to send feedback to host (only if good CRC) 28 * Should be set for mgmt, non-QOS data, mcast, bcast and in scan command [all …]
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/linux/drivers/net/ethernet/broadcom/ |
H A D | b44.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 9 #define DEVCTRL_MPM 0x00000040 /* Magic Packet PME Enable (B0 only) */ 17 #define B44_BIST_STAT 0x000CUL /* Built-In Self-Test Status */ 34 #define ISTAT_LS 0x00000020 /* Link Change (B0 only) */ 44 #define ISTAT_TX 0x01000000 /* TX Interrupt */ 52 #define B44_ADDR_LO 0x0088UL /* ENET Address Lo (B0 only) */ 53 #define B44_ADDR_HI 0x008CUL /* ENET Address Hi (B0 only) */ 56 #define B44_TXBURST 0x00A0UL /* TX Max Burst Length */ 71 #define B44_DMATX_CTRL 0x0200UL /* DMA TX Control */ 77 #define B44_DMATX_ADDR 0x0204UL /* DMA TX Descriptor Ring Address */ [all …]
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/linux/Documentation/devicetree/bindings/serial/ |
H A D | mvebu-uart.txt | 2 e.g., Armada-3700. 5 - compatible: 6 - "marvell,armada-3700-uart" for the standard variant of the UART 7 (32 bytes FIFO, no DMA, level interrupts, 8-bit access to the 9 - "marvell,armada-3700-uart-ext" for the extended variant of the 10 UART (128 bytes FIFO, DMA, front interrupts, 8-bit or 32-bit 12 - reg: offset and length of the register set for the device. 13 - clocks: UART reference clock used to derive the baudrate. If no clock 14 is provided (possible only with the "marvell,armada-3700-uart" 15 compatible string for backward compatibility), it will only work [all …]
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/linux/drivers/dma/ |
H A D | virt-dma.c | 1 // SPDX-License-Identifier: GPL-2.0-only 12 #include "virt-dma.h" 14 static struct virt_dma_desc *to_virt_desc(struct dma_async_tx_descriptor *tx) in to_virt_desc() argument 16 return container_of(tx, struct virt_dma_desc, tx); in to_virt_desc() 19 dma_cookie_t vchan_tx_submit(struct dma_async_tx_descriptor *tx) in vchan_tx_submit() argument 21 struct virt_dma_chan *vc = to_virt_chan(tx->chan); in vchan_tx_submit() 22 struct virt_dma_desc *vd = to_virt_desc(tx); in vchan_tx_submit() 26 spin_lock_irqsave(&vc->lock, flags); in vchan_tx_submit() 27 cookie = dma_cookie_assign(tx); in vchan_tx_submit() 29 list_move_tail(&vd->node, &vc->desc_submitted); in vchan_tx_submit() [all …]
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/linux/drivers/net/wireless/intel/iwlegacy/ |
H A D | commands.h | 8 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved. 29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 33 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved. 77 /* Tx rates */ 92 /* Multi-Station support */ 99 /* RX, TX, LEDs */ 100 N_3945_RX = 0x1b, /* 3945 only */ 102 C_RATE_SCALE = 0x47, /* 3945 only */ 138 /* RF-KILL commands and notifications */ 184 * when sending the response to each driver-originated command, so [all …]
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H A D | prph.h | 8 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved. 29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 33 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved. 94 #define APMG_PS_CTRL_VAL_PWR_SRC_MAX (0x01000000) /* 3945 only */ 106 * processor is sleeping (e.g. for periodic power-saving shutdowns of radio). 119 * The uCode used for open-source drivers includes two programs: 121 * 1) Initialization -- performs hardware calibration and sets up some 128 * 2) Runtime/Protocol -- performs all normal runtime operations. This 134 * 1) Load bootstrap program (instructions only, no data image for bootstrap) 170 * Data caching during power-downs: [all …]
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/linux/include/linux/mfd/ |
H A D | ipaq-micro.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 31 #define MSG_BACKLIGHT 0xd /* H3600 only */ 32 #define MSG_CODEC_CTRL 0xe /* H3100 only */ 33 #define MSG_DISPLAY_CTRL 0xf /* H3100 only */ 44 * struct ipaq_micro_txdev - TX state 45 * @len: length of message in TX buffer 46 * @index: current index into TX buffer 47 * @buf: TX buffer 56 * struct ipaq_micro_rxdev - RX state 74 * struct ipaq_micro_msg - message to the iPAQ microcontroller [all …]
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/linux/drivers/net/can/spi/mcp251xfd/ |
H A D | mcp251xfd-ram.c | 1 // SPDX-License-Identifier: GPL-2.0 3 // mcp251xfd - Microchip MCP251xFD Family CAN controller driver 6 // Marc Kleine-Budde <kernel@pengutronix.de> 9 #include "mcp251xfd-ram.h" 17 max = min_t(u8, obj->max, obj->fifo_num * config->fifo_depth); in can_ram_clamp() 18 return clamp(val, obj->min, max); in can_ram_clamp() 26 u8 fifo_num = obj->fifo_num; in can_ram_rounddown_pow_of_two() 35 * coalescing or only half of FIFO (FIFO Half Full in can_ram_rounddown_pow_of_two() 38 ret = min_t(u8, coalesce * 2, config->fifo_depth); in can_ram_rounddown_pow_of_two() 39 val -= ret; in can_ram_rounddown_pow_of_two() [all …]
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/linux/drivers/infiniband/hw/hfi1/ |
H A D | user_sdma.c | 1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 3 * Copyright(c) 2020 - 2023 Cornelis Networks, Inc. 4 * Copyright(c) 2015 - 2018 Intel Corporation. 46 struct user_sdma_txreq *tx, u32 datalen); 48 struct user_sdma_txreq *tx, u32 len); 72 container_of(wait->iow, struct hfi1_user_sdma_pkt_q, busy); in defer_packet_queue() 74 write_seqlock(&sde->waitlock); in defer_packet_queue() 75 trace_hfi1_usdma_defer(pq, sde, &pq->busy); in defer_packet_queue() 80 * is to the dmawait list since that is the only place where in defer_packet_queue() 83 xchg(&pq->state, SDMA_PKT_Q_DEFERRED); in defer_packet_queue() [all …]
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/linux/drivers/net/can/peak_canfd/ |
H A D | peak_pciefd_main.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (C) 2012 Stephane Grosjean <s.grosjean@peak-system.com> 7 * Copyright (C) 2001-2006 PEAK System-Technik GmbH 22 MODULE_AUTHOR("Stephane Grosjean <s.grosjean@peak-system.com>"); 23 MODULE_DESCRIPTION("Socket-CAN driver for PEAK PCAN PCIe/M.2 FD family cards"); 30 #define PCAN_CPCIEFD_ID 0x0014 /* for Compact-PCI Serial slot cards */ 31 #define PCAN_PCIE104FD_ID 0x0017 /* for PCIe-104 Express slot cards */ 32 #define PCAN_MINIPCIEFD_ID 0x0018 /* for mini-PCIe slot cards */ 59 /* CAN-FD channel addresses */ 64 /* CAN-FD channel registers */ [all …]
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/linux/Documentation/devicetree/bindings/net/ |
H A D | motorcomm,yt8xxx.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Frank Sae <frank.sae@motor-comm.com> 13 - $ref: ethernet-phy.yaml# 18 - ethernet-phy-id4f51.e91a 19 - ethernet-phy-id4f51.e91b 21 rx-internal-delay-ps: 23 RGMII RX Clock Delay used only when PHY operates in RGMII mode with 24 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds. [all …]
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