Lines Matching +full:tx +full:- +full:only
1 /* SPDX-License-Identifier: GPL-2.0 */
30 /* Yukon-2 */
32 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
33 PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */
34 PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */
35 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
36 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
37 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
38 PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
60 /* PCI_OUR_REG_3 32 bit Our Register 3 (Yukon-ECU only) */
62 P_CLK_ASF_REGS_DIS = 1<<18,/* Disable Clock ASF (Yukon-Ext.) */
64 P_CLK_MACSEC_DIS = 1<<17,/* Disable Clock MACSec (Yukon-Ext.) */
91 /* PCI_OUR_REG_4 32 bit Our Register 4 (Yukon-ECU only) */
100 P_FORCE_ASPM_REQUEST = 1<<15, /* Force ASPM Request (A1 only) */
101 P_ASPM_GPHY_LINK_DOWN = 1<<14, /* GPHY Link Down (A1 only) */
102 P_ASPM_INT_FIFO_EMPTY = 1<<13, /* Internal FIFO Empty (A1 only) */
103 P_ASPM_CLKRUN_REQUEST = 1<<12, /* CLKRUN Request (A1 only) */
105 P_ASPM_FORCE_CLKREQ_ENA = 1<<4, /* Force CLKREQ Enable (A1b only) */
106 P_ASPM_CLKREQ_PAD_CTL = 1<<3, /* CLKREQ PAD Control (A1 only) */
107 P_ASPM_A1_MODE_SELECT = 1<<2, /* A1 Mode Select (A1 only) */
114 /* PCI_OUR_REG_5 32 bit Our Register 5 (Yukon-ECU only) */
118 P_CTL_SRESET_VMAIN_AV = 1<<30, /* Soft Reset for Vmain_av De-Glitch */
119 P_CTL_BYPASS_VMAIN_AV = 1<<29, /* Bypass En. for Vmain_av De-Glitch */
122 P_REL_PCIE_RST_DE_ASS = 1<<26, /* PCIe Reset De-Asserted */
141 P_GAT_PME_DE_ASSERTED = 1<<4, /* PME De-Asserted */
157 /* PCI_CFG_REG_1 32 bit Config Register 1 (Yukon-Ext only) */
163 P_CF1_REL_PCIE_RESET = 1<<21, /* PCI-E reset */
166 P_CF1_GAT_PCIE_RX_IDLE = 1<<19, /* PCI-E Rx Electrical idle */
167 P_CF1_GAT_PCIE_RESET = 1<<18, /* PCI-E Reset */
168 P_CF1_PRST_PHY_CLKREQ = 1<<17, /* Enable PCI-E rst & PM2PHY gen. CLKREQ */
169 P_CF1_PCIE_RST_CLKREQ = 1<<16, /* Enable PCI-E rst generate CLKREQ */
173 P_CF1_ENA_TXBMU_RD_IDLE = 1<<1, /* Enable TX BMU Read IDLE for ASPM */
174 P_CF1_ENA_TXBMU_WR_IDLE = 1<<0, /* Enable TX BMU Write IDLE for ASPM */
188 /* Yukon-Optima */
208 /* Yukon-Supreme */
230 PSM_CONFIG_REG1_DIS_FF_CHIAN_SND_INTA = 1<<11, /* Disable flip-flop chain for sndmsg_inta */
234 PSM_CONFIG_REG1_DIS_PIG = 1<<7, /* Disable Plug-in-Go SM after PSM Goes back to IDLE */
265 /* Special ISR registers (Yukon-2 only) */
308 /* Yukon-2: use RAM_BUFFER() to access the RAM buffer */
310 * The HW-Spec. calls this registers Timeout Value 0..11. But this names are
368 Y2_VMAIN_AVAIL = 1<<17,/* VMAIN available (YUKON-2 only) */
369 Y2_VAUX_AVAIL = 1<<16,/* VAUX available (YUKON-2 only) */
370 Y2_HW_WOL_ON = 1<<15,/* HW WOL On (Yukon-EC Ultra A1 only) */
371 Y2_HW_WOL_OFF = 1<<14,/* HW WOL On (Yukon-EC Ultra A1 only) */
372 Y2_ASF_ENABLE = 1<<13,/* ASF Unit Enable (YUKON-2 only) */
373 Y2_ASF_DISABLE = 1<<12,/* ASF Unit Disable (YUKON-2 only) */
374 Y2_CLK_RUN_ENA = 1<<11,/* CLK_RUN Enable (YUKON-2 only) */
375 Y2_CLK_RUN_DIS = 1<<10,/* CLK_RUN Disable (YUKON-2 only) */
376 Y2_LED_STAT_ON = 1<<9, /* Status LED On (YUKON-2 only) */
377 Y2_LED_STAT_OFF = 1<<8, /* Status LED Off (YUKON-2 only) */
389 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
413 Y2_IS_TWSI_RDY = 1<<26, /* IRQ on end of TWSI Tx */
423 Y2_IS_PSM_ACK = 1<<7, /* PSM Acknowledge (Yukon-Optima only) */
424 Y2_IS_PTP_TIST = 1<<6, /* PTP Time Stamp (Yukon-Optima only) */
425 Y2_IS_PHY_QLNK = 1<<5, /* PHY Quick Link (Yukon-Optima only) */
447 IS_IRQ_TIST_OV = 1<<13, /* Time Stamp Timer Overflow (YUKON only) */
448 IS_IRQ_SENSOR = 1<<12, /* IRQ from Sensor (YUKON only) */
469 Y2_IS_PCI_EXP = 1<<25, /* PCI-Express interrupt */
470 Y2_IS_PCI_NEXP = 1<<24, /* PCI-Express error similar to PCI error */
476 Y2_IS_TCP_TXS2 = 1<<9, /* TCP length mismatch sync Tx queue IRQ */
477 Y2_IS_TCP_TXA2 = 1<<8, /* TCP length mismatch async Tx queue IRQ */
483 Y2_IS_TCP_TXS1 = 1<<1, /* TCP length mismatch sync Tx queue IRQ */
484 Y2_IS_TCP_TXA1 = 1<<0, /* TCP length mismatch async Tx queue IRQ */
537 CHIP_ID_YUKON_XL = 0xb3, /* YUKON-2 XL */
538 CHIP_ID_YUKON_EC_U = 0xb4, /* YUKON-2 EC Ultra */
539 CHIP_ID_YUKON_EX = 0xb5, /* YUKON-2 Extreme */
540 CHIP_ID_YUKON_EC = 0xb6, /* YUKON-2 EC */
541 CHIP_ID_YUKON_FE = 0xb7, /* YUKON-2 FE */
542 CHIP_ID_YUKON_FE_P = 0xb8, /* YUKON-2 FE+ */
543 CHIP_ID_YUKON_SUPR = 0xb9, /* YUKON-2 Supreme */
544 CHIP_ID_YUKON_UL_2 = 0xba, /* YUKON-2 Ultra 2 */
545 CHIP_ID_YUKON_OPT = 0xbc, /* YUKON-2 Optima */
546 CHIP_ID_YUKON_PRM = 0xbd, /* YUKON-2 Optima Prime */
547 CHIP_ID_YUKON_OP_2 = 0xbe, /* YUKON-2 Optima 2 */
558 CHIP_REV_YU_EC_A1 = 0, /* Chip Rev. for Yukon-EC A1/A0 */
559 CHIP_REV_YU_EC_A2 = 1, /* Chip Rev. for Yukon-EC A2 */
560 CHIP_REV_YU_EC_A3 = 2, /* Chip Rev. for Yukon-EC A3 */
590 /* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */
602 /* B2_Y2_HW_RES 8 bit HW Resources (Yukon-2 only) */
612 /* B2_Y2_CLK_CTRL 32 bit Clock Frequency Control Register (Yukon-2/EC) */
641 /* Y2_PEX_PHY_ADDR/DATA PEX PHY address and data reg (Yukon-2 only) */
668 /* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */
669 /* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */
670 /* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */
671 /* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */
675 /* TXA_CTRL 8 bit Tx Arbiter Control Register */
677 TXA_ENA_FSYNC = 1<<7, /* Enable force of sync Tx queue */
678 TXA_DIS_FSYNC = 1<<6, /* Disable force of sync Tx queue */
683 TXA_ENA_ARB = 1<<1, /* Enable Tx Arbiter */
684 TXA_DIS_ARB = 1<<0, /* Disable Tx Arbiter */
688 * Bank 4 - 5
692 TXA_ITI_INI = 0x0200,/* 32 bit Tx Arb Interval Timer Init Val*/
693 TXA_ITI_VAL = 0x0204,/* 32 bit Tx Arb Interval Timer Value */
694 TXA_LIM_INI = 0x0208,/* 32 bit Tx Arb Limit Counter Init Val */
695 TXA_LIM_VAL = 0x020c,/* 32 bit Tx Arb Limit Counter Value */
696 TXA_CTRL = 0x0210,/* 8 bit Tx Arbiter Control Register */
697 TXA_TEST = 0x0211,/* 8 bit Tx Arbiter Test Register */
698 TXA_STAT = 0x0212,/* 8 bit Tx Arbiter Status Register */
716 B6_EXT_REG = 0x0300,/* External registers (GENESIS only) */
739 /* Yukon-2 */
756 F_TX_CHK_AUTO_OFF = 1<<31, /* Tx checksum auto calc off (Yukon EX) */
757 F_TX_CHK_AUTO_ON = 1<<30, /* Tx checksum auto calc off (Yukon EX) */
765 /* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
795 /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */
829 /* Receive GMAC FIFO (YUKON and Yukon-2) */
837 RX_GMF_TR_THR = 0x0c54,/* 32 bit Rx Truncation Threshold (Yukon-2) */
838 RX_GMF_UP_THR = 0x0c58,/* 16 bit Rx Upper Pause Thr (Yukon-EC_U) */
839 RX_GMF_LP_THR = 0x0c5a,/* 16 bit Rx Lower Pause Thr (Yukon-EC_U) */
840 RX_GMF_VLAN = 0x0c5c,/* 32 bit Rx VLAN Type Register (Yukon-2) */
856 /* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */
857 /* B0_XS1_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 1 */
858 /* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */
859 /* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */
862 /* Rx BMU Control / Status Registers (Yukon-2) */
873 BMU_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segment. error (Tx) */
875 BMU_STOP = 1<<9, /* Stop Rx/Tx Queue */
876 BMU_START = 1<<8, /* Start Rx/Tx Queue */
894 /* Tx BMU Control / Status Registers (Yukon-2) */
904 TBMU_TEST_BMU_TX_CHK_AUTO_OFF = 1<<31, /* BMU Tx Checksum Auto Calculation Disable */
905 TBMU_TEST_BMU_TX_CHK_AUTO_ON = 1<<30, /* BMU Tx Checksum Auto Calculation Enable */
938 /* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
974 /* Transmit GMAC FIFO (YUKON only) */
976 TX_GMF_EA = 0x0d40,/* 32 bit Tx GMAC FIFO End Address */
977 TX_GMF_AE_THR = 0x0d44,/* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
978 TX_GMF_CTRL_T = 0x0d48,/* 32 bit Tx GMAC FIFO Control/Test */
980 TX_GMF_WP = 0x0d60,/* 32 bit Tx GMAC FIFO Write Pointer */
981 TX_GMF_WSP = 0x0d64,/* 32 bit Tx GMAC FIFO Write Shadow Ptr. */
982 TX_GMF_WLEV = 0x0d68,/* 32 bit Tx GMAC FIFO Write Level */
984 TX_GMF_RP = 0x0d70,/* 32 bit Tx GMAC FIFO Read Pointer */
985 TX_GMF_RSTP = 0x0d74,/* 32 bit Tx GMAC FIFO Restart Pointer */
986 TX_GMF_RLEV = 0x0d78,/* 32 bit Tx GMAC FIFO Read Level */
988 /* Threshold values for Yukon-EC Ultra and Extreme */
990 ECU_TXFF_LEV = 0x01a0, /* Tx BMU FIFO Level */
1003 /* Time Stamp Timer Registers (YUKON only) */
1010 /* Polling Unit Registers (Yukon-2 only) */
1037 /* ASF Subsystem Registers (Yukon-2 only) */
1051 /* Status BMU Registers (Yukon-2 only)*/
1062 STAT_TX_IDX_TH = 0x0e98,/* 16 bit Status Tx Index Threshold Reg */
1065 /* FIFO Control/Status Registers (Yukon-2 only)*/
1074 /* Level and ISR Timer Registers (Yukon-2 only)*/
1079 STAT_TX_TIMER_INI = 0x0ec0,/* 32 bit Tx Timer Init. Value Reg */
1080 STAT_TX_TIMER_CNT = 0x0ec4,/* 32 bit Tx Timer Counter Reg */
1081 STAT_TX_TIMER_CTRL = 0x0ec8,/* 8 bit Tx Timer Control Reg */
1082 STAT_TX_TIMER_TEST = 0x0ec9,/* 8 bit Tx Timer Test Reg */
1098 /* GMAC and GPHY Control Registers (YUKON only) */
1106 /* Wake-up Frame Pattern Match Control Registers (YUKON only) */
1113 /* WOL Pattern Length Registers (YUKON only) */
1117 /* WOL Pattern Counter Registers (YUKON only) */
1135 * Marvel-PHY Registers, indirect addressed over GMAC
1142 PHY_MARV_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
1144 PHY_MARV_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
1147 /* Marvel-specific registers */
1148 PHY_MARV_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
1149 PHY_MARV_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
1158 PHY_MARV_PORT_IRQ = 0x17,/* 16 bit r/o Port 0 IRQ (88E1111 only) */
1167 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1179 PHY_CT_ANE = 1<<12, /* Bit 12: Auto-Negotiation Enabled */
1182 PHY_CT_RE_CFG = 1<<9, /* Bit 9: (sc) Restart Auto-Negotiation */
1198 PHY_ST_AN_OVER = 1<<5, /* Bit 5: Auto-Negotiation Over */
1200 PHY_ST_AN_CAP = 1<<3, /* Bit 3: Auto-Negotiation Capability */
1222 PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */
1223 PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */
1224 PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */
1225 PHY_MARV_ID1_FE = 0x0C83, /* Yukon-FE (PHY 88E3082 Rev.A1) */
1226 PHY_MARV_ID1_ECU= 0x0CB0, /* Yukon-ECU (PHY 88E1149 Rev.B2?) */
1238 PHY_AN_100FULL = 1<<8, /* Bit 8: Try for 100mbps full-duplex */
1239 PHY_AN_100HALF = 1<<7, /* Bit 7: Try for 100mbps half-duplex */
1240 PHY_AN_10FULL = 1<<6, /* Bit 6: Try for 10mbps full-duplex */
1241 PHY_AN_10HALF = 1<<5, /* Bit 5: Try for 10mbps half-duplex */
1242 PHY_AN_CSMA = 1<<0, /* Bit 0: Only selector supported */
1249 /***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1250 /***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1262 /** Marvell-Specific */
1270 PHY_M_AN_100_T4 = 1<<9, /* Not cap. 100Base-T4 (always 0) */
1271 PHY_M_AN_100_FD = 1<<8, /* Advertise 100Base-TX Full Duplex */
1272 PHY_M_AN_100_HD = 1<<7, /* Advertise 100Base-TX Half Duplex */
1273 PHY_M_AN_10_FD = 1<<6, /* Advertise 10Base-TX Full Duplex */
1274 PHY_M_AN_10_HD = 1<<5, /* Advertise 10Base-TX Half Duplex */
1278 /* special defines for FIBER (88E1011S only) */
1282 PHY_M_AN_1000X_AHD = 1<<6, /* Advertise 10000Base-X Half Duplex */
1283 PHY_M_AN_1000X_AFD = 1<<5, /* Advertise 10000Base-X Full Duplex */
1294 /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1299 PHY_M_1000C_MPD = 1<<10, /* Multi-Port Device */
1306 PHY_M_PC_TX_FFD_MSK = 3<<14,/* Bit 15..14: Tx FIFO Depth Mask */
1333 /* for Yukon-EC Ultra Gigabit Ethernet PHY (88E1149 only) */
1339 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1368 PHY_M_PS_TX_P_EN = 1<<3, /* Tx Pause Enabled */
1376 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1383 PHY_M_IS_AN_ERROR = 1<<15, /* Auto-Negotiation Error */
1387 PHY_M_IS_AN_COMPL = 1<<11, /* Auto-Negotiation Completed */
1408 PHY_M_EC_ENA_BC_EXT = 1<<15, /* Enable Block Carr. Ext. (88E1111 only) */
1409 PHY_M_EC_ENA_LIN_LB = 1<<14, /* Enable Line Loopback (88E1111 only) */
1411 PHY_M_EC_DIS_LINK_P = 1<<12, /* Disable Link Pulses (88E1111 only) */
1413 /* (88E1011 only) */
1415 /* (88E1011 only) */
1417 /* (88E1111 only) */
1418 PHY_M_EC_DOWN_S_ENA = 1<<8, /* Downshift Enable (88E1111 only) */
1422 PHY_M_EC_FIB_AN_ENA = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */
1423 PHY_M_EC_DTE_D_ENA = 1<<2, /* DTE Detect Enable (88E1111 only) */
1424 PHY_M_EC_TX_TIM_CT = 1<<1, /* RGMII Tx Timing Control */
1425 PHY_M_EC_TRANS_DIS = 1<<0, /* Transmitter Disable (88E1111 only) */
1427 PHY_M_10B_TE_ENABLE = 1<<7, /* 10Base-Te Enable (88E8079 and above) */
1438 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1460 PHY_M_LEDC_DP_C_LSB = 1<<7, /* Duplex Control (LSB, 88E1111 only) */
1461 PHY_M_LEDC_TX_C_LSB = 1<<6, /* Tx Control (LSB, 88E1111 only) */
1463 /* (88E1111 only) */
1468 /* (88E1011 only) */
1470 PHY_M_LEDC_DP_C_MSB = 1<<2, /* Duplex Control (MSB, 88E1111 only) */
1472 PHY_M_LEDC_TX_CTRL = 1<<0, /* Tx Activity / Link */
1473 PHY_M_LEDC_TX_C_MSB = 1<<0, /* Tx Control (MSB, 88E1111 only) */
1524 #define PHY_M_LED_MO_TX(x) ((x)<<0) /* Bit 1.. 0: Tx */
1551 /* (88E1111 only) */
1554 PHY_M_DTE_POW_STAT = 1<<4, /* DTE Power Status (88E1111 only) */
1558 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1594 PHY_M_FESC_SEL_CL_A = 1<<0, /* Select Class A driver (100B-TX) */
1597 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1605 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1609 PHY_M_MAC_GMIF_PUP = 1<<3, /* GMII Power Up (88E1149 only) */
1610 PHY_M_MAC_MD_AUTO = 3,/* Auto Copper/1000Base-X */
1611 PHY_M_MAC_MD_COPPER = 5,/* Copper only */
1612 PHY_M_MAC_MD_1000BX = 7,/* 1000Base-X only */
1636 GM_TX_FLOW_CTRL = 0x0010, /* 16 bit r/w Transmit Flow-Control */
1654 GM_TX_IRQ_SRC = 0x0044, /* 16 bit r/o Tx Overflow IRQ Source */
1656 GM_TR_IRQ_SRC = 0x004c, /* 16 bit r/o Tx/Rx Over. IRQ Source */
1659 GM_TX_IRQ_MSK = 0x0050, /* 16 bit r/w Tx Overflow IRQ Mask */
1661 GM_TR_IRQ_MSK = 0x0058, /* 16 bit r/w Tx/Rx Over. IRQ Mask */
1674 * MIB Counters base address definitions (low word) -
1691 GM_RXF_127B = GM_MIB_CNT_BASE + 104,/* 65-127 Byte Rx Frame */
1692 GM_RXF_255B = GM_MIB_CNT_BASE + 112,/* 128-255 Byte Rx Frame */
1693 GM_RXF_511B = GM_MIB_CNT_BASE + 120,/* 256-511 Byte Rx Frame */
1694 GM_RXF_1023B = GM_MIB_CNT_BASE + 128,/* 512-1023 Byte Rx Frame */
1695 GM_RXF_1518B = GM_MIB_CNT_BASE + 136,/* 1024-1518 Byte Rx Frame */
1696 GM_RXF_MAX_SZ = GM_MIB_CNT_BASE + 144,/* 1519-MaxSize Byte Rx Frame */
1707 GM_TXF_64B = GM_MIB_CNT_BASE + 240,/* 64 Byte Tx Frame */
1708 GM_TXF_127B = GM_MIB_CNT_BASE + 248,/* 65-127 Byte Tx Frame */
1709 GM_TXF_255B = GM_MIB_CNT_BASE + 256,/* 128-255 Byte Tx Frame */
1710 GM_TXF_511B = GM_MIB_CNT_BASE + 264,/* 256-511 Byte Tx Frame */
1711 GM_TXF_1023B = GM_MIB_CNT_BASE + 272,/* 512-1023 Byte Tx Frame */
1712 GM_TXF_1518B = GM_MIB_CNT_BASE + 280,/* 1024-1518 Byte Tx Frame */
1713 GM_TXF_MAX_SZ = GM_MIB_CNT_BASE + 288,/* 1519-MaxSize Byte Tx Frame */
1715 GM_TXF_COL = GM_MIB_CNT_BASE + 304,/* Tx Collision */
1716 GM_TXF_LAT_COL = GM_MIB_CNT_BASE + 312,/* Tx Late Collision */
1717 GM_TXF_ABO_COL = GM_MIB_CNT_BASE + 320,/* Tx aborted due to Exces. Col. */
1718 GM_TXF_MUL_COL = GM_MIB_CNT_BASE + 328,/* Tx Multiple Collision */
1719 GM_TXF_SNG_COL = GM_MIB_CNT_BASE + 336,/* Tx Single Collision */
1720 GM_TXE_FIFO_UR = GM_MIB_CNT_BASE + 344,/* Tx FIFO Underrun Event */
1728 GM_GPSR_FC_TX_DIS = 1<<13, /* Bit 13: Tx Flow-Control Mode Disabled */
1731 GM_GPSR_TX_ACTIVE = 1<<10, /* Bit 10: Tx in Progress */
1738 GM_GPSR_FC_RX_DIS = 1<<2, /* Bit 2: Rx Flow-Control Mode Disabled */
1745 GM_GPCR_FC_TX_DIS = 1<<13, /* Bit 13: Disable Tx Flow-Control Mode */
1754 GM_GPCR_FC_RX_DIS = 1<<4, /* Bit 4: Disable Rx Flow-Control Mode */
1756 GM_GPCR_AU_DUP_DIS = 1<<2, /* Bit 2: Disable Auto-Update Duplex */
1757 GM_GPCR_AU_FCT_DIS = 1<<1, /* Bit 1: Disable Auto-Update Flow-C. */
1758 GM_GPCR_AU_SPD_DIS = 1<<0, /* Bit 0: Disable Auto-Update Speed */
1765 GM_TXCR_FORCE_JAM = 1<<15, /* Bit 15: Force Jam / Flow-Control */
1778 GM_RXCR_CRC_DIS = 1<<13, /* Bit 13: Remove 4-byte CRC */
1804 GM_SMOD_LIMIT_4 = 1<<10, /* 4 consecutive Tx trials */
1808 GM_NEW_FLOW_CTRL = 1<<6, /* Enable New Flow-Control */
1810 GM_SMOD_IPG_MSK = 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */
1847 GMR_FS_GOOD_FC = 1<<7, /* Good Flow-Control Packet */
1848 GMR_FS_BAD_FC = 1<<6, /* Bad Flow-Control Packet */
1907 /* RX_GMF_FL_CTRL 16 bit Rx GMAC FIFO Flush Control (Yukon-Supreme) */
1917 RX_FLSH_MISSPKT_ENA = 1<<1, /* RX Flush Miss-Packet Enable */
1918 RX_FLSH_MISSPKT_DIS = 1<<0, /* RX Flush Miss-Packet Disable */
1921 /* TX_GMF_EA 32 bit Tx GMAC FIFO End Address */
1923 TX_DYN_WM_ENA = 3, /* Yukon-FE+ specific */
1926 /* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */
1941 GMF_CLI_TX_FU = 1<<6, /* Clear IRQ Tx FIFO Underrun */
1942 GMF_CLI_TX_FC = 1<<5, /* Clear IRQ Tx Frame Complete */
1943 GMF_CLI_TX_PE = 1<<4, /* Clear IRQ Tx Parity Error */
1946 /* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */
2004 /* STAT_CTRL 32 bit Status BMU control register (Yukon-2 only) */
2013 /* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */
2019 GMC_BYP_MACSECTX_ON = 1<<11,/* Bypass macsec TX */
2020 GMC_BYP_MACSECTX_OFF= 1<<10,/* Bypass macsec TX off*/
2034 /* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */
2036 GPC_TX_PAUSE = 1<<30, /* Tx pause enabled (ro) */
2062 /* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */
2063 /* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */
2075 /* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */
2139 /* YUKON-2 STATUS opcodes defines */
2228 u16 tx_next; /* debug only */
2285 #define SKY2_HW_AUTO_TX_SUM 0x00000040 /* new IP decode for Tx */
2311 return !(hw->flags & SKY2_HW_FIBRE_PHY); in sky2_is_copper()
2317 return readl(hw->regs + reg); in sky2_read32()
2322 return readw(hw->regs + reg); in sky2_read16()
2327 return readb(hw->regs + reg); in sky2_read8()
2332 writel(val, hw->regs + reg); in sky2_write32()
2337 writew(val, hw->regs + reg); in sky2_write16()
2342 writeb(val, hw->regs + reg); in sky2_write8()
2347 (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg))