1*b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 2adfc5217SJeff Kirsher #ifndef _B44_H 3adfc5217SJeff Kirsher #define _B44_H 4adfc5217SJeff Kirsher 52729b427SFlorian Fainelli #include <linux/brcmphy.h> 62729b427SFlorian Fainelli 7adfc5217SJeff Kirsher /* Register layout. (These correspond to struct _bcmenettregs in bcm4400.) */ 8adfc5217SJeff Kirsher #define B44_DEVCTRL 0x0000UL /* Device Control */ 9adfc5217SJeff Kirsher #define DEVCTRL_MPM 0x00000040 /* Magic Packet PME Enable (B0 only) */ 10adfc5217SJeff Kirsher #define DEVCTRL_PFE 0x00000080 /* Pattern Filtering Enable */ 11adfc5217SJeff Kirsher #define DEVCTRL_IPP 0x00000400 /* Internal EPHY Present */ 12adfc5217SJeff Kirsher #define DEVCTRL_EPR 0x00008000 /* EPHY Reset */ 13adfc5217SJeff Kirsher #define DEVCTRL_PME 0x00001000 /* PHY Mode Enable */ 14adfc5217SJeff Kirsher #define DEVCTRL_PMCE 0x00002000 /* PHY Mode Clocks Enable */ 15adfc5217SJeff Kirsher #define DEVCTRL_PADDR 0x0007c000 /* PHY Address */ 16adfc5217SJeff Kirsher #define DEVCTRL_PADDR_SHIFT 18 17adfc5217SJeff Kirsher #define B44_BIST_STAT 0x000CUL /* Built-In Self-Test Status */ 18adfc5217SJeff Kirsher #define B44_WKUP_LEN 0x0010UL /* Wakeup Length */ 19adfc5217SJeff Kirsher #define WKUP_LEN_P0_MASK 0x0000007f /* Pattern 0 */ 20adfc5217SJeff Kirsher #define WKUP_LEN_D0 0x00000080 21adfc5217SJeff Kirsher #define WKUP_LEN_P1_MASK 0x00007f00 /* Pattern 1 */ 22adfc5217SJeff Kirsher #define WKUP_LEN_P1_SHIFT 8 23adfc5217SJeff Kirsher #define WKUP_LEN_D1 0x00008000 24adfc5217SJeff Kirsher #define WKUP_LEN_P2_MASK 0x007f0000 /* Pattern 2 */ 25adfc5217SJeff Kirsher #define WKUP_LEN_P2_SHIFT 16 26adfc5217SJeff Kirsher #define WKUP_LEN_D2 0x00000000 27adfc5217SJeff Kirsher #define WKUP_LEN_P3_MASK 0x7f000000 /* Pattern 3 */ 28adfc5217SJeff Kirsher #define WKUP_LEN_P3_SHIFT 24 29adfc5217SJeff Kirsher #define WKUP_LEN_D3 0x80000000 30adfc5217SJeff Kirsher #define WKUP_LEN_DISABLE 0x80808080 31adfc5217SJeff Kirsher #define WKUP_LEN_ENABLE_TWO 0x80800000 32adfc5217SJeff Kirsher #define WKUP_LEN_ENABLE_THREE 0x80000000 33adfc5217SJeff Kirsher #define B44_ISTAT 0x0020UL /* Interrupt Status */ 34adfc5217SJeff Kirsher #define ISTAT_LS 0x00000020 /* Link Change (B0 only) */ 35adfc5217SJeff Kirsher #define ISTAT_PME 0x00000040 /* Power Management Event */ 36adfc5217SJeff Kirsher #define ISTAT_TO 0x00000080 /* General Purpose Timeout */ 37adfc5217SJeff Kirsher #define ISTAT_DSCE 0x00000400 /* Descriptor Error */ 38adfc5217SJeff Kirsher #define ISTAT_DATAE 0x00000800 /* Data Error */ 39adfc5217SJeff Kirsher #define ISTAT_DPE 0x00001000 /* Descr. Protocol Error */ 40adfc5217SJeff Kirsher #define ISTAT_RDU 0x00002000 /* Receive Descr. Underflow */ 41adfc5217SJeff Kirsher #define ISTAT_RFO 0x00004000 /* Receive FIFO Overflow */ 42adfc5217SJeff Kirsher #define ISTAT_TFU 0x00008000 /* Transmit FIFO Underflow */ 43adfc5217SJeff Kirsher #define ISTAT_RX 0x00010000 /* RX Interrupt */ 44adfc5217SJeff Kirsher #define ISTAT_TX 0x01000000 /* TX Interrupt */ 45adfc5217SJeff Kirsher #define ISTAT_EMAC 0x04000000 /* EMAC Interrupt */ 46adfc5217SJeff Kirsher #define ISTAT_MII_WRITE 0x08000000 /* MII Write Interrupt */ 47adfc5217SJeff Kirsher #define ISTAT_MII_READ 0x10000000 /* MII Read Interrupt */ 48adfc5217SJeff Kirsher #define ISTAT_ERRORS (ISTAT_DSCE|ISTAT_DATAE|ISTAT_DPE|ISTAT_RDU|ISTAT_RFO|ISTAT_TFU) 49adfc5217SJeff Kirsher #define B44_IMASK 0x0024UL /* Interrupt Mask */ 50adfc5217SJeff Kirsher #define IMASK_DEF (ISTAT_ERRORS | ISTAT_TO | ISTAT_RX | ISTAT_TX) 51adfc5217SJeff Kirsher #define B44_GPTIMER 0x0028UL /* General Purpose Timer */ 52adfc5217SJeff Kirsher #define B44_ADDR_LO 0x0088UL /* ENET Address Lo (B0 only) */ 53adfc5217SJeff Kirsher #define B44_ADDR_HI 0x008CUL /* ENET Address Hi (B0 only) */ 54adfc5217SJeff Kirsher #define B44_FILT_ADDR 0x0090UL /* ENET Filter Address */ 55adfc5217SJeff Kirsher #define B44_FILT_DATA 0x0094UL /* ENET Filter Data */ 56adfc5217SJeff Kirsher #define B44_TXBURST 0x00A0UL /* TX Max Burst Length */ 57adfc5217SJeff Kirsher #define B44_RXBURST 0x00A4UL /* RX Max Burst Length */ 58adfc5217SJeff Kirsher #define B44_MAC_CTRL 0x00A8UL /* MAC Control */ 59adfc5217SJeff Kirsher #define MAC_CTRL_CRC32_ENAB 0x00000001 /* CRC32 Generation Enable */ 60adfc5217SJeff Kirsher #define MAC_CTRL_PHY_PDOWN 0x00000004 /* Onchip EPHY Powerdown */ 61adfc5217SJeff Kirsher #define MAC_CTRL_PHY_EDET 0x00000008 /* Onchip EPHY Energy Detected */ 62adfc5217SJeff Kirsher #define MAC_CTRL_PHY_LEDCTRL 0x000000e0 /* Onchip EPHY LED Control */ 63adfc5217SJeff Kirsher #define MAC_CTRL_PHY_LEDCTRL_SHIFT 5 64adfc5217SJeff Kirsher #define B44_MAC_FLOW 0x00ACUL /* MAC Flow Control */ 65adfc5217SJeff Kirsher #define MAC_FLOW_RX_HI_WATER 0x000000ff /* Receive FIFO HI Water Mark */ 66adfc5217SJeff Kirsher #define MAC_FLOW_PAUSE_ENAB 0x00008000 /* Enable Pause Frame Generation */ 67adfc5217SJeff Kirsher #define B44_RCV_LAZY 0x0100UL /* Lazy Interrupt Control */ 68adfc5217SJeff Kirsher #define RCV_LAZY_TO_MASK 0x00ffffff /* Timeout */ 69adfc5217SJeff Kirsher #define RCV_LAZY_FC_MASK 0xff000000 /* Frame Count */ 70adfc5217SJeff Kirsher #define RCV_LAZY_FC_SHIFT 24 71adfc5217SJeff Kirsher #define B44_DMATX_CTRL 0x0200UL /* DMA TX Control */ 72adfc5217SJeff Kirsher #define DMATX_CTRL_ENABLE 0x00000001 /* Enable */ 73adfc5217SJeff Kirsher #define DMATX_CTRL_SUSPEND 0x00000002 /* Suepend Request */ 74adfc5217SJeff Kirsher #define DMATX_CTRL_LPBACK 0x00000004 /* Loopback Enable */ 75adfc5217SJeff Kirsher #define DMATX_CTRL_FAIRPRIOR 0x00000008 /* Fair Priority */ 76adfc5217SJeff Kirsher #define DMATX_CTRL_FLUSH 0x00000010 /* Flush Request */ 77adfc5217SJeff Kirsher #define B44_DMATX_ADDR 0x0204UL /* DMA TX Descriptor Ring Address */ 78adfc5217SJeff Kirsher #define B44_DMATX_PTR 0x0208UL /* DMA TX Last Posted Descriptor */ 79adfc5217SJeff Kirsher #define B44_DMATX_STAT 0x020CUL /* DMA TX Current Active Desc. + Status */ 80adfc5217SJeff Kirsher #define DMATX_STAT_CDMASK 0x00000fff /* Current Descriptor Mask */ 81adfc5217SJeff Kirsher #define DMATX_STAT_SMASK 0x0000f000 /* State Mask */ 82adfc5217SJeff Kirsher #define DMATX_STAT_SDISABLED 0x00000000 /* State Disabled */ 83adfc5217SJeff Kirsher #define DMATX_STAT_SACTIVE 0x00001000 /* State Active */ 84adfc5217SJeff Kirsher #define DMATX_STAT_SIDLE 0x00002000 /* State Idle Wait */ 85adfc5217SJeff Kirsher #define DMATX_STAT_SSTOPPED 0x00003000 /* State Stopped */ 86adfc5217SJeff Kirsher #define DMATX_STAT_SSUSP 0x00004000 /* State Suspend Pending */ 87adfc5217SJeff Kirsher #define DMATX_STAT_EMASK 0x000f0000 /* Error Mask */ 88adfc5217SJeff Kirsher #define DMATX_STAT_ENONE 0x00000000 /* Error None */ 89adfc5217SJeff Kirsher #define DMATX_STAT_EDPE 0x00010000 /* Error Desc. Protocol Error */ 90adfc5217SJeff Kirsher #define DMATX_STAT_EDFU 0x00020000 /* Error Data FIFO Underrun */ 91adfc5217SJeff Kirsher #define DMATX_STAT_EBEBR 0x00030000 /* Error Bus Error on Buffer Read */ 92adfc5217SJeff Kirsher #define DMATX_STAT_EBEDA 0x00040000 /* Error Bus Error on Desc. Access */ 93adfc5217SJeff Kirsher #define DMATX_STAT_FLUSHED 0x00100000 /* Flushed */ 94adfc5217SJeff Kirsher #define B44_DMARX_CTRL 0x0210UL /* DMA RX Control */ 95adfc5217SJeff Kirsher #define DMARX_CTRL_ENABLE 0x00000001 /* Enable */ 96adfc5217SJeff Kirsher #define DMARX_CTRL_ROMASK 0x000000fe /* Receive Offset Mask */ 97adfc5217SJeff Kirsher #define DMARX_CTRL_ROSHIFT 1 /* Receive Offset Shift */ 98adfc5217SJeff Kirsher #define B44_DMARX_ADDR 0x0214UL /* DMA RX Descriptor Ring Address */ 99adfc5217SJeff Kirsher #define B44_DMARX_PTR 0x0218UL /* DMA RX Last Posted Descriptor */ 100adfc5217SJeff Kirsher #define B44_DMARX_STAT 0x021CUL /* DMA RX Current Active Desc. + Status */ 101adfc5217SJeff Kirsher #define DMARX_STAT_CDMASK 0x00000fff /* Current Descriptor Mask */ 102adfc5217SJeff Kirsher #define DMARX_STAT_SMASK 0x0000f000 /* State Mask */ 103adfc5217SJeff Kirsher #define DMARX_STAT_SDISABLED 0x00000000 /* State Disabled */ 104adfc5217SJeff Kirsher #define DMARX_STAT_SACTIVE 0x00001000 /* State Active */ 105adfc5217SJeff Kirsher #define DMARX_STAT_SIDLE 0x00002000 /* State Idle Wait */ 106adfc5217SJeff Kirsher #define DMARX_STAT_SSTOPPED 0x00003000 /* State Stopped */ 107adfc5217SJeff Kirsher #define DMARX_STAT_EMASK 0x000f0000 /* Error Mask */ 108adfc5217SJeff Kirsher #define DMARX_STAT_ENONE 0x00000000 /* Error None */ 109adfc5217SJeff Kirsher #define DMARX_STAT_EDPE 0x00010000 /* Error Desc. Protocol Error */ 110adfc5217SJeff Kirsher #define DMARX_STAT_EDFO 0x00020000 /* Error Data FIFO Overflow */ 111adfc5217SJeff Kirsher #define DMARX_STAT_EBEBW 0x00030000 /* Error Bus Error on Buffer Write */ 112adfc5217SJeff Kirsher #define DMARX_STAT_EBEDA 0x00040000 /* Error Bus Error on Desc. Access */ 113adfc5217SJeff Kirsher #define B44_DMAFIFO_AD 0x0220UL /* DMA FIFO Diag Address */ 114adfc5217SJeff Kirsher #define DMAFIFO_AD_OMASK 0x0000ffff /* Offset Mask */ 115adfc5217SJeff Kirsher #define DMAFIFO_AD_SMASK 0x000f0000 /* Select Mask */ 116adfc5217SJeff Kirsher #define DMAFIFO_AD_SXDD 0x00000000 /* Select Transmit DMA Data */ 117adfc5217SJeff Kirsher #define DMAFIFO_AD_SXDP 0x00010000 /* Select Transmit DMA Pointers */ 118adfc5217SJeff Kirsher #define DMAFIFO_AD_SRDD 0x00040000 /* Select Receive DMA Data */ 119adfc5217SJeff Kirsher #define DMAFIFO_AD_SRDP 0x00050000 /* Select Receive DMA Pointers */ 120adfc5217SJeff Kirsher #define DMAFIFO_AD_SXFD 0x00080000 /* Select Transmit FIFO Data */ 121adfc5217SJeff Kirsher #define DMAFIFO_AD_SXFP 0x00090000 /* Select Transmit FIFO Pointers */ 122adfc5217SJeff Kirsher #define DMAFIFO_AD_SRFD 0x000c0000 /* Select Receive FIFO Data */ 123adfc5217SJeff Kirsher #define DMAFIFO_AD_SRFP 0x000c0000 /* Select Receive FIFO Pointers */ 124adfc5217SJeff Kirsher #define B44_DMAFIFO_LO 0x0224UL /* DMA FIFO Diag Low Data */ 125adfc5217SJeff Kirsher #define B44_DMAFIFO_HI 0x0228UL /* DMA FIFO Diag High Data */ 126adfc5217SJeff Kirsher #define B44_RXCONFIG 0x0400UL /* EMAC RX Config */ 127adfc5217SJeff Kirsher #define RXCONFIG_DBCAST 0x00000001 /* Disable Broadcast */ 128adfc5217SJeff Kirsher #define RXCONFIG_ALLMULTI 0x00000002 /* Accept All Multicast */ 129adfc5217SJeff Kirsher #define RXCONFIG_NORX_WHILE_TX 0x00000004 /* Receive Disable While Transmitting */ 130adfc5217SJeff Kirsher #define RXCONFIG_PROMISC 0x00000008 /* Promiscuous Enable */ 131adfc5217SJeff Kirsher #define RXCONFIG_LPBACK 0x00000010 /* Loopback Enable */ 132adfc5217SJeff Kirsher #define RXCONFIG_FLOW 0x00000020 /* Flow Control Enable */ 133adfc5217SJeff Kirsher #define RXCONFIG_FLOW_ACCEPT 0x00000040 /* Accept Unicast Flow Control Frame */ 134adfc5217SJeff Kirsher #define RXCONFIG_RFILT 0x00000080 /* Reject Filter */ 135adfc5217SJeff Kirsher #define RXCONFIG_CAM_ABSENT 0x00000100 /* CAM Absent */ 136adfc5217SJeff Kirsher #define B44_RXMAXLEN 0x0404UL /* EMAC RX Max Packet Length */ 137adfc5217SJeff Kirsher #define B44_TXMAXLEN 0x0408UL /* EMAC TX Max Packet Length */ 138adfc5217SJeff Kirsher #define B44_MDIO_CTRL 0x0410UL /* EMAC MDIO Control */ 139adfc5217SJeff Kirsher #define MDIO_CTRL_MAXF_MASK 0x0000007f /* MDC Frequency */ 140adfc5217SJeff Kirsher #define MDIO_CTRL_PREAMBLE 0x00000080 /* MII Preamble Enable */ 141adfc5217SJeff Kirsher #define B44_MDIO_DATA 0x0414UL /* EMAC MDIO Data */ 142adfc5217SJeff Kirsher #define MDIO_DATA_DATA 0x0000ffff /* R/W Data */ 143adfc5217SJeff Kirsher #define MDIO_DATA_TA_MASK 0x00030000 /* Turnaround Value */ 144adfc5217SJeff Kirsher #define MDIO_DATA_TA_SHIFT 16 145adfc5217SJeff Kirsher #define MDIO_TA_VALID 2 146adfc5217SJeff Kirsher #define MDIO_DATA_RA_MASK 0x007c0000 /* Register Address */ 147adfc5217SJeff Kirsher #define MDIO_DATA_RA_SHIFT 18 148adfc5217SJeff Kirsher #define MDIO_DATA_PMD_MASK 0x0f800000 /* Physical Media Device */ 149adfc5217SJeff Kirsher #define MDIO_DATA_PMD_SHIFT 23 150adfc5217SJeff Kirsher #define MDIO_DATA_OP_MASK 0x30000000 /* Opcode */ 151adfc5217SJeff Kirsher #define MDIO_DATA_OP_SHIFT 28 152adfc5217SJeff Kirsher #define MDIO_OP_WRITE 1 153adfc5217SJeff Kirsher #define MDIO_OP_READ 2 154adfc5217SJeff Kirsher #define MDIO_DATA_SB_MASK 0xc0000000 /* Start Bits */ 155adfc5217SJeff Kirsher #define MDIO_DATA_SB_SHIFT 30 156adfc5217SJeff Kirsher #define MDIO_DATA_SB_START 0x40000000 /* Start Of Frame */ 157adfc5217SJeff Kirsher #define B44_EMAC_IMASK 0x0418UL /* EMAC Interrupt Mask */ 158adfc5217SJeff Kirsher #define B44_EMAC_ISTAT 0x041CUL /* EMAC Interrupt Status */ 159adfc5217SJeff Kirsher #define EMAC_INT_MII 0x00000001 /* MII MDIO Interrupt */ 160adfc5217SJeff Kirsher #define EMAC_INT_MIB 0x00000002 /* MIB Interrupt */ 161adfc5217SJeff Kirsher #define EMAC_INT_FLOW 0x00000003 /* Flow Control Interrupt */ 162adfc5217SJeff Kirsher #define B44_CAM_DATA_LO 0x0420UL /* EMAC CAM Data Low */ 163adfc5217SJeff Kirsher #define B44_CAM_DATA_HI 0x0424UL /* EMAC CAM Data High */ 164adfc5217SJeff Kirsher #define CAM_DATA_HI_VALID 0x00010000 /* Valid Bit */ 165adfc5217SJeff Kirsher #define B44_CAM_CTRL 0x0428UL /* EMAC CAM Control */ 166adfc5217SJeff Kirsher #define CAM_CTRL_ENABLE 0x00000001 /* CAM Enable */ 167adfc5217SJeff Kirsher #define CAM_CTRL_MSEL 0x00000002 /* Mask Select */ 168adfc5217SJeff Kirsher #define CAM_CTRL_READ 0x00000004 /* Read */ 169adfc5217SJeff Kirsher #define CAM_CTRL_WRITE 0x00000008 /* Read */ 170adfc5217SJeff Kirsher #define CAM_CTRL_INDEX_MASK 0x003f0000 /* Index Mask */ 171adfc5217SJeff Kirsher #define CAM_CTRL_INDEX_SHIFT 16 172adfc5217SJeff Kirsher #define CAM_CTRL_BUSY 0x80000000 /* CAM Busy */ 173adfc5217SJeff Kirsher #define B44_ENET_CTRL 0x042CUL /* EMAC ENET Control */ 174adfc5217SJeff Kirsher #define ENET_CTRL_ENABLE 0x00000001 /* EMAC Enable */ 175adfc5217SJeff Kirsher #define ENET_CTRL_DISABLE 0x00000002 /* EMAC Disable */ 176adfc5217SJeff Kirsher #define ENET_CTRL_SRST 0x00000004 /* EMAC Soft Reset */ 177adfc5217SJeff Kirsher #define ENET_CTRL_EPSEL 0x00000008 /* External PHY Select */ 178adfc5217SJeff Kirsher #define B44_TX_CTRL 0x0430UL /* EMAC TX Control */ 179adfc5217SJeff Kirsher #define TX_CTRL_DUPLEX 0x00000001 /* Full Duplex */ 180adfc5217SJeff Kirsher #define TX_CTRL_FMODE 0x00000002 /* Flow Mode */ 181adfc5217SJeff Kirsher #define TX_CTRL_SBENAB 0x00000004 /* Single Backoff Enable */ 182adfc5217SJeff Kirsher #define TX_CTRL_SMALL_SLOT 0x00000008 /* Small Slottime */ 183adfc5217SJeff Kirsher #define B44_TX_WMARK 0x0434UL /* EMAC TX Watermark */ 184adfc5217SJeff Kirsher #define B44_MIB_CTRL 0x0438UL /* EMAC MIB Control */ 185adfc5217SJeff Kirsher #define MIB_CTRL_CLR_ON_READ 0x00000001 /* Autoclear on Read */ 186adfc5217SJeff Kirsher #define B44_TX_GOOD_O 0x0500UL /* MIB TX Good Octets */ 187adfc5217SJeff Kirsher #define B44_TX_GOOD_P 0x0504UL /* MIB TX Good Packets */ 188adfc5217SJeff Kirsher #define B44_TX_O 0x0508UL /* MIB TX Octets */ 189adfc5217SJeff Kirsher #define B44_TX_P 0x050CUL /* MIB TX Packets */ 190adfc5217SJeff Kirsher #define B44_TX_BCAST 0x0510UL /* MIB TX Broadcast Packets */ 191adfc5217SJeff Kirsher #define B44_TX_MCAST 0x0514UL /* MIB TX Multicast Packets */ 192adfc5217SJeff Kirsher #define B44_TX_64 0x0518UL /* MIB TX <= 64 byte Packets */ 193adfc5217SJeff Kirsher #define B44_TX_65_127 0x051CUL /* MIB TX 65 to 127 byte Packets */ 194adfc5217SJeff Kirsher #define B44_TX_128_255 0x0520UL /* MIB TX 128 to 255 byte Packets */ 195adfc5217SJeff Kirsher #define B44_TX_256_511 0x0524UL /* MIB TX 256 to 511 byte Packets */ 196adfc5217SJeff Kirsher #define B44_TX_512_1023 0x0528UL /* MIB TX 512 to 1023 byte Packets */ 197adfc5217SJeff Kirsher #define B44_TX_1024_MAX 0x052CUL /* MIB TX 1024 to max byte Packets */ 198adfc5217SJeff Kirsher #define B44_TX_JABBER 0x0530UL /* MIB TX Jabber Packets */ 199adfc5217SJeff Kirsher #define B44_TX_OSIZE 0x0534UL /* MIB TX Oversize Packets */ 200adfc5217SJeff Kirsher #define B44_TX_FRAG 0x0538UL /* MIB TX Fragment Packets */ 201adfc5217SJeff Kirsher #define B44_TX_URUNS 0x053CUL /* MIB TX Underruns */ 202adfc5217SJeff Kirsher #define B44_TX_TCOLS 0x0540UL /* MIB TX Total Collisions */ 203adfc5217SJeff Kirsher #define B44_TX_SCOLS 0x0544UL /* MIB TX Single Collisions */ 204adfc5217SJeff Kirsher #define B44_TX_MCOLS 0x0548UL /* MIB TX Multiple Collisions */ 205adfc5217SJeff Kirsher #define B44_TX_ECOLS 0x054CUL /* MIB TX Excessive Collisions */ 206adfc5217SJeff Kirsher #define B44_TX_LCOLS 0x0550UL /* MIB TX Late Collisions */ 207adfc5217SJeff Kirsher #define B44_TX_DEFERED 0x0554UL /* MIB TX Defered Packets */ 208adfc5217SJeff Kirsher #define B44_TX_CLOST 0x0558UL /* MIB TX Carrier Lost */ 209adfc5217SJeff Kirsher #define B44_TX_PAUSE 0x055CUL /* MIB TX Pause Packets */ 210adfc5217SJeff Kirsher #define B44_RX_GOOD_O 0x0580UL /* MIB RX Good Octets */ 211adfc5217SJeff Kirsher #define B44_RX_GOOD_P 0x0584UL /* MIB RX Good Packets */ 212adfc5217SJeff Kirsher #define B44_RX_O 0x0588UL /* MIB RX Octets */ 213adfc5217SJeff Kirsher #define B44_RX_P 0x058CUL /* MIB RX Packets */ 214adfc5217SJeff Kirsher #define B44_RX_BCAST 0x0590UL /* MIB RX Broadcast Packets */ 215adfc5217SJeff Kirsher #define B44_RX_MCAST 0x0594UL /* MIB RX Multicast Packets */ 216adfc5217SJeff Kirsher #define B44_RX_64 0x0598UL /* MIB RX <= 64 byte Packets */ 217adfc5217SJeff Kirsher #define B44_RX_65_127 0x059CUL /* MIB RX 65 to 127 byte Packets */ 218adfc5217SJeff Kirsher #define B44_RX_128_255 0x05A0UL /* MIB RX 128 to 255 byte Packets */ 219adfc5217SJeff Kirsher #define B44_RX_256_511 0x05A4UL /* MIB RX 256 to 511 byte Packets */ 220adfc5217SJeff Kirsher #define B44_RX_512_1023 0x05A8UL /* MIB RX 512 to 1023 byte Packets */ 221adfc5217SJeff Kirsher #define B44_RX_1024_MAX 0x05ACUL /* MIB RX 1024 to max byte Packets */ 222adfc5217SJeff Kirsher #define B44_RX_JABBER 0x05B0UL /* MIB RX Jabber Packets */ 223adfc5217SJeff Kirsher #define B44_RX_OSIZE 0x05B4UL /* MIB RX Oversize Packets */ 224adfc5217SJeff Kirsher #define B44_RX_FRAG 0x05B8UL /* MIB RX Fragment Packets */ 225adfc5217SJeff Kirsher #define B44_RX_MISS 0x05BCUL /* MIB RX Missed Packets */ 226adfc5217SJeff Kirsher #define B44_RX_CRCA 0x05C0UL /* MIB RX CRC Align Errors */ 227adfc5217SJeff Kirsher #define B44_RX_USIZE 0x05C4UL /* MIB RX Undersize Packets */ 228adfc5217SJeff Kirsher #define B44_RX_CRC 0x05C8UL /* MIB RX CRC Errors */ 229adfc5217SJeff Kirsher #define B44_RX_ALIGN 0x05CCUL /* MIB RX Align Errors */ 230adfc5217SJeff Kirsher #define B44_RX_SYM 0x05D0UL /* MIB RX Symbol Errors */ 231adfc5217SJeff Kirsher #define B44_RX_PAUSE 0x05D4UL /* MIB RX Pause Packets */ 232adfc5217SJeff Kirsher #define B44_RX_NPAUSE 0x05D8UL /* MIB RX Non-Pause Packets */ 233adfc5217SJeff Kirsher 234adfc5217SJeff Kirsher /* 4400 PHY registers */ 235adfc5217SJeff Kirsher #define B44_MII_AUXCTRL 24 /* Auxiliary Control */ 236adfc5217SJeff Kirsher #define MII_AUXCTRL_DUPLEX 0x0001 /* Full Duplex */ 237adfc5217SJeff Kirsher #define MII_AUXCTRL_SPEED 0x0002 /* 1=100Mbps, 0=10Mbps */ 238adfc5217SJeff Kirsher #define MII_AUXCTRL_FORCED 0x0004 /* Forced 10/100 */ 239adfc5217SJeff Kirsher #define B44_MII_ALEDCTRL 26 /* Activity LED */ 240adfc5217SJeff Kirsher #define MII_ALEDCTRL_ALLMSK 0x7fff 241adfc5217SJeff Kirsher #define B44_MII_TLEDCTRL 27 /* Traffic Meter LED */ 242adfc5217SJeff Kirsher #define MII_TLEDCTRL_ENABLE 0x0040 243adfc5217SJeff Kirsher 244adfc5217SJeff Kirsher struct dma_desc { 245adfc5217SJeff Kirsher __le32 ctrl; 246adfc5217SJeff Kirsher __le32 addr; 247adfc5217SJeff Kirsher }; 248adfc5217SJeff Kirsher 249adfc5217SJeff Kirsher /* There are only 12 bits in the DMA engine for descriptor offsetting 250adfc5217SJeff Kirsher * so the table must be aligned on a boundary of this. 251adfc5217SJeff Kirsher */ 252adfc5217SJeff Kirsher #define DMA_TABLE_BYTES 4096 253adfc5217SJeff Kirsher 254adfc5217SJeff Kirsher #define DESC_CTRL_LEN 0x00001fff 255adfc5217SJeff Kirsher #define DESC_CTRL_CMASK 0x0ff00000 /* Core specific bits */ 256adfc5217SJeff Kirsher #define DESC_CTRL_EOT 0x10000000 /* End of Table */ 257adfc5217SJeff Kirsher #define DESC_CTRL_IOC 0x20000000 /* Interrupt On Completion */ 258adfc5217SJeff Kirsher #define DESC_CTRL_EOF 0x40000000 /* End of Frame */ 259adfc5217SJeff Kirsher #define DESC_CTRL_SOF 0x80000000 /* Start of Frame */ 260adfc5217SJeff Kirsher 261adfc5217SJeff Kirsher #define RX_COPY_THRESHOLD 256 262adfc5217SJeff Kirsher 263adfc5217SJeff Kirsher struct rx_header { 264adfc5217SJeff Kirsher __le16 len; 265adfc5217SJeff Kirsher __le16 flags; 266adfc5217SJeff Kirsher __le16 pad[12]; 267adfc5217SJeff Kirsher }; 268adfc5217SJeff Kirsher #define RX_HEADER_LEN 28 269adfc5217SJeff Kirsher 270adfc5217SJeff Kirsher #define RX_FLAG_OFIFO 0x00000001 /* FIFO Overflow */ 271adfc5217SJeff Kirsher #define RX_FLAG_CRCERR 0x00000002 /* CRC Error */ 272adfc5217SJeff Kirsher #define RX_FLAG_SERR 0x00000004 /* Receive Symbol Error */ 273adfc5217SJeff Kirsher #define RX_FLAG_ODD 0x00000008 /* Frame has odd number of nibbles */ 274adfc5217SJeff Kirsher #define RX_FLAG_LARGE 0x00000010 /* Frame is > RX MAX Length */ 275adfc5217SJeff Kirsher #define RX_FLAG_MCAST 0x00000020 /* Dest is Multicast Address */ 276adfc5217SJeff Kirsher #define RX_FLAG_BCAST 0x00000040 /* Dest is Broadcast Address */ 277adfc5217SJeff Kirsher #define RX_FLAG_MISS 0x00000080 /* Received due to promisc mode */ 278adfc5217SJeff Kirsher #define RX_FLAG_LAST 0x00000800 /* Last buffer in frame */ 279adfc5217SJeff Kirsher #define RX_FLAG_ERRORS (RX_FLAG_ODD | RX_FLAG_SERR | RX_FLAG_CRCERR | RX_FLAG_OFIFO) 280adfc5217SJeff Kirsher 281adfc5217SJeff Kirsher struct ring_info { 282adfc5217SJeff Kirsher struct sk_buff *skb; 283adfc5217SJeff Kirsher dma_addr_t mapping; 284adfc5217SJeff Kirsher }; 285adfc5217SJeff Kirsher 286adfc5217SJeff Kirsher #define B44_MCAST_TABLE_SIZE 32 2872729b427SFlorian Fainelli /* no local phy regs, e.g: Broadcom switches pseudo-PHY */ 2882729b427SFlorian Fainelli #define B44_PHY_ADDR_NO_LOCAL_PHY BRCM_PSEUDO_PHY_ADDR 2892729b427SFlorian Fainelli /* no phy present at all */ 2902729b427SFlorian Fainelli #define B44_PHY_ADDR_NO_PHY 31 291adfc5217SJeff Kirsher #define B44_MDC_RATIO 5000000 292adfc5217SJeff Kirsher 293adfc5217SJeff Kirsher #define B44_STAT_REG_DECLARE \ 294adfc5217SJeff Kirsher _B44(tx_good_octets) \ 295adfc5217SJeff Kirsher _B44(tx_good_pkts) \ 296adfc5217SJeff Kirsher _B44(tx_octets) \ 297adfc5217SJeff Kirsher _B44(tx_pkts) \ 298adfc5217SJeff Kirsher _B44(tx_broadcast_pkts) \ 299adfc5217SJeff Kirsher _B44(tx_multicast_pkts) \ 300adfc5217SJeff Kirsher _B44(tx_len_64) \ 301adfc5217SJeff Kirsher _B44(tx_len_65_to_127) \ 302adfc5217SJeff Kirsher _B44(tx_len_128_to_255) \ 303adfc5217SJeff Kirsher _B44(tx_len_256_to_511) \ 304adfc5217SJeff Kirsher _B44(tx_len_512_to_1023) \ 305adfc5217SJeff Kirsher _B44(tx_len_1024_to_max) \ 306adfc5217SJeff Kirsher _B44(tx_jabber_pkts) \ 307adfc5217SJeff Kirsher _B44(tx_oversize_pkts) \ 308adfc5217SJeff Kirsher _B44(tx_fragment_pkts) \ 309adfc5217SJeff Kirsher _B44(tx_underruns) \ 310adfc5217SJeff Kirsher _B44(tx_total_cols) \ 311adfc5217SJeff Kirsher _B44(tx_single_cols) \ 312adfc5217SJeff Kirsher _B44(tx_multiple_cols) \ 313adfc5217SJeff Kirsher _B44(tx_excessive_cols) \ 314adfc5217SJeff Kirsher _B44(tx_late_cols) \ 315adfc5217SJeff Kirsher _B44(tx_defered) \ 316adfc5217SJeff Kirsher _B44(tx_carrier_lost) \ 317adfc5217SJeff Kirsher _B44(tx_pause_pkts) \ 318adfc5217SJeff Kirsher _B44(rx_good_octets) \ 319adfc5217SJeff Kirsher _B44(rx_good_pkts) \ 320adfc5217SJeff Kirsher _B44(rx_octets) \ 321adfc5217SJeff Kirsher _B44(rx_pkts) \ 322adfc5217SJeff Kirsher _B44(rx_broadcast_pkts) \ 323adfc5217SJeff Kirsher _B44(rx_multicast_pkts) \ 324adfc5217SJeff Kirsher _B44(rx_len_64) \ 325adfc5217SJeff Kirsher _B44(rx_len_65_to_127) \ 326adfc5217SJeff Kirsher _B44(rx_len_128_to_255) \ 327adfc5217SJeff Kirsher _B44(rx_len_256_to_511) \ 328adfc5217SJeff Kirsher _B44(rx_len_512_to_1023) \ 329adfc5217SJeff Kirsher _B44(rx_len_1024_to_max) \ 330adfc5217SJeff Kirsher _B44(rx_jabber_pkts) \ 331adfc5217SJeff Kirsher _B44(rx_oversize_pkts) \ 332adfc5217SJeff Kirsher _B44(rx_fragment_pkts) \ 333adfc5217SJeff Kirsher _B44(rx_missed_pkts) \ 334adfc5217SJeff Kirsher _B44(rx_crc_align_errs) \ 335adfc5217SJeff Kirsher _B44(rx_undersize) \ 336adfc5217SJeff Kirsher _B44(rx_crc_errs) \ 337adfc5217SJeff Kirsher _B44(rx_align_errs) \ 338adfc5217SJeff Kirsher _B44(rx_symbol_errs) \ 339adfc5217SJeff Kirsher _B44(rx_pause_pkts) \ 340adfc5217SJeff Kirsher _B44(rx_nonpause_pkts) 341adfc5217SJeff Kirsher 342adfc5217SJeff Kirsher /* SW copy of device statistics, kept up to date by periodic timer 343adfc5217SJeff Kirsher * which probes HW values. Check b44_stats_update if you mess with 344adfc5217SJeff Kirsher * the layout 345adfc5217SJeff Kirsher */ 346adfc5217SJeff Kirsher struct b44_hw_stats { 347eeda8585SKevin Groeneveld #define _B44(x) u64 x; 348adfc5217SJeff Kirsher B44_STAT_REG_DECLARE 349adfc5217SJeff Kirsher #undef _B44 350eeda8585SKevin Groeneveld struct u64_stats_sync syncp; 351adfc5217SJeff Kirsher }; 352adfc5217SJeff Kirsher 353b04138b3SHauke Mehrtens #define B44_BOARDFLAG_ROBO 0x0010 /* Board has robo switch */ 354b04138b3SHauke Mehrtens #define B44_BOARDFLAG_ADM 0x0080 /* Board has ADMtek switch */ 355b04138b3SHauke Mehrtens 356adfc5217SJeff Kirsher struct ssb_device; 357adfc5217SJeff Kirsher 358adfc5217SJeff Kirsher struct b44 { 359adfc5217SJeff Kirsher spinlock_t lock; 360adfc5217SJeff Kirsher 361adfc5217SJeff Kirsher u32 imask, istat; 362adfc5217SJeff Kirsher 363adfc5217SJeff Kirsher struct dma_desc *rx_ring, *tx_ring; 364adfc5217SJeff Kirsher 365adfc5217SJeff Kirsher u32 tx_prod, tx_cons; 366adfc5217SJeff Kirsher u32 rx_prod, rx_cons; 367adfc5217SJeff Kirsher 368adfc5217SJeff Kirsher struct ring_info *rx_buffers; 369adfc5217SJeff Kirsher struct ring_info *tx_buffers; 370adfc5217SJeff Kirsher 371adfc5217SJeff Kirsher struct napi_struct napi; 372adfc5217SJeff Kirsher 373adfc5217SJeff Kirsher u32 dma_offset; 374adfc5217SJeff Kirsher u32 flags; 375adfc5217SJeff Kirsher #define B44_FLAG_B0_ANDLATER 0x00000001 376adfc5217SJeff Kirsher #define B44_FLAG_BUGGY_TXPTR 0x00000002 377adfc5217SJeff Kirsher #define B44_FLAG_REORDER_BUG 0x00000004 378adfc5217SJeff Kirsher #define B44_FLAG_PAUSE_AUTO 0x00008000 379adfc5217SJeff Kirsher #define B44_FLAG_FULL_DUPLEX 0x00010000 380adfc5217SJeff Kirsher #define B44_FLAG_100_BASE_T 0x00020000 381adfc5217SJeff Kirsher #define B44_FLAG_TX_PAUSE 0x00040000 382adfc5217SJeff Kirsher #define B44_FLAG_RX_PAUSE 0x00080000 383adfc5217SJeff Kirsher #define B44_FLAG_FORCE_LINK 0x00100000 384adfc5217SJeff Kirsher #define B44_FLAG_ADV_10HALF 0x01000000 385adfc5217SJeff Kirsher #define B44_FLAG_ADV_10FULL 0x02000000 386adfc5217SJeff Kirsher #define B44_FLAG_ADV_100HALF 0x04000000 387adfc5217SJeff Kirsher #define B44_FLAG_ADV_100FULL 0x08000000 388d6194195SHauke Mehrtens #define B44_FLAG_EXTERNAL_PHY 0x10000000 389adfc5217SJeff Kirsher #define B44_FLAG_RX_RING_HACK 0x20000000 390adfc5217SJeff Kirsher #define B44_FLAG_TX_RING_HACK 0x40000000 391adfc5217SJeff Kirsher #define B44_FLAG_WOL_ENABLE 0x80000000 392adfc5217SJeff Kirsher 393adfc5217SJeff Kirsher u32 msg_enable; 394adfc5217SJeff Kirsher 395adfc5217SJeff Kirsher struct timer_list timer; 396adfc5217SJeff Kirsher 397adfc5217SJeff Kirsher struct b44_hw_stats hw_stats; 398adfc5217SJeff Kirsher 399adfc5217SJeff Kirsher struct ssb_device *sdev; 400adfc5217SJeff Kirsher struct net_device *dev; 401adfc5217SJeff Kirsher 402adfc5217SJeff Kirsher dma_addr_t rx_ring_dma, tx_ring_dma; 403adfc5217SJeff Kirsher 404adfc5217SJeff Kirsher u32 rx_pending; 405adfc5217SJeff Kirsher u32 tx_pending; 406adfc5217SJeff Kirsher u8 phy_addr; 407adfc5217SJeff Kirsher u8 force_copybreak; 40886f4ea63SHauke Mehrtens struct mii_bus *mii_bus; 40986f4ea63SHauke Mehrtens int old_link; 410adfc5217SJeff Kirsher struct mii_if_info mii_if; 411adfc5217SJeff Kirsher }; 412adfc5217SJeff Kirsher 413adfc5217SJeff Kirsher #endif /* _B44_H */ 414