Lines Matching +full:tx +full:- +full:only
8 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
33 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
94 #define APMG_PS_CTRL_VAL_PWR_SRC_MAX (0x01000000) /* 3945 only */
106 * processor is sleeping (e.g. for periodic power-saving shutdowns of radio).
119 * The uCode used for open-source drivers includes two programs:
121 * 1) Initialization -- performs hardware calibration and sets up some
128 * 2) Runtime/Protocol -- performs all normal runtime operations. This
134 * 1) Load bootstrap program (instructions only, no data image for bootstrap)
170 * Data caching during power-downs:
173 * power-saving modes, or for RFKILL), uCode stores (via PCI busmaster DMA)
186 * uCode from where it left off before the power-down.
193 * RFKILL should use complete restarts (with total re-initialization) of uCode,
198 * for modified data! If you need to completely re-initialize the NIC, make
230 * BSM special memory, stays powered on during power-save sleeps.
231 * Read/write, address range from LOWER_BOUND to (LOWER_BOUND + SIZE -1)
236 /* 3945 Tx scheduler registers */
247 * Tx Scheduler
249 * The Tx Scheduler selects the next frame to be transmitted, choosing TFDs
250 * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in
251 * host DRAM. It steers each frame's Tx command (which contains the frame
252 * data) into one of up to 7 prioritized Tx DMA FIFO channels within the
253 * device. A queue maps to only one (selectable by driver) Tx DMA channel,
256 * Tx DMA FIFOs have dedicated purposes. For 4965, they are used as follows
259 * 0 -- EDCA BK (background) frames, lowest priority
260 * 1 -- EDCA BE (best effort) frames, normal priority
261 * 2 -- EDCA VI (video) frames, higher priority
262 * 3 -- EDCA VO (voice) and management frames, highest priority
263 * 4 -- Commands (e.g. RXON, etc.)
264 * 5 -- unused (HCCA)
265 * 6 -- unused (HCCA)
266 * 7 -- not used by driver (device-internal only)
269 * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6.
270 * In addition, driver can map the remaining queues to Tx DMA/FIFO
271 * channels 0-3 to support 11n aggregation via EDCA DMA channels.
275 * 1) Scheduler-Ack, in which the scheduler automatically supports a
276 * block-ack (BA) win of up to 64 TFDs. In this mode, each queue
279 * Quality-Of-Service (QOS) priority, destined for a single station.
281 * In scheduler-ack mode, the scheduler keeps track of the Tx status of
284 * automatically processes block-acks received from the receiving STA,
285 * and reschedules un-acked frames to be retransmitted (successful
286 * Tx completion may end up being out-of-order).
292 * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order.
293 * The device may automatically retry Tx, but will retry only one frame
318 * Max Tx win size is the max number of contiguous TFDs that the scheduler
319 * can keep track of at one time when creating block-ack chains of frames.
320 * Note that "64" matches the number of ack bits in a block-ack packet.
332 * Value is valid only after "Alive" response from uCode.
337 * Driver may need to update queue-empty bits after changing queue's
338 * write and read pointers (idxes) during (re-)initialization (i.e. when
341 * 31-16: Write mask -- 1: update empty bit, 0: don't change empty bit
342 * 15-00: Empty state, one for each queue -- 1: empty, 0: non-empty
349 * Each Tx queue has a BC CB in host DRAM to support Scheduler-ACK mode.
350 * This register points to BC CB for queue 0, must be on 1024-byte boundary.
355 * 25-00: Byte Count CB physical address [35:10], must be 1024-byte aligned.
360 * Enables any/all Tx DMA/FIFO channels.
361 * Scheduler generates requests for only the active channels.
364 * 7- 0: Enable (1), disable (0), one bit for each channel 0-7
368 * Queue (x) Write Pointers (idxes, really!), one for each Tx queue.
377 * Queue (x) Read Pointers (idxes, really!), one for each Tx queue.
379 * For Scheduler-ACK mode, idx indicates first frame in Tx win.
388 * 31-16: Reserved
389 * 15-00: Mode, one bit for each queue -- 1: Chain mode, 0: one-at-a-time
391 * Scheduler-ACK mode as well, via SCD_QUEUE_STATUS_BITS(x).
399 * 31-16: Reserved
400 * 15-00: Interrupt enable, one bit for each queue -- 1: enabled, 0: disabled
401 * NOTE: This functionality is apparently a no-op; driver relies on interrupts
402 * from Rx queue to read Tx command responses and update Tx queues.
408 * Sets up queue mode and assigns queue to Tx DMA channel.
410 * 19-10: Write mask/enable bits for bits 0-9
412 * 8: Scheduler-ACK mode (1), non-Scheduler-ACK (i.e. FIFO) mode (0).
414 * 7-6: Driver should init to "0"
417 * this bit to "1" for aggregation mode, or "0" for non-agg.
418 * 4-1: Tx FIFO to use (range 0-7).
422 * NOTE: If enabling Scheduler-ACK mode, chain mode should also be enabled
455 * Queue context. One 8-byte entry for each of 16 queues.
462 * 0-06: Max Tx win size for Scheduler-ACK. Driver should init to 64.
465 * 16-22: Frame limit. Driver should init to 10 (0xa).
482 * Tx Status Bitmap
485 * "Alive" notification from uCode. Area is used only by device itself;
493 * When queue is in Scheduler-ACK mode, frames placed in a that queue must be
494 * for only one combination of receiver address (RA) and traffic ID (TID), i.e.
496 * not final destination). The SCD_TRANSLATE_TBL area provides 16 16-bit
497 * mappings, one for each of the 16 queues. If queue is not in Scheduler-ACK
500 * Bit fields, for each 16-bit map:
501 * 15-9: Reserved, set to 0
502 * 8-4: Index into device's station table for recipient station
503 * 3-0: Traffic ID (tid), range 0-15
506 * "Alive" notification from uCode. To update a 16-bit map value, driver
507 * must read a dword-aligned value from device SRAM, replace the 16-bit map
520 /*********************** END TX SCHEDULER *************************************/