Lines Matching +full:tx +full:- +full:only
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * hd64572.h Description of the Hitachi HD64572 (SCA-II), valid for
8 * Copyright: (c) 2000-2001 Cyclades Corp.
15 * PC300 initial CVS version (3.4.0-pre1)
48 #define DTX_REG(reg, chan) (reg + 0x20*(2*chan + 1)) /* DMA Tx */
50 #define TTX_REG(reg, chan) (reg + 0x10*(2*chan + 1)) /* Timer Tx */
53 #define IR0_DTX(val, chan) ((val)<<(4*(2*chan + 1))) /* Int DMA Tx */
66 #define TXS 0x13d /* TX clock source */
68 #define TMCT 0x144 /* Time constant (Tx) */
85 #define TRBL 0x100 /* TX/RX buffer reg L */
86 #define TRBK 0x101 /* TX/RX buffer reg K */
87 #define TRBJ 0x102 /* TX/RX buffer reg J */
88 #define TRBH 0x103 /* TX/RX buffer reg H */
89 #define TRC0 0x148 /* TX Ready control reg 0 */
90 #define TRC1 0x149 /* TX Ready control reg 1 */
97 #define TFS 0x14b /* Tx Start Threshold Ctl Reg */
98 #define TFN 0x143 /* Inter-transmit-frame Time Fill Ctl Reg */
99 #define TBN 0x110 /* Tx Buffer Number Reg */
101 #define TNR0 0x150 /* Tx DMA Request Ctl Reg 0 */
102 #define TNR1 0x151 /* Tx DMA Request Ctl Reg 1 */
103 #define TCR 0x152 /* Tx DMA Critical Request Reg */
124 #define BTCR 0x08 /* Burst Tx Ctl Reg */
125 #define BOLR 0x0c /* Back-off Length Reg */
127 #define DSR_TX(chan) (0x49 + 2*chan) /* DMA Status Reg (Tx) */
129 #define DIR_TX(chan) (0x4d + 2*chan) /* DMA Interrupt Enable Reg (Tx) */
131 #define FCT_TX(chan) (0x51 + 2*chan) /* Frame End Interrupt Counter (Tx) */
133 #define DMR_TX(chan) (0x55 + 2*chan) /* DMA Mode Reg (Tx) */
135 #define DCR_TX(chan) (0x59 + 2*chan) /* DMA Command Reg (Tx) */
143 #define DARL 0x80 /* Dest Addr Register L (single-block, RX only) */
144 #define DARH 0x81 /* Dest Addr Register H (single-block, RX only) */
145 #define DARB 0x82 /* Dest Addr Register B (single-block, RX only) */
146 #define DARBH 0x83 /* Dest Addr Register BH (single-block, RX only) */
147 #define SARL 0x80 /* Source Addr Register L (single-block, TX only) */
148 #define SARH 0x81 /* Source Addr Register H (single-block, TX only) */
149 #define SARB 0x82 /* Source Addr Register B (single-block, TX only) */
150 #define DARBH 0x83 /* Source Addr Register BH (single-block, TX only) */
151 #define BARL 0x80 /* Buffer Addr Register L (chained-block) */
152 #define BARH 0x81 /* Buffer Addr Register H (chained-block) */
153 #define BARB 0x82 /* Buffer Addr Register B (chained-block) */
154 #define BARBH 0x83 /* Buffer Addr Register BH (chained-block) */
163 #define BFLL 0x90 /* RX Buffer Length L (only RX) */
164 #define BFLH 0x91 /* RX Buffer Length H (only RX) */
183 u8 unused; /* pads to 4-byte boundary */
193 6 - Short Frame
194 5 - Abort
195 4 - Residual bit
197 2 - CRC
199 0 EOT -
230 #define TECNTL 0x160 /* Tx EOM Counter L */
231 #define TECNTM 0x161 /* Tx EOM Counter M */
232 #define TECNTH 0x162 /* Tx EOM Counter H */
233 #define TECCR 0x163 /* Tx EOM Counter Ctl Reg */
284 #define MD0_HDLC 0x80 /* Bit-sync HDLC mode */
362 #define CLK_TX_RXCLK 0x60 /* TX clock from RX clock */
440 #define IE0_UDRN 0x00008000 /* TX underrun MSCI interrupt enable */