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/linux/drivers/pci/controller/dwc/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
3 menu "DesignWare-based PCIe controllers"
39 required only for DT-based platforms. ACPI platforms with the
50 DesignWare IP and therefore the driver re-uses the DesignWare
61 and therefore the driver re-uses the DesignWare core functions to
68 bool "Axis ARTPEC-6 PCIe controller (host mode)"
74 Enables support for the PCIe controller in the ARTPEC-6 SoC to work in
78 bool "Axis ARTPEC-6 PCIe controller (endpoint mode)"
84 Enables support for the PCIe controller in the ARTPEC-6 SoC to work in
88 tristate "Baikal-T1 PCIe controller"
[all …]
/linux/arch/arm/mach-omap2/
H A Dcm.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2007-2009, 2012 Texas Instruments, Inc.
6 * Copyright (C) 2007-2009 Nokia Corporation
25 #include "prcm-common.h"
45 * struct cm_ll_data - fn ptrs to per-SoC CM function implementations
46 * @split_idlest_reg: ptr to the SoC CM-specific split_idlest_reg impl
47 * @wait_module_ready: ptr to the SoC CM-specific wait_module_ready impl
48 * @wait_module_idle: ptr to the SoC CM-specific wait_module_idle impl
49 * @module_enable: ptr to the SoC CM-specific module_enable impl
50 * @module_disable: ptr to the SoC CM-specific module_disable impl
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmarvell,mvebu-pinctrl.txt1 * Marvell SoC pinctrl core driver for mpp
3 The pinctrl driver enables Marvell SoCs to configure the multi-purpose pins
4 (mpp) to a specific function. For each SoC family there is a SoC specific
7 Please refer to pinctrl-bindings.txt in this directory for details of the
11 A Marvell SoC pin configuration node is a node of a group of pins which can
12 be used for a specific device or function. Each node requires one or more
16 - compatible: "marvell,<soc>-pinctrl"
17 Please refer to each marvell,<soc>-pinctrl.txt binding doc for supported SoCs.
20 - marvell,pins: string array of mpp pins or group of pins to be muxed.
21 - marvell,function: string representing a function to mux to for all
[all …]
H A Dfsl,imx-pinctrl.txt10 Please refer to pinctrl-bindings.txt in this directory for details of the
15 used for a specific device or function. This node represents both mux and config
18 such as pull-up, open drain, drive strength, etc.
21 - compatible: "fsl,<soc>-iomuxc"
22 Please refer to each fsl,<soc>-pinctrl.txt binding doc for supported SoCs.
25 - fsl,pins: each entry consists of 6 integers and represents the mux and config
28 imx*-pinfunc.h under device tree source folder. The last integer CONFIG is
29 the pad setting value like pull-up on this pin. And that's why fsl,pins entry
41 Please refer to each fsl,<soc>-pinctrl,txt binding doc for SoC specific part
45 Some requirements for using fsl,imx-pinctrl binding:
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/linux/Documentation/devicetree/bindings/mmc/
H A Dbluefield-dw-mshc.txt1 * Mellanox Bluefield SoC specific extensions to the Synopsys Designware
4 Read synopsys-dw-mshc.txt for more details
7 a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
9 by synopsys-dw-mshc.txt and the properties used by the Mellanox Bluefield SoC
10 specific extensions to the Synopsys Designware Mobile Storage Host Controller.
15 - "mellanox,bluefield-dw-mshc": for controllers with Mellanox Bluefield SoC
16 specific extensions.
20 /* Mellanox Bluefield SoC MMC */
22 compatible = "mellanox,bluefield-dw-mshc";
25 fifo-depth = <0x100>;
[all …]
H A Dk3-dw-mshc.txt1 * Hisilicon specific extensions to the Synopsys Designware Mobile
4 Read synopsys-dw-mshc.txt for more details
7 a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
9 by synopsys-dw-mshc.txt and the properties used by the Hisilicon specific
15 - "hisilicon,hi3660-dw-mshc": for controllers with hi3660 specific extensions.
16 - "hisilicon,hi3670-dw-mshc", "hisilicon,hi3660-dw-mshc": for controllers
17 with hi3670 specific extensions.
18 - "hisilicon,hi4511-dw-mshc": for controllers with hi4511 specific extensions.
19 - "hisilicon,hi6220-dw-mshc": for controllers with hi6220 specific extensions.
22 - hisilicon,peripheral-syscon: phandle of syscon used to control peripheral.
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/linux/drivers/pinctrl/nomadik/
H A Dpinctrl-abx500.h1 /* SPDX-License-Identifier: GPL-2.0 */
34 * struct abx500_function - ABx500 pinctrl mux function
46 * struct abx500_pingroup - describes a ABx500 pin group
47 * @name: the name of this specific pin group
49 * from the driver-local pin enumeration space
73 #define UNUSED -1
85 * function between the ABx500 SOC family when using
109 * struct abx500_gpio_irq_cluster - indicates GPIOs which are interrupt
116 * read-in values into the cluster information table
126 * struct abx500_pinrange - map pin numbers to GPIO offsets
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/linux/drivers/mmc/host/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
94 implements a hardware byte swapper using a 32-bit datum.
106 support UHS2-capable devices.
133 disabled, it will steal the MMC cards away - rendering them
145 identified by ACPI Compatibility ID PNP0D40 or specific
171 (SDHCI). This hardware is found e.g. in Xilinx' Zynq SoC.
254 tristate "SDHCI OF support for the SpacemiT K1 SoC"
261 found in the SpacemiT K1 SoC.
268 tristate "SDHCI OF support for the MCHP Sparx5 SoC"
273 found in the MCHP Sparx5 SoC.
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/linux/Documentation/devicetree/bindings/sifive/
H A Dsifive-blocks-ip-versioning.txt1 DT compatible string versioning for SiFive open-source IP blocks
4 strings for open-source SiFive IP blocks. HDL for these IP blocks
7 https://github.com/sifive/sifive-blocks
9 IP block-specific DT compatible strings are contained within the HDL,
10 in the form "sifive,<ip-block-name><integer version number>".
14 https://github.com/sifive/sifive-blocks/blob/v1.0/src/main/scala/devices/uart/UART.scala#L43
17 auto-discovery, the maintainers of these IP blocks intend to increment
25 upstream sifive-blocks commits. It is expected that most drivers will
26 match on these IP block-specific compatible strings.
28 DT data authors, when writing data for a particular SoC, should
[all …]
/linux/drivers/ufs/host/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0+
5 # Copyright (C) 2011-2013 Samsung India Software Operations
45 This selects the Cadence-specific additions to UFSHCD platform driver.
58 tristate "QCOM specific hooks to UFS controller platform driver"
64 This selects the QCOM specific additions to UFSHCD platform driver.
65 UFS host on QCOM needs some vendor specific configuration before
67 specific registers.
73 tristate "Mediatek specific hooks to UFS controller platform driver"
79 This selects the Mediatek specific additions to UFSHCD platform driver.
80 UFS host on Mediatek needs some vendor specific configuration before
[all …]
/linux/Documentation/arch/arm/spear/
H A Doverview.rst6 ------------
11 The ST Microelectronics SPEAr range of ARM9/CortexA9 System-on-Chip CPUs are
19 - SPEAr3XX (3XX SOC series, based on ARM9)
20 - SPEAr300 (SOC)
21 - SPEAr300 Evaluation Board
22 - SPEAr310 (SOC)
23 - SPEAr310 Evaluation Board
24 - SPEAr320 (SOC)
25 - SPEAr320 Evaluation Board
26 - SPEAr6XX (6XX SOC series, based on ARM9)
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/linux/Documentation/sound/soc/
H A Doverview.rst2 ALSA SoC Layer Overview
6 provide better ALSA support for embedded system-on-chip processors (e.g.
8 subsystem there was some support in the kernel for SoC audio, however it
9 had some limitations:-
11 * Codec drivers were often tightly coupled to the underlying SoC
12 CPU. This is not ideal and leads to code duplication - for example,
13 Linux had different wm8731 drivers for 4 different SoC platforms.
18 machine specific code to re-route audio, enable amps, etc., after such an
31 features :-
36 * Easy I2S/PCM audio interface setup between codec and SoC. Each SoC
[all …]
H A Dusb.rst12 an implementation that allows for an alternate power-optimized path in the audio
32 | |SoC-USB | |
34 |USB SND |<--->|USBSND |<------------>|________| |
35 |(card.c)| |offld |<---------- |
43 | | | |->|audio DSP |
45 |XHCI HCD |<- |
49 SoC USB driver
52 ----------
55 - ``list``: list head for SND SoC struct list
56 - ``component``: reference to ASoC component
[all …]
/linux/drivers/pinctrl/mvebu/
H A Dpinctrl-mvebu.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 * struct mvebu_mpp_ctrl_data - private data for the mpp ctrl operations
29 * struct mvebu_mpp_ctrl - describe a mpp control
39 * internal function, inside the SoC. Each muxable unit can be switched
44 * specific mode. The optional mpp_gpio_req/_dir functions can be used
62 * struct mvebu_mpp_ctrl_setting - describe a mpp ctrl setting
64 * @name: ctrl setting name, e.g. uart2, spi0 - unique per mpp_mode
69 * A ctrl_setting describes a specific internal mux function that a mpp pin
71 * register for common mpp pin configuration registers on MVEBU. SoC specific
[all …]
/linux/drivers/pinctrl/mediatek/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
142 on Airoha EN7581 SoC.
166 on MediaTek MT6779 SoC.
168 map specific eint which doesn't have real gpio pin.
192 on the MediaTek Dimensity 1200 MT6893 Smartphone SoC.
258 on MediaTek MT8188 SoC.
260 map specific eint which doesn't have real gpio pin.
270 on MediaTek MT8189 SoC.
272 map specific eint which doesn't have real gpio pin.
296 on MediaTek MT8196 SoC.
[all …]
/linux/arch/mips/lantiq/
H A Dprom.c1 // SPDX-License-Identifier: GPL-2.0-only
26 * this struct is filled by the soc specific detection code and holds
27 * information about the specific soc type, revision and name
102 /* call the soc specific detetcion code and get it to fill soc_info */ in prom_init()
104 snprintf(soc_info.sys_type, LTQ_SYS_TYPE_LEN - 1, "%s rev %s", in prom_init()
106 soc_info.sys_type[LTQ_SYS_TYPE_LEN - 1] = '\0'; in prom_init()
107 pr_info("SoC: %s\n", soc_info.sys_type); in prom_init()
/linux/sound/soc/qcom/
H A Dlpass.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2010-2011,2013-2015,2020 The Linux Foundation. All rights reserved.
5 * lpass.h - Definitions for the QTi LPASS
15 #include <dt-bindings/sound/qcom,lpass.h>
16 #include <dt-bindings/sound/qcom,q6afe.h>
17 #include "lpass-hdmi.h"
39 return -EINVAL; \
97 /* AHB-I/X bus clocks inside the low-power audio subsystem (LPASS) */
121 /* low-power audio interface (LPAIF) registers */
130 /* regmap backed by the low-power audio interface (LPAIF) registers */
[all …]
/linux/drivers/soc/ti/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
4 # TI SOC drivers
7 bool "TI SOC drivers support"
18 Packets are queued/de-queued by writing/reading descriptor address
40 c-states on AM335x. Also required for rtc and ddr in self-refresh low
44 tristate "TI AMx3 Wkup-M3 IPC Driver"
70 Include support for the SoC bus socinfo for the TI K3 Multicore SoC
71 platforms to provide information about the SoC family and
75 tristate "TI PRU-ICSS Subsystem Platform drivers"
79 TI PRU-ICSS Subsystem platform specific support.
[all …]
/linux/drivers/soc/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 menu "SOC (System On Chip) specific Drivers"
4 source "drivers/soc/amlogic/Kconfig"
5 source "drivers/soc/apple/Kconfig"
6 source "drivers/soc/aspeed/Kconfig"
7 source "drivers/soc/atmel/Kconfig"
8 source "drivers/soc/bcm/Kconfig"
9 source "drivers/soc/canaan/Kconfig"
10 source "drivers/soc/cirrus/Kconfig"
11 source "drivers/soc/fsl/Kconfig"
[all …]
/linux/Documentation/devicetree/bindings/input/
H A Dbrcm,bcm-keypad.txt3 Broadcom Keypad controller is used to interface a SoC with a matrix-type
6 The keypad controller can sense a key-press and key-release and report the
9 This binding is based on the matrix-keymap binding with the following
12 keypad,num-rows and keypad,num-columns are required.
14 Required SoC Specific Properties:
15 - compatible: should be "brcm,bcm-keypad"
17 - reg: physical base address of the controller and length of memory mapped
20 - interrupts: The interrupt number to the cpu.
22 Board Specific Properties:
23 - keypad,num-rows: Number of row lines connected to the keypad
[all …]
/linux/Documentation/devicetree/bindings/mtd/
H A Dbrcm,brcmnand.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Brian Norris <computersforpeace@gmail.com>
11 - Kamal Dasu <kdasu.kdev@gmail.com>
12 - William Zhang <william.zhang@broadcom.com>
15 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
16 flash chips. It has a memory-mapped register interface for both control
23 Broadband SoC (BCM63xx), ARM based Broadband SoC (BCMBCA) and iProc/Cygnus.
27 -- Additional SoC-specific NAND controller properties --
[all …]
/linux/drivers/soc/samsung/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
3 # Samsung SoC drivers
6 bool "Samsung SoC driver support" if COMPILE_TEST
12 bool "Exynos ASV ARMv7-specific driver extensions" if COMPILE_TEST
23 Support for Samsung Exynos SoC ChipID and Adaptive Supply Voltage.
33 IP-core found in modern Samsung Exynos SoCs, like Exynos850 and
49 bool "Exynos PMU ARMv7-specific driver extensions" if COMPILE_TEST
76 bool "Exynos SoC Regulator Coupler" if COMPILE_TEST
/linux/Documentation/driver-api/phy/
H A Dsamsung-usb2.rst6 --------------
18 --------------------
20 - phy-samsung-usb2.c
25 of the PHY module. Depending on which SoC was chosen they execute SoC
26 specific callbacks. The specific SoC version is selected by choosing
30 - phy-samsung-usb2.h
36 ------------------
38 To support a new SoC a new file should be added to the drivers/phy
39 directory. Each SoC's configuration is stored in an instance of the
51 property is a boolean flag that determines whether the SoC has USB host
[all …]
/linux/drivers/pinctrl/intel/
H A Dpinctrl-intel.h1 /* SPDX-License-Identifier: GPL-2.0 */
26 * struct intel_pingroup - Description about group of pins
38 * struct intel_function - Description about a function
48 * struct intel_padgroup - Hardware pad group information
67 * enum - Special treatment for GPIO base in pad group
74 INTEL_GPIO_BASE_ZERO = -2,
75 INTEL_GPIO_BASE_NOMAP = -1,
80 * struct intel_community - Intel pin community description
100 * @pad_map: Optional non-linear mapping of the pads
103 * @regs: Community specific common registers (reserved for core driver)
[all …]
/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Ddcsr.txt21 - compatible
24 Definition: Must include "fsl,dcsr" and "simple-bus".
25 The DCSR space exists in the memory-mapped bus.
27 - #address-cells
33 - #size-cells
40 - ranges
42 Value type: <prop-encoded-array>
48 #address-cells = <1>;
49 #size-cells = <1>;
50 compatible = "fsl,dcsr", "simple-bus";
[all …]

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