| /linux/drivers/gpu/drm/rockchip/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
16 Choose this option if you have a Rockchip soc chipset.
20 IP found on the SoC.
38 bool "Rockchip specific extensions for Analogix DP driver"
43 This selects support for Rockchip SoC specific extensions
45 on RK3288 or RK3399 based SoC, you should select this option.
53 This selects support for Rockchip SoC specific extensions
55 RK3399 based SoC, you should select this
59 bool "Rockchip specific extensions for Synopsys DW HDMI"
61 This selects support for Rockchip SoC specific extensions
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| /linux/drivers/net/ethernet/stmicro/stmmac/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "STMicroelectronics Multi-Gigabit Ethernet driver"
34 This selects the platform specific bus support for the stmmac driver.
45 tristate "Support for snps,dwc-qos-ethernet.txt DT binding."
50 Support for chips using the snps,dwc-qos-ethernet.txt DT binding.
57 platform specific code to function or is using platform
67 This selects the Anarion SoC glue layer support for the stmmac driver.
89 This selects the IPQ806x SoC glue layer support for the stmmac
91 acceleration features available on this SoC. Network devices
92 will behave like standard non-accelerated ethernet interfaces.
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| /linux/Documentation/process/ |
| H A D | maintainer-soc.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 SoC Subsystem
8 --------
10 The SoC subsystem is a place of aggregation for SoC-specific code.
13 * devicetrees for 32- & 64-bit ARM and RISC-V
14 * 32-bit ARM board files (arch/arm/mach*)
15 * 32- & 64-bit ARM defconfigs
16 * SoC-specific drivers across architectures, in particular for 32- & 64-bit
17 ARM, RISC-V and Loongarch
19 These "SoC-specific drivers" do not include clock, GPIO etc drivers that have
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| /linux/arch/arm/mach-omap2/ |
| H A D | cm.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2007-2009, 2012 Texas Instruments, Inc.
6 * Copyright (C) 2007-2009 Nokia Corporation
25 #include "prcm-common.h"
45 * struct cm_ll_data - fn ptrs to per-SoC CM function implementations
46 * @split_idlest_reg: ptr to the SoC CM-specific split_idlest_reg impl
47 * @wait_module_ready: ptr to the SoC CM-specific wait_module_ready impl
48 * @wait_module_idle: ptr to the SoC CM-specific wait_module_idle impl
49 * @module_enable: ptr to the SoC CM-specific module_enable impl
50 * @module_disable: ptr to the SoC CM-specific module_disable impl
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| /linux/drivers/thermal/samsung/ |
| H A D | exynos_tmu.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * exynos_tmu.c - Samsung Exynos TMU (Thermal Management Unit)
25 #include <dt-bindings/thermal/thermal_exynos.h>
43 /* Exynos3250 specific registers */
46 /* Exynos4210 specific registers */
50 /* Exynos5250, Exynos4412, Exynos3250 specific registers */
73 /* Exynos5260 specific */
79 /* Exynos4412 specific */
83 /* Exynos5433 specific registers */
106 /* Exynos7 specific registers */
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| /linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | marvell,mvebu-pinctrl.txt | 1 * Marvell SoC pinctrl core driver for mpp
3 The pinctrl driver enables Marvell SoCs to configure the multi-purpose pins
4 (mpp) to a specific function. For each SoC family there is a SoC specific
7 Please refer to pinctrl-bindings.txt in this directory for details of the
11 A Marvell SoC pin configuration node is a node of a group of pins which can
12 be used for a specific device or function. Each node requires one or more
16 - compatible: "marvell,<soc>-pinctrl"
17 Please refer to each marvell,<soc>-pinctrl.txt binding doc for supported SoCs.
20 - marvell,pins: string array of mpp pins or group of pins to be muxed.
21 - marvell,function: string representing a function to mux to for all
[all …]
|
| H A D | fsl,imx-pinctrl.txt | 10 Please refer to pinctrl-bindings.txt in this directory for details of the
15 used for a specific device or function. This node represents both mux and config
18 such as pull-up, open drain, drive strength, etc.
21 - compatible: "fsl,<soc>-iomuxc"
22 Please refer to each fsl,<soc>-pinctrl.txt binding doc for supported SoCs.
25 - fsl,pins: each entry consists of 6 integers and represents the mux and config
28 imx*-pinfunc.h under device tree source folder. The last integer CONFIG is
29 the pad setting value like pull-up on this pin. And that's why fsl,pins entry
41 Please refer to each fsl,<soc>-pinctrl,txt binding doc for SoC specific part
45 Some requirements for using fsl,imx-pinctrl binding:
[all …]
|
| /linux/Documentation/devicetree/bindings/mmc/ |
| H A D | bluefield-dw-mshc.txt | 1 * Mellanox Bluefield SoC specific extensions to the Synopsys Designware
4 Read synopsys-dw-mshc.txt for more details
7 a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
9 by synopsys-dw-mshc.txt and the properties used by the Mellanox Bluefield SoC
10 specific extensions to the Synopsys Designware Mobile Storage Host Controller.
15 - "mellanox,bluefield-dw-mshc": for controllers with Mellanox Bluefield SoC
16 specific extensions.
20 /* Mellanox Bluefield SoC MMC */
22 compatible = "mellanox,bluefield-dw-mshc";
25 fifo-depth = <0x100>;
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|
| /linux/drivers/pinctrl/nomadik/ |
| H A D | pinctrl-abx500.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
34 * struct abx500_function - ABx500 pinctrl mux function
46 * struct abx500_pingroup - describes a ABx500 pin group
47 * @name: the name of this specific pin group
49 * from the driver-local pin enumeration space
73 #define UNUSED -1
85 * function between the ABx500 SOC family when using
109 * struct abx500_gpio_irq_cluster - indicates GPIOs which are interrupt
116 * read-in values into the cluster information table
126 * struct abx500_pinrange - map pin numbers to GPIO offsets
[all …]
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| /linux/drivers/ufs/host/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0+
5 # Copyright (C) 2011-2013 Samsung India Software Operations
45 This selects the Cadence-specific additions to UFSHCD platform driver.
58 tristate "QCOM specific hooks to UFS controller platform driver"
64 This selects the QCOM specific additions to UFSHCD platform driver.
65 UFS host on QCOM needs some vendor specific configuration before
67 specific registers.
73 tristate "Mediatek specific hooks to UFS controller platform driver"
79 This selects the Mediatek specific additions to UFSHCD platform driver.
80 UFS host on Mediatek needs some vendor specific configuration before
[all …]
|
| /linux/Documentation/devicetree/bindings/sifive/ |
| H A D | sifive-blocks-ip-versioning.txt | 1 DT compatible string versioning for SiFive open-source IP blocks
4 strings for open-source SiFive IP blocks. HDL for these IP blocks
7 https://github.com/sifive/sifive-blocks
9 IP block-specific DT compatible strings are contained within the HDL,
10 in the form "sifive,<ip-block-name><integer version number>".
14 https://github.com/sifive/sifive-blocks/blob/v1.0/src/main/scala/devices/uart/UART.scala#L43
17 auto-discovery, the maintainers of these IP blocks intend to increment
25 upstream sifive-blocks commits. It is expected that most drivers will
26 match on these IP block-specific compatible strings.
28 DT data authors, when writing data for a particular SoC, should
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|
| /linux/Documentation/devicetree/ |
| H A D | usage-model.rst | 1 .. SPDX-License-Identifier: GPL-2.0
44 ----------
56 In 2005, when PowerPC Linux began a major cleanup and to merge 32-bit
57 and 64-bit support, the decision was made to require DT support on all
61 blob without requiring a real Open Firmware implementation. U-Boot,
66 existing non-DT aware firmware.
74 -------------
79 -------------------
88 per-machine hard coded selections.
101 ---------------------------
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| /linux/Documentation/devicetree/bindings/powerpc/fsl/ |
| H A D | mpic.txt | 14 - compatible
22 - reg
24 Value type: <prop-encoded-array>
29 - interrupt-controller
35 - #interrupt-cells
39 specifiers do not contain the interrupt-type or type-specific
42 - #address-cells
47 - pic-no-reset
53 configuration registers to a sane state-- masked or
60 - big-endian
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|
| /linux/Documentation/arch/arm/spear/ |
| H A D | overview.rst | 6 ------------
11 The ST Microelectronics SPEAr range of ARM9/CortexA9 System-on-Chip CPUs are
19 - SPEAr3XX (3XX SOC series, based on ARM9)
20 - SPEAr300 (SOC)
21 - SPEAr300 Evaluation Board
22 - SPEAr310 (SOC)
23 - SPEAr310 Evaluation Board
24 - SPEAr320 (SOC)
25 - SPEAr320 Evaluation Board
26 - SPEAr6XX (6XX SOC series, based on ARM9)
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|
| /linux/Documentation/sound/soc/ |
| H A D | overview.rst | 2 ALSA SoC Layer Overview
6 provide better ALSA support for embedded system-on-chip processors (e.g.
8 subsystem there was some support in the kernel for SoC audio, however it
9 had some limitations:-
11 * Codec drivers were often tightly coupled to the underlying SoC
12 CPU. This is not ideal and leads to code duplication - for example,
13 Linux had different wm8731 drivers for 4 different SoC platforms.
18 machine specific code to re-route audio, enable amps, etc., after such an
31 features :-
36 * Easy I2S/PCM audio interface setup between codec and SoC. Each SoC
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|
| /linux/drivers/pinctrl/mvebu/ |
| H A D | pinctrl-mvebu.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 * struct mvebu_mpp_ctrl_data - private data for the mpp ctrl operations
29 * struct mvebu_mpp_ctrl - describe a mpp control
39 * internal function, inside the SoC. Each muxable unit can be switched
44 * specific mode. The optional mpp_gpio_req/_dir functions can be used
62 * struct mvebu_mpp_ctrl_setting - describe a mpp ctrl setting
64 * @name: ctrl setting name, e.g. uart2, spi0 - unique per mpp_mode
69 * A ctrl_setting describes a specific internal mux function that a mpp pin
71 * register for common mpp pin configuration registers on MVEBU. SoC specific
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|
| /linux/Documentation/devicetree/bindings/arm/marvell/ |
| H A D | marvell,orion5x.txt | 1 Marvell Orion SoC Family Device Tree Bindings
2 ---------------------------------------------
4 Boards with a SoC of the Marvell Orion family, eg 88f5181
9 In addition, the above compatible shall be extended with the specific
10 SoC. Currently known SoC compatibles are:
12 "marvell,orion5x-88f5181"
13 "marvell,orion5x-88f5182"
15 And in addition, the compatible shall be extended with the specific
21 "lacie,ethernet-disk-mini-v2"
22 "lacie,d2-network"
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|
| /linux/Documentation/devicetree/bindings/rtc/ |
| H A D | isil,isl12057.txt | 8 ("wakeup-source") to handle the specific use-case found
9 on at least three in-tree users of the chip (NETGEAR ReadyNAS 102, 104
10 and 2120 ARM-based NAS); On those devices, the IRQ#2 pin of the chip
12 to the SoC but to a PMIC. It allows the device to be powered up when
14 get access to the 'wakealarm' sysfs entry, this specific property can
15 be set when the IRQ#2 pin of the chip is not connected to the SoC but
20 - "compatible": must be "isil,isl12057"
21 - "reg": I2C bus address of the device
25 - "wakeup-source": mark the chip as a wakeup source, independently of
26 the availability of an IRQ line connected to the SoC.
[all …]
|
| /linux/arch/mips/lantiq/ |
| H A D | prom.c | 1 // SPDX-License-Identifier: GPL-2.0-only
26 * this struct is filled by the soc specific detection code and holds
27 * information about the specific soc type, revision and name
102 /* call the soc specific detetcion code and get it to fill soc_info */ in prom_init()
104 snprintf(soc_info.sys_type, LTQ_SYS_TYPE_LEN - 1, "%s rev %s", in prom_init()
106 soc_info.sys_type[LTQ_SYS_TYPE_LEN - 1] = '\0'; in prom_init()
107 pr_info("SoC: %s\n", soc_info.sys_type); in prom_init()
|
| /linux/sound/soc/qcom/ |
| H A D | lpass.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2010-2011,2013-2015,2020 The Linux Foundation. All rights reserved.
5 * lpass.h - Definitions for the QTi LPASS
15 #include <dt-bindings/sound/qcom,lpass.h>
16 #include "lpass-hdmi.h"
38 return -EINVAL; \
96 /* AHB-I/X bus clocks inside the low-power audio subsystem (LPASS) */
120 /* low-power audio interface (LPAIF) registers */
129 /* regmap backed by the low-power audio interface (LPAIF) registers */
135 /* interrupts from the low-power audio interface (LPAIF) */
[all …]
|
| /linux/drivers/soc/ti/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
4 # TI SOC drivers
7 bool "TI SOC drivers support"
18 Packets are queued/de-queued by writing/reading descriptor address
40 c-states on AM335x. Also required for rtc and ddr in self-refresh low
44 tristate "TI AMx3 Wkup-M3 IPC Driver"
70 Include support for the SoC bus socinfo for the TI K3 Multicore SoC
71 platforms to provide information about the SoC family and
75 tristate "TI PRU-ICSS Subsystem Platform drivers"
79 TI PRU-ICSS Subsystem platform specific support.
[all …]
|
| /linux/Documentation/devicetree/bindings/input/ |
| H A D | brcm,bcm-keypad.txt | 3 Broadcom Keypad controller is used to interface a SoC with a matrix-type
6 The keypad controller can sense a key-press and key-release and report the
9 This binding is based on the matrix-keymap binding with the following
12 keypad,num-rows and keypad,num-columns are required.
14 Required SoC Specific Properties:
15 - compatible: should be "brcm,bcm-keypad"
17 - reg: physical base address of the controller and length of memory mapped
20 - interrupts: The interrupt number to the cpu.
22 Board Specific Properties:
23 - keypad,num-rows: Number of row lines connected to the keypad
[all …]
|
| /linux/Documentation/devicetree/bindings/mtd/ |
| H A D | brcm,brcmnand.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Brian Norris <computersforpeace@gmail.com>
11 - Kamal Dasu <kdasu.kdev@gmail.com>
12 - William Zhang <william.zhang@broadcom.com>
15 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
16 flash chips. It has a memory-mapped register interface for both control
23 Broadband SoC (BCM63xx), ARM based Broadband SoC (BCMBCA) and iProc/Cygnus.
27 -- Additional SoC-specific NAND controller properties --
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|
| /linux/drivers/soc/samsung/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
3 # Samsung SoC drivers
6 bool "Samsung SoC driver support" if COMPILE_TEST
12 bool "Exynos ASV ARMv7-specific driver extensions" if COMPILE_TEST
23 Support for Samsung Exynos SoC ChipID and Adaptive Supply Voltage.
33 IP-core found in modern Samsung Exynos SoCs, like Exynos850 and
49 bool "Exynos PMU ARMv7-specific driver extensions" if COMPILE_TEST
76 bool "Exynos SoC Regulator Coupler" if COMPILE_TEST
|
| /linux/Documentation/driver-api/phy/ |
| H A D | samsung-usb2.rst | 6 --------------
18 --------------------
20 - phy-samsung-usb2.c
25 of the PHY module. Depending on which SoC was chosen they execute SoC
26 specific callbacks. The specific SoC version is selected by choosing
30 - phy-samsung-usb2.h
36 ------------------
38 To support a new SoC a new file should be added to the drivers/phy
39 directory. Each SoC's configuration is stored in an instance of the
51 property is a boolean flag that determines whether the SoC has USB host
[all …]
|