| /linux/sound/soc/meson/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
13 in the Amlogic Meson8, Meson8b and GX SoC families
26 embedded in the Amlogic AXG SoC family
33 embedded in the Amlogic AXG SoC family
50 in the Amlogic AXG SoC family
58 in the Amlogic AXG SoC family
74 Select Y or M to add support for the AXG SoC sound card
83 in the Amlogic AXG SoC family
90 in the Amlogic AXG SoC family
98 in the Amlogic AXG SoC family
[all …]
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| /linux/include/uapi/linux/ |
| H A D | serial_core.h | 1 /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
19 #define PORT_RM9000 16 /* PMC-Sierra RM9xxx internal UART */
20 #define PORT_OCTEON 17 /* Cavium OCTEON internal UART */
21 #define PORT_AR7 18 /* Texas Instruments AR7 internal UART */
22 #define PORT_U6_16550A 19 /* ST-Ericsson U6xxx internal UART */
23 #define PORT_TEGRA 20 /* NVIDIA Tegra internal UART */
25 #define PORT_LPC3220 22 /* NXP LPC32xx SoC "Standard" UART */
32 #define PORT_RT2880 29 /* Ralink RT2880 internal UART */
73 /* Atmel AT91 SoC */
80 /* SH-SCI */
[all …]
|
| /linux/drivers/pci/controller/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
20 3700 SoC.
52 system-on-chips, like the Apple M1. This is required for the USB
53 type-A ports, Ethernet, Wi-Fi, and Bluetooth.
111 bool "Cavium Thunder PCIe controller to off-chip devices"
119 bool "Cavium Thunder ECAM controller to on-chip devices on pass-1.x silicon"
124 Say Y here if you want ECAM support for CN88XX-Pass-1.x Cavium Thunder SoCs.
154 in the Intel IXP4xx XScale-based network processor SoC.
191 is used on 32-bit Marvell ARM SoCs: Dove, Kirkwood, Armada 370,
213 multi-function devices.
[all …]
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| /linux/Documentation/devicetree/bindings/spi/ |
| H A D | spi-davinci.txt | 4 Keystone 2 - https://www.ti.com/lit/ug/sprugp2a/sprugp2a.pdf
5 dm644x - https://www.ti.com/lit/ug/sprue32a/sprue32a.pdf
6 OMAP-L138/da830 - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
9 - #address-cells: number of cells required to define a chip select
11 - #size-cells: should be zero.
12 - compatible:
13 - "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family
14 - "ti,da830-spi" for SPI used similar to that on DA8xx SoC family
15 - "ti,keystone-spi" for SPI used similar to that on Keystone2 SoC
17 - reg: Offset and length of SPI controller register space
[all …]
|
| /linux/Documentation/power/ |
| H A D | opp.rst | 5 (C) 2009-2010 Nishanth Menon <nm@ti.com>, Texas Instruments Incorporated
20 -------------------------------------------------
22 Complex SoCs of today consists of a multiple sub-modules working in conjunction.
23 In an operational system executing varied use cases, not all modules in the SoC
25 facilitate this, sub-modules in a SoC are grouped into domains, allowing some
41 - {300000000, 1000000}
42 - {800000000, 1200000}
43 - {1000000000, 1300000}
46 ----------------------------------------
57 (users) -> registers a set of default OPPs -> (library)
[all …]
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| /linux/Documentation/devicetree/bindings/clock/ |
| H A D | mediatek,mt8196-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/mediatek,mt8196-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Guangjie Song <guangjie.song@mediatek.com>
11 - Laura Nao <laura.nao@collabora.com>
15 PLLs -->
16 dividers -->
18 -->
26 - enum:
[all …]
|
| H A D | mediatek,mt8196-sys-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/mediatek,mt8196-sys-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Guangjie Song <guangjie.song@mediatek.com>
11 - Laura Nao <laura.nao@collabora.com>
15 PLLs -->
16 dividers -->
18 -->
22 provide most of the PLLs which are generated from the SoC's 26MHZ crystal oscillator.
[all …]
|
| /linux/Documentation/sound/soc/ |
| H A D | overview.rst | 2 ALSA SoC Layer Overview
6 provide better ALSA support for embedded system-on-chip processors (e.g.
8 subsystem there was some support in the kernel for SoC audio, however it
9 had some limitations:-
11 * Codec drivers were often tightly coupled to the underlying SoC
12 CPU. This is not ideal and leads to code duplication - for example,
13 Linux had different wm8731 drivers for 4 different SoC platforms.
18 machine specific code to re-route audio, enable amps, etc., after such an
31 features :-
36 * Easy I2S/PCM audio interface setup between codec and SoC. Each SoC
[all …]
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| /linux/Documentation/devicetree/bindings/bus/ |
| H A D | mvebu-mbus.txt | 6 - compatible: Should be set to one of the following:
7 marvell,armada370-mbus
8 marvell,armadaxp-mbus
9 marvell,armada375-mbus
10 marvell,armada380-mbus
11 marvell,kirkwood-mbus
12 marvell,dove-mbus
13 marvell,orion5x-88f5281-mbus
14 marvell,orion5x-88f5182-mbus
15 marvell,orion5x-88f5181-mbus
[all …]
|
| /linux/Documentation/devicetree/bindings/net/ |
| H A D | qcom-emac.txt | 4 internal PHY. Each device is represented by a device tree node. A phandle
5 connects the MAC node to its corresponding internal phy node. Another
11 - compatible : Should be "qcom,fsm9900-emac".
12 - reg : Offset and length of the register regions for the device
13 - interrupts : Interrupt number used by this controller
14 - mac-address : The 6-byte MAC address. If present, it is the default
16 - internal-phy : phandle to the internal PHY node
17 - phy-handle : phandle to the external PHY node
19 Internal PHY node:
20 - compatible : Should be "qcom,fsm9900-emac-sgmii" or "qcom,qdf2432-emac-sgmii".
[all …]
|
| H A D | motorcomm,yt8xxx.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Sae <frank.sae@motor-comm.com>
13 - $ref: ethernet-phy.yaml#
18 - ethernet-phy-id4f51.e91a
19 - ethernet-phy-id4f51.e91b
21 rx-internal-delay-ps:
24 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
30 tx-internal-delay-ps:
[all …]
|
| /linux/Documentation/devicetree/bindings/phy/ |
| H A D | nvidia,tegra194-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra194-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 signals) which connect directly to pins/pads on the SoC package. Each lane
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
[all …]
|
| H A D | nvidia,tegra186-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 signals) which connect directly to pins/pads on the SoC package. Each lane
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
[all …]
|
| H A D | nvidia,tegra210-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 signals) which connect directly to pins/pads on the SoC package. Each lane
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
[all …]
|
| H A D | fsl,imx8-pcie-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8 SoC series PCIe PHY
10 - Richard Zhu <hongxing.zhu@nxp.com>
13 "#phy-cells":
18 - fsl,imx8mm-pcie-phy
19 - fsl,imx8mp-pcie-phy
27 clock-names:
[all …]
|
| /linux/drivers/soc/amlogic/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
2 menu "Amlogic SoC drivers"
12 tristate "Amlogic Meson SoC Clock Measure driver"
17 Say yes to support of Measuring a set of internal SoC clocks
21 bool "Amlogic Meson GX SoC Information driver"
26 Say yes to support decoding of Amlogic Meson GX SoC family
30 bool "Amlogic Meson MX SoC Information driver"
36 Meson8b and Meson8m2 SoC family information about the type
|
| /linux/sound/soc/uniphier/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
34 tristate "UniPhier SoC internal audio codec"
37 This adds Codec driver for Socionext UniPhier LD11/20 SoC
38 internal DAC. This driver supports Line In / Out and HeadPhone.
|
| /linux/drivers/usb/phy/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
38 of the Keystone SOC.
42 depends on USB_GADGET || !USB_GADGET # if USB_GADGET=m, NOP can't be built-in
46 built-in with usb ip or which are autonomous and doesn't require any
61 AM335x SoC.
71 UTMI PHY is embedded in OMAP4430. The internal PHY configurations APIs
73 The definition of internal PHY APIs are in the mach-omap2 layer.
76 tristate "GPIO based peripheral-only VBUS sensing 'transceiver'"
83 internal transceiver via the usb_phy interface, and
98 will be called phy-omap-otg.
[all …]
|
| /linux/Documentation/devicetree/bindings/thermal/ |
| H A D | thermal-sensor.yaml | 1 # SPDX-License-Identifier: (GPL-2.0)
4 ---
5 $id: http://devicetree.org/schemas/thermal/thermal-sensor.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Amit Kucheria <amitk@kernel.org>
20 - thermal-sensor: device that measures temperature, has SoC-specific bindings
21 - cooling-device: device used to dissipate heat either passively or actively
22 - thermal-zones: a container of the following node types used to describe all
25 This binding describes the thermal-sensor.
29 devices may control one or more internal sensors.
[all …]
|
| /linux/drivers/bus/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
37 Driver for the Broadcom Set Top Box System-on-a-chip internal bus
39 and internal bus master decoding.
42 bool "Baikal-T1 APB-bus driver"
46 Baikal-T1 AXI-APB bridge is used to access the SoC subsystem CSRs.
53 errors counter. The counter and the APB-bus operations timeout can be
57 bool "Baikal-T1 AXI-bus driver"
61 AXI3-bus is the main communication bus connecting all high-speed
62 peripheral IP-cores with RAM controller and with MIPS P5600 cores on
63 Baikal-T1 SoC. Traffic arbitration is done by means of DW AMBA 3 AXI
[all …]
|
| /linux/Documentation/admin-guide/media/ |
| H A D | fimc.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 Copyright |copy| 2012 - 2013 Samsung Electronics Co., Ltd.
11 SoC Application Processors is an integrated camera host interface, color
13 data from LCD controller (FIMD) through the SoC internal writeback data
17 drivers/media/platform/samsung/exynos4-is directory.
20 --------------
22 S5PC100 (mem-to-mem only), S5PV210, Exynos4210
25 ------------------
27 - camera parallel interface capture (ITU-R.BT601/565);
28 - camera serial interface capture (MIPI-CSI2);
[all …]
|
| /linux/drivers/phy/tegra/ |
| H A D | xusb.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
20 #include <soc/tegra/fuse.h>
31 if (args->args_count != 0) in tegra_xusb_pad_of_xlate()
32 return ERR_PTR(-EINVAL); in tegra_xusb_pad_of_xlate()
34 for (i = 0; i < pad->soc->num_lanes; i++) { in tegra_xusb_pad_of_xlate()
35 if (!pad->lanes[i]) in tegra_xusb_pad_of_xlate()
38 if (pad->lanes[i]->dev.of_node == args->np) { in tegra_xusb_pad_of_xlate()
39 phy = pad->lanes[i]; in tegra_xusb_pad_of_xlate()
45 phy = ERR_PTR(-ENODEV); in tegra_xusb_pad_of_xlate()
[all …]
|
| /linux/drivers/pinctrl/mvebu/ |
| H A D | pinctrl-mvebu.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 * struct mvebu_mpp_ctrl_data - private data for the mpp ctrl operations
29 * struct mvebu_mpp_ctrl - describe a mpp control
39 * internal function, inside the SoC. Each muxable unit can be switched
62 * struct mvebu_mpp_ctrl_setting - describe a mpp ctrl setting
64 * @name: ctrl setting name, e.g. uart2, spi0 - unique per mpp_mode
69 * A ctrl_setting describes a specific internal mux function that a mpp pin
71 * register for common mpp pin configuration registers on MVEBU. SoC specific
80 * The variant can be used to combine different revisions of one SoC to a
[all …]
|
| /linux/sound/soc/codecs/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
5 # setting - SPI can't be modular so that case doesn't need to be covered.
498 tristate "Analog Devices AU1761 CODEC - I2C"
504 tristate "Analog Devices AU1761 CODEC - SPI"
541 tristate "Analog Devices ADAU7002 Stereo PDM-to-I2S/TDM Converter"
547 tristate "Analog Devices ADAU7118 8 Channel PDM-t
[all...] |
| /linux/arch/arm/boot/dts/marvell/ |
| H A D | armada-xp-98dx3336.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Marvell 98dx3336 family SoC
7 * Contains definitions specific to the 98dx3236 SoC that are not
11 #include "armada-xp-98dx3236.dtsi"
14 model = "Marvell 98DX3336 SoC";
15 compatible = "marvell,armadaxp-98dx3336", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
20 compatible = "marvell,sheeva-v7";
23 clock-latency = <1000000>;
27 soc {
28 internal-regs {
[all …]
|