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/linux/Documentation/devicetree/bindings/soc/socionext/
H A Dsocionext,uniphier-soc-glue.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-soc-glue.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier SoC-glue logic
10 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
13 SoC-glue logic implemented on Socionext UniPhier SoCs is a collection of
19 - enum:
20 - socionext,uniphier-ld4-soc-glue
21 - socionext,uniphier-pro4-soc-glue
[all …]
H A Dsocionext,uniphier-soc-glue-debug.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-soc-glue-debug.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier SoC-glue logic debug part
10 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
13 SoC-glue logic debug part implemented on Socionext UniPhier SoCs is
20 - enum:
21 - socionext,uniphier-ld4-soc-glue-debug
22 - socionext,uniphier-pro4-soc-glue-debug
[all …]
H A Dsocionext,uniphier-ahci-glue.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-ahci-glue.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier SoC AHCI glue layer
10 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
13 AHCI glue layer implemented on Socionext UniPhier SoCs is a sideband
19 - enum:
20 - socionext,uniphier-pro4-ahci-glue
21 - socionext,uniphier-pxs2-ahci-glue
[all …]
H A Dsocionext,uniphier-dwc3-glue.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-dwc3-glue.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier SoC DWC3 USB3.0 glue layer
10 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
13 DWC3 USB3.0 glue layer implemented on Socionext UniPhier SoCs is
20 - enum:
21 - socionext,uniphier-pro4-dwc3-glue
22 - socionext,uniphier-pro5-dwc3-glue
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/linux/sound/soc/meson/
H A DMakefile1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 snd-soc-meson-aiu-y := aiu.o
4 snd-soc-meson-aiu-y += aiu-acodec-ctrl.o
5 snd-soc-meson-aiu-y += aiu-codec-ctrl.o
6 snd-soc-meson-aiu-y += aiu-encoder-i2s.o
7 snd-soc-meson-aiu-y += aiu-encoder-spdif.o
8 snd-soc-meson-aiu-y += aiu-fifo.o
9 snd-soc-meson-aiu-y += aiu-fifo-i2s.o
10 snd-soc-meson-aiu-y += aiu-fifo-spdif.o
11 snd-soc-meson-axg-fifo-y := axg-fifo.o
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H A Dg12a-toacodec.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <sound/soc.h>
14 #include <sound/soc-dai.h>
16 #include <dt-bindings/sound/meson-g12a-toacodec.h>
17 #include "axg-tdm.h"
18 #include "meson-codec-glue.h"
20 #define G12A_TOACODEC_DRV_NAME "g12a-toacodec"
71 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; in g12a_toacodec_mux_put_enum()
74 if (ucontrol->value.enumerated.item[0] >= e->items) in g12a_toacodec_mux_put_enum()
75 return -EINVAL; in g12a_toacodec_mux_put_enum()
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H A Dmeson-codec-glue.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <sound/soc.h>
9 #include <sound/soc-dai.h>
11 #include "meson-codec-glue.h"
20 if (!p->connect) in meson_codec_glue_get_input()
24 if (snd_soc_dapm_to_component(w->dapm) != in meson_codec_glue_get_input()
25 snd_soc_dapm_to_component(p->source->dapm)) in meson_codec_glue_get_input()
28 if (p->source->id == snd_soc_dapm_dai_in) in meson_codec_glue_get_input()
29 return p->source; in meson_codec_glue_get_input()
31 in = meson_codec_glue_get_input(p->source); in meson_codec_glue_get_input()
[all …]
H A Daiu-acodec-ctrl.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <sound/soc.h>
9 #include <sound/soc-dai.h>
11 #include <dt-bindings/sound/meson-aiu.h>
13 #include "meson-codec-glue.h"
38 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; in aiu_acodec_ctrl_mux_put_enum()
41 mux = snd_soc_enum_item_to_val(e, ucontrol->value.enumerated.item[0]); in aiu_acodec_ctrl_mux_put_enum()
42 changed = snd_soc_component_test_bits(component, e->reg, in aiu_acodec_ctrl_mux_put_enum()
53 snd_soc_component_update_bits(component, e->reg, in aiu_acodec_ctrl_mux_put_enum()
95 /* The glue will provide 1 lane out of the 4 to the output */ in aiu_acodec_ctrl_input_hw_params()
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dsti-dwmac.txt1 STMicroelectronics SoC DWMAC glue layer controller
5 and what is needed on STi platforms to program the stmmac glue logic.
10 - compatible : "st,stih407-dwmac"
11 - st,syscon : Should be phandle/offset pair. The phandle to the syscon node which
12 encompases the glue register, and the offset of the control register.
13 - st,gmac_en: this is to enable the gmac into a dedicated sysctl control
14 register available on STiH407 SoC.
15 - pinctrl-0: pin-control for all the MII mode supported.
18 - resets : phandle pointing to the system reset controller with correct
20 - st,ext-phyclk: valid only for RMII where PHY can generate 50MHz clock or
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H A Damlogic,g12a-mdio-mux.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/amlogic,g12a-mdio-mux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MDIO bus multiplexer/glue of Amlogic G12a SoC family
15 - Neil Armstrong <neil.armstrong@linaro.org>
18 - $ref: mdio-mux.yaml#
22 const: amlogic,g12a-mdio-mux
29 - description: peripheral clock
30 - description: platform crytal
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/linux/Documentation/devicetree/bindings/usb/
H A Ddwc3-st.txt1 ST DWC3 glue logic
3 This file documents the parameters for the dwc3-st driver.
4 This driver controls the glue logic used to configure the dwc3 core on
8 - compatible : must be "st,stih407-dwc3"
9 - reg : glue logic base address and USB syscfg ctrl register offset
10 - reg-names : should be "reg-glue" and "syscfg-reg"
11 - st,syscon : should be phandle to system configuration node which
12 encompasses the glue registers
13 - resets : list of phandle and reset specifier pairs. There should be two entries, one
15 - reset-names : list of reset signal names. Names should be "powerdown" and "softreset"
[all …]
H A Domap-usb.txt1 OMAP GLUE AND OTHER OMAP SPECIFIC COMPONENTS
3 OMAP MUSB GLUE
4 - compatible : Should be "ti,omap4-musb" or "ti,omap3-musb"
5 - ti,hwmods : must be "usb_otg_hs"
6 - multipoint : Should be "1" indicating the musb controller supports
7 multipoint. This is a MUSB configuration-specific setting.
8 - num-eps : Specifies the number of endpoints. This is also a
9 MUSB configuration-specific setting. Should be set to "16"
10 - ram-bits : Specifies the ram address size. Should be set to "12"
11 - interface-type : This is a board specific setting to describe the type of
[all …]
H A Damlogic,meson-g12a-usb-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/amlogic,meson-g12a-usb-ctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Amlogic Meson G12A DWC3 USB SoC Controller Glue
11 - Neil Armstrong <neil.armstrong@linaro.org>
15 in host-only mode, and a DWC2 IP Core configured for USB2 peripheral mode
18 A glue connects the DWC3 core to USB2 PHYs and optionally to an USB3 PHY.
20 One of the USB2 PHYs can be re-routed in peripheral mode to a DWC2 USB IP.
22 The DWC3 Glue controls the PHY routing and power, an interrupt line is
[all …]
H A Drealtek,rtd-dwc3.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/realtek,rtd-dwc3.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Realtek DWC3 USB SoC Controller Glue
11 - Stanley Chang <stanley_chang@realtek.com>
14 The Realtek DHC SoC embeds a DWC3 USB IP Core configured for USB 2.0
15 and USB 3.0 in host or dual-role mode.
20 - enum:
21 - realtek,rtd1295-dwc3
[all …]
/linux/Documentation/driver-api/usb/
H A Dwriting_musb_glue_layer.rst2 Writing a MUSB Glue Layer
15 Instead, these embedded UDC rely on the USB On-the-Go (OTG)
18 Dual-Role Controller (MUSB HDRC) found in the Mentor Graphics Inventra™
21 As a self-taught exercise I have written an MUSB glue layer for the
22 Ingenic JZ4740 SoC, modelled after the many MUSB glue layers in the
25 basics of the ``jz4740.c`` glue layer, explaining the different pieces and
26 what needs to be done in order to write your own device glue layer.
28 .. _musb-basics:
33 To get started on the topic, please read USB On-the-Go Basics (see
46 ------------------------
[all …]
/linux/drivers/reset/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
12 via GPIOs or SoC-internal reset controller modules.
30 AR71xx SoC reset controller.
87 GPIOs. Typically for OF platforms this driver expects "reset-gpios"
90 If compiled as module, it will be called reset-gpio.
127 bool "Reset controller driver for Canaan Kendryte K210 SoC"
132 Support for the Canaan Kendryte K210 RISC-V SoC reset controller.
154 This driver supports switch core reset for the Microchip Sparx5 SoC.
169 This enables the reset controller driver for Nuvoton MA35D1 SoC.
178 bool "Microchip PolarFire SoC (MPFS) Reset Driver"
[all …]
/linux/drivers/ufs/host/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0+
5 # Copyright (C) 2011-2013 Samsung India Software Operations
45 This selects the Cadence-specific additions to UFSHCD platform driver.
110 tristate "TI glue layer for Cadence UFS Controller"
113 This selects driver for TI glue layer for Cadence UFS Host
123 This selects the Samsung Exynos SoC specific additions to UFSHCD
124 platform driver. UFS host on Samsung Exynos SoC includes HCI and
125 UNIPRO layer, and associates with UFS-PHY driver.
127 Select this if you have UFS host controller on Samsung Exynos SoC.
/linux/drivers/usb/dwc3/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
54 comment "Platform Glue Driver Support"
69 tristate "Samsung Exynos SoC Platform"
78 tristate "PCIe-based Platforms"
86 tristate "Synopsys PCIe-based HAPS Platforms"
113 tristate "Generic OF Simple Glue Layer"
117 Support USB2/3 functionality in simple SoC integrations.
149 NXP iMX8M Plus SoC use DesignWare Core IP for USB2/3
159 This driver handles ZynqMP SoC operations.
189 or dual-role mode.
/linux/drivers/net/mdio/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
20 loadable module or built-in.
54 interface units of the Allwinner SoC that have an EMAC (A10,
58 tristate "APM X-Gene SoC MDIO bus controller"
62 APM X-Gene SoC's.
71 controllers found in the ASPEED AST2600 SoC. This is a driver for the
72 third revision of the ASPEED MDIO register interface - the first two
94 Broadcom iProc SoC's.
109 tristate "GPIO lib-based bitbanged MDIO buses"
113 Supports GPIO lib-based MDIO busses.
[all …]
/linux/drivers/mtd/nand/raw/brcmnand/
H A Dbcma_nand.c1 // SPDX-License-Identifier: GPL-2.0-only
14 struct brcmnand_soc soc; member
41 static inline struct brcmnand_bcma_soc *to_bcma_soc(struct brcmnand_soc *soc) in to_bcma_soc() argument
43 return container_of(soc, struct brcmnand_bcma_soc, soc); in to_bcma_soc()
46 static u32 brcmnand_bcma_read_reg(struct brcmnand_soc *soc, u32 offset) in brcmnand_bcma_read_reg() argument
48 struct brcmnand_bcma_soc *sc = to_bcma_soc(soc); in brcmnand_bcma_read_reg()
57 val = bcma_cc_read32(sc->cc, offset); in brcmnand_bcma_read_reg()
65 static void brcmnand_bcma_write_reg(struct brcmnand_soc *soc, u32 val, in brcmnand_bcma_write_reg() argument
68 struct brcmnand_bcma_soc *sc = to_bcma_soc(soc); in brcmnand_bcma_write_reg()
80 bcma_cc_write32(sc->cc, offset, val); in brcmnand_bcma_write_reg()
[all …]
/linux/arch/arm/boot/dts/socionext/
H A Duniphier-pro4.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier Pro4 SoC
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/uniphier-gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "socionext,uniphier-pro4";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 #address-cells = <1>;
18 #size-cells = <0>;
[all …]
/linux/Documentation/sound/soc/
H A Doverview.rst2 ALSA SoC Layer Overview
6 provide better ALSA support for embedded system-on-chip processors (e.g.
8 subsystem there was some support in the kernel for SoC audio, however it
9 had some limitations:-
11 * Codec drivers were often tightly coupled to the underlying SoC
12 CPU. This is not ideal and leads to code duplication - for example,
13 Linux had different wm8731 drivers for 4 different SoC platforms.
18 machine specific code to re-route audio, enable amps, etc., after such an
31 features :-
36 * Easy I2S/PCM audio interface setup between codec and SoC. Each SoC
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Dkeystone-usb-phy.txt4 - compatible: should be "ti,keystone-usbphy".
5 - #address-cells, #size-cells : should be '1' if the device has sub-nodes
7 - reg : Address and length of the usb phy control register set.
10 gate on the Keystone SOC for both the USB2 and USB3 PHY. Otherwise it is just
12 phy node in the USB Glue layer driver node.
15 compatible = "ti,keystone-usbphy";
16 #address-cells = <1>;
17 #size-cells = <1>;
/linux/Documentation/devicetree/bindings/sound/
H A Dsocionext,uniphier-aio.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/sound/socionext,uniphier-aio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - <alsa-devel@alsa-project.org>
13 - $ref: dai-common.yaml#
18 - socionext,uniphier-ld11-aio
19 - socionext,uniphier-ld20-aio
20 - socionext,uniphier-pxs2-aio
28 clock-names:
[all …]
/linux/drivers/net/ethernet/arc/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
33 This selects Rockchip SoC glue layer support for the

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