Home
last modified time | relevance | path

Searched full:sdx65 (Results 1 – 22 of 22) sorted by relevance

/linux/arch/arm/boot/dts/qcom/
H A Dqcom-sdx65.dtsi3 * SDX65 SoC device tree source
9 #include <dt-bindings/clock/qcom,gcc-sdx65.h>
15 #include <dt-bindings/interconnect/qcom,sdx65.h>
68 compatible = "qcom,scm-sdx65", "qcom,scm";
73 compatible = "qcom,sdx65-mc-virt";
205 compatible = "qcom,gcc-sdx65";
232 compatible = "qcom,sdx65-usb-hs-phy",
243 compatible = "qcom,sdx65-qmp-usb3-uni-phy";
268 compatible = "qcom,sdx65-system-noc";
303 compatible = "qcom,sdx65-pcie-ep", "qcom,sdx55-pcie-ep";
[all …]
H A Dqcom-sdx65-mtp.dts11 #include "qcom-sdx65.dtsi"
18 model = "Qualcomm Technologies, Inc. SDX65 MTP";
19 compatible = "qcom,sdx65-mtp", "qcom,sdx65";
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dqcom,sdx65-tlmm.yaml4 $id: http://devicetree.org/schemas/pinctrl/qcom,sdx65-tlmm.yaml#
7 title: Qualcomm Technologies, Inc. SDX65 TLMM block
13 Top Level Mode Multiplexer pin controller in Qualcomm SDX65 SoC.
17 const: qcom,sdx65-tlmm
31 - $ref: "#/$defs/qcom-sdx65-tlmm-state"
34 $ref: "#/$defs/qcom-sdx65-tlmm-state"
38 qcom-sdx65-tlmm-state:
125 compatible = "qcom,sdx65-tlmm";
/linux/Documentation/devicetree/bindings/interconnect/
H A Dqcom,rpmh.yaml69 - qcom,sdx65-mc-virt
70 - qcom,sdx65-mem-noc
71 - qcom,sdx65-system-noc
119 - qcom,sdx65-mc-virt
/linux/drivers/clk/qcom/
H A DKconfig121 tristate "A7 PLL driver for SDX55 and SDX65"
123 Support for the A7 PLL on SDX55 and SDX65 devices. It provides the CPU with
125 Say Y if you want to support higher CPU frequencies on SDX55 and SDX65
148 tristate "SDX55 and SDX65 APCS Clock Controller"
152 Support for the APCS Clock Controller on SDX55, SDX65 platforms. The
155 such as SDX55, SDX65.
968 tristate "SDX65 Global Clock Controller"
972 Support for the global clock controller on SDX65 devices.
H A Dgcc-sdx65.c14 #include <dt-bindings/clock/qcom,gcc-sdx65.h>
1565 { .compatible = "qcom,gcc-sdx65" },
1589 .name = "gcc-sdx65",
1606 MODULE_DESCRIPTION("QTI GCC SDX65 Driver");
H A DMakefile128 obj-$(CONFIG_SDX_GCC_65) += gcc-sdx65.o
H A Dclk-rpmh.c1005 { .compatible = "qcom,sdx65-rpmh-clk", .data = &clk_rpmh_sdx65},
/linux/Documentation/devicetree/bindings/usb/
H A Dqcom,dwc3.yaml56 - qcom,sdx65-dwc3
227 - qcom,sdx65-dwc3
503 - qcom,sdx65-dwc3
H A Dqcom,snps-dwc3.yaml57 - qcom,sdx65-dwc3
212 - qcom,sdx65-dwc3
491 - qcom,sdx65-dwc3
/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,a7pll.yaml13 The A7 PLL on the Qualcomm platforms like SDX55, SDX65 is used to provide high
H A Dqcom,rpmhcc.yaml33 - qcom,sdx65-rpmh-clk
/linux/Documentation/devicetree/bindings/mfd/
H A Dqcom,tcsr.yaml34 - qcom,sdx65-tcsr
/linux/Documentation/devicetree/bindings/watchdog/
H A Dqcom-wdt.yaml40 - qcom,apss-wdt-sdx65
/linux/Documentation/devicetree/bindings/power/
H A Dqcom,rpmpd.yaml53 - qcom,sdx65-rpmhpd
/linux/Documentation/devicetree/bindings/iommu/
H A Darm,smmu.yaml53 - qcom,sdx65-smmu-500
591 - qcom,sdx65-smmu-500
/linux/Documentation/devicetree/bindings/net/
H A Dqcom,ipa.yaml53 - qcom,sdx65-ipa
/linux/Documentation/devicetree/bindings/phy/
H A Dqcom,sc8280xp-qmp-pcie-phy.yaml31 - qcom,sdx65-qmp-gen4x2-pcie-phy
/linux/drivers/pmdomain/qcom/
H A Drpmhpd.c351 /* SDX65 RPMH powerdomains */
785 { .compatible = "qcom,sdx65-rpmhpd", .data = &sdx65_desc},
/linux/drivers/net/ipa/
H A Dipa_main.c669 .compatible = "qcom,sdx65-ipa",
/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-usb.c2140 if (of_device_is_compatible(dev->of_node, "qcom,sdx65-qmp-usb3-uni-phy")) in qmp_usb_parse_dt_legacy()
2341 .compatible = "qcom,sdx65-qmp-usb3-uni-phy",
H A Dphy-qcom-qmp-pcie.c5220 .compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy",