pinctrl: qcom: Add Hawi pinctrl driver

Add pinctrl driver for TLMM block found in the Hawi SoC.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Mukesh Ojha <mukesh.ojha@o

pinctrl: qcom: Add Hawi pinctrl driver

Add pinctrl driver for TLMM block found in the Hawi SoC.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Linus Walleij <linusw@kernel.org>

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pinctrl: qcom: add sdm670 lpi tlmm

The Snapdragon 670 has an Low-Power Island (LPI) TLMM for configuring
pins related to audio. Add the driver for this.

Signed-off-by: Richard Acayan <mailingradian

pinctrl: qcom: add sdm670 lpi tlmm

The Snapdragon 670 has an Low-Power Island (LPI) TLMM for configuring
pins related to audio. Add the driver for this.

Signed-off-by: Richard Acayan <mailingradian@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>

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pinctrl: qcom: Introduce IPQ5210 TLMM driver

Qualcomm's IPQ5210 SoC comes with a TLMM block, like all other platforms,
so add a driver for it.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm

pinctrl: qcom: Introduce IPQ5210 TLMM driver

Qualcomm's IPQ5210 SoC comes with a TLMM block, like all other platforms,
so add a driver for it.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
[linusw@kernel.org: Dropped intr_target_reg]
Signed-off-by: Linus Walleij <linusw@kernel.org>

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pinctrl: qcom: Add Milos LPASS LPI TLMM

Add a driver for the pin controller in the Low Power Audio SubSystem
(LPASS) on the Milos SoC.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Signed-of

pinctrl: qcom: Add Milos LPASS LPI TLMM

Add a driver for the pin controller in the Low Power Audio SubSystem
(LPASS) on the Milos SoC.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>

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pinctrl: qcom: Add Eliza pinctrl driver

Add pinctrl driver for TLMM block found in the Eliza SoC.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.b

pinctrl: qcom: Add Eliza pinctrl driver

Add pinctrl driver for TLMM block found in the Eliza SoC.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>

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pinctrl: qcom: sm8350-lpass-lpi: Merge with SC7280 to fix I2S2 and SWR TX pins

Qualcomm SC7280 and SM8350 SoCs have slightly different LPASS audio
blocks (v9.4.5 and v9.2), however the LPASS LPI pin

pinctrl: qcom: sm8350-lpass-lpi: Merge with SC7280 to fix I2S2 and SWR TX pins

Qualcomm SC7280 and SM8350 SoCs have slightly different LPASS audio
blocks (v9.4.5 and v9.2), however the LPASS LPI pin controllers are
exactly the same. The driver for SM8350 has two issues, which can be
fixed by simply moving over to SC7280 driver which has them correct:

1. "i2s2_data_groups" listed twice GPIO12, but should have both GPIO12
and GPIO13,

2. "swr_tx_data_groups" contained GPIO5 for "swr_tx_data2" function, but
that function is also available on GPIO14, thus listing it twice is
not necessary. OTOH, GPIO5 has also "swr_rx_data1", so selecting
swr_rx_data function should not block the TX one.

Fixes: be9f6d56381d ("pinctrl: qcom: sm8350-lpass-lpi: add SM8350 LPASS TLMM")
Cc: stable@vger.kernel.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>

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pinctrl: qcom: add the tlmm driver for Kaanapali platforms

Add support for Kaanapali TLMM configuration and control via the pinctrl
framework.

Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.c

pinctrl: qcom: add the tlmm driver for Kaanapali platforms

Add support for Kaanapali TLMM configuration and control via the pinctrl
framework.

Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

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pinctrl: qcom: Add SDM660 LPASS LPI TLMM

The Snapdragon 660 has a Low-Power Island (LPI) TLMM for configuring
pins related to audio. Add the driver for this.
Also, this driver uses predefined pin_of

pinctrl: qcom: Add SDM660 LPASS LPI TLMM

The Snapdragon 660 has a Low-Power Island (LPI) TLMM for configuring
pins related to audio. Add the driver for this.
Also, this driver uses predefined pin_offsets for each pin taken from
downstream driver, which does not follow the usual 0x1000 distance
between pins and uses an array with predefined offsets that do not
follow any regular pattern [1].

[1] https://git.codelinaro.org/clo/la/kernel/msm-4.4/-/blob/LA.UM.7.2.c27-07400-sdm660.0/drivers/pinctrl/qcom/pinctrl-lpi.c#L107

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Richard Acayan <mailingradian@gmail.com>
Co-developed-by: Nickolay Goppen <setotau@mainlining.org>
Signed-off-by: Nickolay Goppen <setotau@mainlining.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

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pinctrl: qcom: Add glymur pinctrl driver

Add TLMM pinctrl driver to support pin configuration with pinctrl
framework for Glymur SoC.

Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Reviewed-by:

pinctrl: qcom: Add glymur pinctrl driver

Add TLMM pinctrl driver to support pin configuration with pinctrl
framework for Glymur SoC.

Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

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pinctrl: qcom: Add Milos pinctrl driver

Add pinctrl driver for TLMM block found in the Milos SoC.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Bjorn Andersson <andersson@kernel

pinctrl: qcom: Add Milos pinctrl driver

Add pinctrl driver for TLMM block found in the Milos SoC.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/20250702-sm7635-pinctrl-v2-2-c138624b9924@fairphone.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

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pinctrl: qcom: Add test case for TLMM interrupt handling

While looking at the X1E PDC GPIO interrupts it became clear that we're
lacking a convenient and accessible way to validate if the TLMM
inter

pinctrl: qcom: Add test case for TLMM interrupt handling

While looking at the X1E PDC GPIO interrupts it became clear that we're
lacking a convenient and accessible way to validate if the TLMM
interrupt code performing as expected.

This introduces a kunit-based "hack" that relies on pin bias/pull
configuration to tickle the interrupt logic in non-connected pins to
allow us to evaluate that an expected number of interrupts are
delivered.

The bias/pull configuration is done with mmio accesses directly from the
test code, to avoid having to programmatically acquire and drive the
pinconf interface for the test pin. This limits the scalability of the
code to targets with a particular register layout, but serves our needs
for now.

The pin to be used for testing is specified by the tester using the
"tlmm-test.gpio" module parameter.

Worth mentioning is that some of the test cases currently fails for
GPIOs that is not backed by PDC (i.e. "non-wakeup" GPIOs), as lingering
latched interrupt state is being delivered at IRQ request time.

Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
Link: https://lore.kernel.org/20250227-tlmm-test-v1-1-d18877b4a5db@oss.qualcomm.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

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pinctrl: qcom: Add MSM8917 tlmm pinctrl driver

It is based on MSM8916 driver with the pinctrl definitions from
Qualcomm's downstream MSM8917 driver.

Signed-off-by: Otto Pflüger <otto.pflueger@abscu

pinctrl: qcom: Add MSM8917 tlmm pinctrl driver

It is based on MSM8916 driver with the pinctrl definitions from
Qualcomm's downstream MSM8917 driver.

Signed-off-by: Otto Pflüger <otto.pflueger@abscue.de>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org>
Link: https://lore.kernel.org/20241215-msm8917-v9-3-bacaa26f3eef@mainlining.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

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pinctrl: qcom: Add sm8750 pinctrl driver

Add TLMM pinctrl driver to support pin configuration with pinctrl
framework for sm8750 SoC.

Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
Reviewed

pinctrl: qcom: Add sm8750 pinctrl driver

Add TLMM pinctrl driver to support pin configuration with pinctrl
framework for sm8750 SoC.

Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/20241112002843.2804490-3-quic_molvera@quicinc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

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pinctrl: qcom: add support for TLMM on SAR2130P

Add driver for the pincontrol device as present on the Qualcomm
SAR2130P platform. This is based on the msm-5.10 tree, tag
KERNEL.PLATFORM.1.0.r4-0040

pinctrl: qcom: add support for TLMM on SAR2130P

Add driver for the pincontrol device as present on the Qualcomm
SAR2130P platform. This is based on the msm-5.10 tree, tag
KERNEL.PLATFORM.1.0.r4-00400-NEO.0.

Co-developed-by: Mayank Grover <groverm@codeaurora.org>
Signed-off-by: Mayank Grover <groverm@codeaurora.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/20241018-sar2130p-tlmm-v2-2-11a1d09a6e5f@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

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pinctrl: qcom: add the tlmm driver for QCS8300 platforms

Add support for QCS8300 TLMM configuration and control via the
pinctrl framework.

Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com>
Link:

pinctrl: qcom: add the tlmm driver for QCS8300 platforms

Add support for QCS8300 TLMM configuration and control via the
pinctrl framework.

Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com>
Link: https://lore.kernel.org/20241018-qcs8300_tlmm-v3-2-8b8d3957cf1a@quicinc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

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pinctrl: qcom: add the tlmm driver for QCS615 platform

Add support for QCS615 TLMM configuration and control via the
pinctrl framework.

Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
Link: ht

pinctrl: qcom: add the tlmm driver for QCS615 platform

Add support for QCS615 TLMM configuration and control via the
pinctrl framework.

Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
Link: https://lore.kernel.org/20240920-add_qcs615_pinctrl_driver-v2-2-e03c42a9d055@quicinc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

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pinctrl: qcom: Introduce IPQ5424 TLMM driver

The IPQ5424 SoC comes with a TLMM block, like all other Qualcomm
platforms, so add a driver for it.

Co-developed-by: Varadarajan Narayanan <quic_varada@

pinctrl: qcom: Introduce IPQ5424 TLMM driver

The IPQ5424 SoC comes with a TLMM block, like all other Qualcomm
platforms, so add a driver for it.

Co-developed-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
Link: https://lore.kernel.org/20240927065244.3024604-6-quic_srichara@quicinc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

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pinctrl: qcom: Introduce SM4250 LPI pinctrl driver

Add support for the pin controller block on SM4250 Low Power Island.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-

pinctrl: qcom: Introduce SM4250 LPI pinctrl driver

Add support for the pin controller block on SM4250 Low Power Island.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/20240612-sm4250-lpi-v4-2-a0342e47e21b@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

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pinctrl: qcom: sm4450: dd SM4450 pinctrl driver

Add pinctrl driver for TLMM block found in SM4450 SoC.
Can Guo helped out in reviewing the driver.

Reviewed-by: Bjorn Andersson <andersson@kernel.org

pinctrl: qcom: sm4450: dd SM4450 pinctrl driver

Add pinctrl driver for TLMM block found in SM4450 SoC.
Can Guo helped out in reviewing the driver.

Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
Link: https://lore.kernel.org/r/20231212094900.12615-3-quic_tengfan@quicinc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

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pinctrl: qcom: Add X1E80100 pinctrl driver

Add initial pinctrl driver to support pin configuration with pinctrl
framework for X1E80100 SoC.

Co-developed-by: Abel Vesa <abel.vesa@linaro.org>
Signed-

pinctrl: qcom: Add X1E80100 pinctrl driver

Add initial pinctrl driver to support pin configuration with pinctrl
framework for X1E80100 SoC.

Co-developed-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com>
Co-developed-by: Sibi Sankar <quic_sibis@quicinc.com>
Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20231117093921.31968-3-quic_sibis@quicinc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

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pinctrl: qcom: Introduce the SM8650 Top Level Mode Multiplexer driver

Add Top Level Mode Multiplexer (pinctrl) support for the SM8650 platform.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski

pinctrl: qcom: Introduce the SM8650 Top Level Mode Multiplexer driver

Add Top Level Mode Multiplexer (pinctrl) support for the SM8650 platform.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20231106-topic-sm8650-upstream-tlmm-v3-3-0e179c368933@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

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pinctrl: qcom: sm8650-lpass-lpi: add SM8650 LPASS

Add driver for the pin controller in Low Power Audio SubSystem (LPASS)
of Qualcomm SM8650 SoC.

Notable differences against SM8550 LPASS pin control

pinctrl: qcom: sm8650-lpass-lpi: add SM8650 LPASS

Add driver for the pin controller in Low Power Audio SubSystem (LPASS)
of Qualcomm SM8650 SoC.

Notable differences against SM8550 LPASS pin controller:
1. Additional address space for slew rate thus driver uses
LPI_FLAG_SLEW_RATE_SAME_REG and sets slew rate via different
register.

2. Two new pin mux functions: qca_swr_clk and qca_swr_data

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20231027093615.140656-3-krzysztof.kozlowski@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

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pinctrl: qcom: Introduce SM6115 LPI pinctrl driver

Add support for the pin controller block on SM6115's Low Power Island.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-of

pinctrl: qcom: Introduce SM6115 LPI pinctrl driver

Add support for the pin controller block on SM6115's Low Power Island.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230722-topic-6115_lpasstlmm-v2-2-d4883831a858@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

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pinctrl: qcom: sm8350-lpass-lpi: add SM8350 LPASS TLMM

Add driver for pin controller in Low Power Audio SubSystem (LPASS). The
driver is similar to SM8250 LPASS pin controller, with difference in o

pinctrl: qcom: sm8350-lpass-lpi: add SM8350 LPASS TLMM

Add driver for pin controller in Low Power Audio SubSystem (LPASS). The
driver is similar to SM8250 LPASS pin controller, with difference in one
new pin (gpio14) belonging to swr_tx_data.

Link: https://lore.kernel.org/r/20230719192058.433517-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

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pinctrl: qcom: Add IPQ5018 pinctrl driver

Add pinctrl definitions for the TLMM of IPQ5018.

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro

pinctrl: qcom: Add IPQ5018 pinctrl driver

Add pinctrl definitions for the TLMM of IPQ5018.

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Co-developed-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
Co-developed-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
Link: https://lore.kernel.org/r/20230608122152.3930377-5-quic_srichara@quicinc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

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