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/linux/Documentation/devicetree/bindings/reset/
H A Dzynq-reset.txt1 Xilinx Zynq Reset Manager
8 - compatible: "xlnx,zynq-reset"
12 - #reset-cells: Must be 1
14 The Zynq Reset Manager needs to be a childnode of the SLCR.
18 compatible = "xlnx,zynq-reset";
20 #reset-cells = <1>;
24 Reset outputs:
25 0 : soft reset
26 32 : ddr reset
27 64 : topsw reset
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H A Dsocionext,uniphier-reset.yaml4 $id: http://devicetree.org/schemas/reset/socionext,uniphier-reset.yaml#
7 title: UniPhier reset controller
15 - description: System reset
17 - socionext,uniphier-ld4-reset
18 - socionext,uniphier-pro4-reset
19 - socionext,uniphier-sld8-reset
20 - socionext,uniphier-pro5-reset
21 - socionext,uniphier-pxs2-reset
22 - socionext,uniphier-ld6b-reset
23 - socionext,uniphier-ld11-reset
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H A Dreset.txt1 = Reset Signal Device Tree Bindings =
3 This binding is intended to represent the hardware reset signals present
4 internally in most IC (SoC, FPGA, ...) designs. Reset signals for whole
8 Hardware blocks typically receive a reset signal. This signal is generated by
9 a reset provider (e.g. power management or clock module) and received by a
10 reset consumer (the module being reset, or a module managing when a sub-
11 ordinate module is reset). This binding exists to represent the provider and
14 A reset signal is represented by the phandle of the provider, plus a reset
15 specifier - a list of DT cells that represents the reset signal within the
16 provider. The length (number of cells) and semantics of the reset specifier
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H A Dti-syscon-reset.txt1 TI SysCon Reset Controller
4 Almost all SoCs have hardware modules that require reset control in addition
5 to clock and power control for their functionality. The reset control is
12 A SysCon Reset Controller node defines a device that uses a syscon node
13 and provides reset management functionality for various hardware modules
16 SysCon Reset Controller Node
18 Each of the reset provider/controller nodes should be a child of a syscon
27 "ti,syscon-reset"
28 - #reset-cells : Should be 1. Please see the reset consumer node below
30 - ti,reset-bits : Contains the reset control register information
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H A Damlogic,meson-reset.yaml5 $id: http://devicetree.org/schemas/reset/amlogic,meson-reset.yaml#
8 title: Amlogic Meson SoC Reset Controller
17 - amlogic,meson8b-reset # Reset Controller on Meson8b and compatible SoCs
18 - amlogic,meson-gxbb-reset # Reset Controller on GXBB and compatible SoCs
19 - amlogic,meson-axg-reset # Reset Controller on AXG and compatible SoCs
20 - amlogic,meson-a1-reset # Reset Controller on A1 and compatible SoCs
21 - amlogic,meson-s4-reset # Reset Controller on S4 and compatible SoCs
22 - amlogic,c3-reset # Reset Controller on C3 and compatible SoCs
23 - amlogic,t7-reset
26 - amlogic,a4-reset
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H A Dsocionext,uniphier-glue-reset.yaml4 $id: http://devicetree.org/schemas/reset/socionext,uniphier-glue-reset.yaml#
7 title: Socionext UniPhier peripheral core reset in glue layer
10 Some peripheral core reset belongs to its own glue layer. Before using
11 this core reset, it is necessary to control the clocks and resets to
21 - socionext,uniphier-pro4-usb3-reset
22 - socionext,uniphier-pro5-usb3-reset
23 - socionext,uniphier-pxs2-usb3-reset
24 - socionext,uniphier-ld20-usb3-reset
25 - socionext,uniphier-pxs3-usb3-reset
26 - socionext,uniphier-nx1-usb3-reset
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H A Dxlnx,zynqmp-reset.yaml4 $id: http://devicetree.org/schemas/reset/xlnx,zynqmp-reset.yaml#
7 title: Zynq UltraScale+ MPSoC and Versal reset
15 The PS reset subsystem is responsible for handling the external reset
16 input to the device and that all internal reset requirements are met
19 Please also refer to reset.txt in this directory for common reset
20 controller binding usage. Device nodes that need access to reset
21 lines should specify them as a reset phandle in their corresponding
22 node as specified in reset.txt.
24 For list of all valid reset indices for Zynq UltraScale+ MPSoC
25 <dt-bindings/reset/xlnx-zynqmp-resets.h>
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H A Dsnps,hsdk-reset.txt1 Binding for the Synopsys HSDK reset controller
3 This binding uses the common reset binding[1].
5 [1] Documentation/devicetree/bindings/reset/reset.txt
8 - compatible: should be "snps,hsdk-reset".
9 - reg: should always contain 2 pairs address - length: first for reset
10 configuration register and second for corresponding SW reset and status bits
12 - #reset-cells: from common reset binding; Should always be set to 1.
15 reset: reset@880 {
16 compatible = "snps,hsdk-reset";
17 #reset-cells = <1>;
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H A Dimg,pistachio-reset.txt1 Pistachio Reset Controller
4 This binding describes a reset controller device that is used to enable and
5 disable individual IP blocks within the Pistachio SoC using "soft reset"
8 The actual action taken when soft reset is asserted is hardware dependent.
13 Please refer to Documentation/devicetree/bindings/reset/reset.txt
14 for common reset controller binding usage.
18 - compatible: Contains "img,pistachio-reset"
20 - #reset-cells: Contains 1
31 pistachio_reset: reset-controller {
32 compatible = "img,pistachio-reset";
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H A Dhisilicon,hi3660-reset.yaml4 $id: http://devicetree.org/schemas/reset/hisilicon,hi3660-reset.yaml#
7 title: Hisilicon System Reset Controller
13 Please also refer to reset.txt in this directory for common reset
15 The reset controller registers are part of the system-ctl block on
22 - const: hisilicon,hi3660-reset
24 - const: hisilicon,hi3670-reset
25 - const: hisilicon,hi3660-reset
29 description: phandle of the reset's syscon, use hisilicon,rst-syscon instead
33 description: phandle of the reset's syscon.
36 '#reset-cells':
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H A Dthead,th1520-reset.yaml4 $id: http://devicetree.org/schemas/reset/thead,th1520-reset.yaml#
7 title: T-HEAD TH1520 SoC Reset Controller
10 The T-HEAD TH1520 reset controller is a hardware block that asserts/deasserts
19 - thead,th1520-reset # Reset controller for VO subsystem
20 - thead,th1520-reset-ao
21 - thead,th1520-reset-ap
22 - thead,th1520-reset-dsp
23 - thead,th1520-reset-misc
24 - thead,th1520-reset-vi
25 - thead,th1520-reset-vp
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H A Dfsl,imx7-src.yaml4 $id: http://devicetree.org/schemas/reset/fsl,imx7-src.yaml#
7 title: Freescale i.MX7 System Reset Controller
13 The system reset controller can be used to reset various set of
14 peripherals. Device nodes that need access to reset lines should
15 specify them as a reset phandle in their corresponding node as
16 specified in reset.txt.
18 For list of all valid reset indices see
19 <dt-bindings/reset/imx7-reset.h> for i.MX7,
20 <dt-bindings/reset/imx8mq-reset.h> for i.MX8MQ, i.MX8MM and i.MX8MN,
21 <dt-bindings/reset/imx8mp-reset.h> for i.MX8MP.
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H A Dbrcm,brcmstb-reset.yaml4 $id: http://devicetree.org/schemas/reset/brcm,brcmstb-reset.yaml#
7 title: Broadcom STB SW_INIT-style reset controller
10 Broadcom STB SoCs have a SW_INIT-style reset controller with separate
12 reset lines.
14 Please also refer to reset.txt in this directory for common reset
22 const: brcm,brcmstb-reset
27 "#reset-cells":
33 - "#reset-cells"
39 reset: reset-controller@8404318 {
40 compatible = "brcm,brcmstb-reset";
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H A Dallwinner,sun6i-a31-clock-reset.yaml4 $id: http://devicetree.org/schemas/reset/allwinner,sun6i-a31-clock-reset.yaml#
7 title: Allwinner A31 Peripheral Reset Controller
20 - allwinner,sun6i-a31-ahb1-reset
21 - allwinner,sun6i-a31-clock-reset
31 "#reset-cells":
34 This additional argument passed to that reset controller is the
35 offset of the bit controlling this particular reset line in the
40 - allwinner,sun6i-a31-ahb1-reset
41 - allwinner,sun6i-a31-clock-reset
47 - "#reset-cells"
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H A Dmicrochip,rst.yaml4 $id: http://devicetree.org/schemas/reset/microchip,rst.yaml#
7 title: Microchip Sparx5 Switch Reset Controller
14 The Microchip Sparx5 Switch provides reset control and implements the following
16 - One Time Switch Core Reset (Soft Reset)
20 pattern: "^reset-controller@[0-9a-f]+$"
25 - microchip,sparx5-switch-reset
26 - microchip,lan966x-switch-reset
29 - microchip,lan9691-switch-reset
30 - const: microchip,lan966x-switch-reset
40 "#reset-cells":
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H A Dintel,rcu-gw.yaml4 $id: http://devicetree.org/schemas/reset/intel,rcu-gw.yaml#
7 title: System Reset Controller on Intel Gateway SoCs
19 description: Reset controller registers.
22 intel,global-reset:
23 description: Global reset register offset and bit offset.
31 "#reset-cells":
35 First cell is reset request register offset.
36 Second cell is bit offset in reset request register.
37 Third cell is bit offset in reset status register.
38 For LGM SoC, reset cell count is 2 as bit offset in
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H A Dnuvoton,npcm750-reset.yaml4 $id: http://devicetree.org/schemas/reset/nuvoton,npcm750-reset.yaml#
7 title: Nuvoton NPCM Reset controller
15 - nuvoton,npcm750-reset # Poleg NPCM7XX SoC
16 - nuvoton,npcm845-reset # Arbel NPCM8XX SoC
21 '#reset-cells':
35 nuvoton,sw-reset-number:
40 Contains the software reset number to restart the SoC.
41 If not specified, software reset is disabled.
46 - '#reset-cells'
54 - nuvoton,npcm845-reset
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/linux/drivers/accel/habanalabs/include/gaudi2/
H A Dgaudi2_async_ids_map_extended.h27 int reset; member
32 { .fc_id = 0, .cpu_id = 0, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
34 { .fc_id = 1, .cpu_id = 1, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
36 { .fc_id = 2, .cpu_id = 2, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
38 { .fc_id = 3, .cpu_id = 3, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
40 { .fc_id = 4, .cpu_id = 4, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
42 { .fc_id = 5, .cpu_id = 5, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
44 { .fc_id = 6, .cpu_id = 6, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
46 { .fc_id = 7, .cpu_id = 7, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
48 { .fc_id = 8, .cpu_id = 8, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
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/linux/drivers/power/reset/
H A Dat91-reset.c2 * Atmel AT91 SAM9 & SAMA5 SoCs reset code
20 #include <linux/reset-controller.h>
26 #include <dt-bindings/reset/sama7g5-reset.h>
28 #define AT91_RSTC_CR 0x00 /* Reset Controller Control Register */
29 #define AT91_RSTC_PROCRST BIT(0) /* Processor Reset */
30 #define AT91_RSTC_PERRST BIT(2) /* Peripheral Reset */
31 #define AT91_RSTC_EXTRST BIT(3) /* External Reset */
34 #define AT91_RSTC_SR 0x04 /* Reset Controller Status Register */
35 #define AT91_RSTC_URSTS BIT(0) /* User Reset Status */
36 #define AT91_RSTC_RSTTYP GENMASK(10, 8) /* Reset Type */
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/linux/drivers/reset/
H A Dreset-ti-sci.c3 * Texas Instrument's System Control Interface (TI-SCI) reset driver
14 #include <linux/reset-controller.h>
18 * struct ti_sci_reset_control - reset control structure
20 * @reset_mask: reset mask to use for toggling reset
30 * struct ti_sci_reset_data - reset controller information structure
31 * @rcdev: reset controller entity
32 * @dev: reset controller device pointer
34 * @idr: idr structure for mapping ids to reset control structures
47 * ti_sci_reset_set() - program a device's reset
48 * @rcdev: reset controller entity
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H A Dreset-ti-syscon.c3 * TI SYSCON regmap reset driver
15 #include <linux/reset-controller.h>
17 #include <dt-bindings/reset/ti-syscon.h>
20 * struct ti_syscon_reset_control - reset control structure
21 * @assert_offset: reset assert control register offset from syscon base
22 * @assert_bit: reset assert bit in the reset assert control register
23 * @deassert_offset: reset deassert control register offset from syscon base
24 * @deassert_bit: reset deassert bit in the reset deassert control register
25 * @status_offset: reset status register offset from syscon base
26 * @status_bit: reset status bit in the reset status register
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H A Dreset-scmi.c3 * ARM System Control and Management Interface (ARM SCMI) reset driver
11 #include <linux/reset-controller.h>
17 * struct scmi_reset_data - reset controller information structure
18 * @rcdev: reset controller entity
30 * scmi_reset_assert() - assert device reset
31 * @rcdev: reset controller entity
32 * @id: ID of the reset to be asserted
34 * This function implements the reset driver op to assert a device's reset
48 * scmi_reset_deassert() - deassert device reset
49 * @rcdev: reset controller entity
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H A Dcore.c3 * Reset Controller framework
25 #include <linux/reset.h>
26 #include <linux/reset-controller.h>
39 * struct reset_control - a reset control
40 * @rcdev: a pointer to the reset controller device
41 * this reset control belongs to
43 * @list: list entry for the rcdev's reset controller list
44 * @id: ID of the reset controller in the reset
49 * @array: Is this an array of reset controls (1)?
50 * @deassert_count: Number of times this reset line has been deasserted
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/linux/Documentation/devicetree/bindings/power/reset/
H A Dkeystone-reset.txt1 * Device tree bindings for Texas Instruments keystone reset
3 This node is intended to allow SoC reset in case of software reset
6 The Keystone SoCs can contain up to 4 watchdog timers to reset
7 SoC. Each watchdog timer event input is connected to the Reset Mux
8 block. The Reset Mux block can be configured to cause reset or not.
10 Additionally soft or hard reset can be configured.
14 - compatible: ti,keystone-reset
18 reset control registers.
26 - ti,soft-reset: Boolean option indicating soft reset.
27 By default hard reset is used.
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/linux/drivers/clk/visconti/
H A Dreset.c3 * Toshiba Visconti ARM SoC reset controller
16 #include "reset.h"
25 struct visconti_reset *reset = to_visconti_reset(rcdev); in visconti_reset_assert() local
26 const struct visconti_reset_data *data = &reset->resets[id]; in visconti_reset_assert()
31 spin_lock_irqsave(reset->lock, flags); in visconti_reset_assert()
32 ret = regmap_update_bits(reset->regmap, data->rson_offset, rst, rst); in visconti_reset_assert()
33 spin_unlock_irqrestore(reset->lock, flags); in visconti_reset_assert()
40 struct visconti_reset *reset = to_visconti_reset(rcdev); in visconti_reset_deassert() local
41 const struct visconti_reset_data *data = &reset->resets[id]; in visconti_reset_deassert()
46 spin_lock_irqsave(reset->lock, flags); in visconti_reset_deassert()
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